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2022-01-28mb/google/zork/var/shuboz: Add SPD ID for MT40A512M16TB-062E:RKane Chen
Add supported memory parts in "mem_parts_used.txt" and generate the SPD ID 0x04 for the parts. Shuboz memory table as follow: value Vendor Part number 0000 MICRON MT40A512M16TB-062E:J 0001 HYNIX H5AN8G6NCJR-XNC 0010 MICRON MT40A1G16KD-062E:E 0011 SAMSUNG K4AAG165WA-BCWE 0100 MICRON MT40A512M16TB-062E:R BUG=b:216571906 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Ib0100456457adabed6fd6615e0873de2cf9acb98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61373 Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-28mb/google/brya: Remove EC_GOOGLE_CHROMEEC_ACPI_MEMMAP KconfigTim Wawrzynczak
The EC_GOOGLE_CHROMEEC_ACPI_MEMMAP is intended for Chrome microchip ECs only, which have different requirements as to the amount of memory mapped space they can claim. The brya family of boards does not use any microchip ECs, therefore remove this Kconfig. BUG=b:214460174 TEST=boot brya4es to kernel, no EC errors seen in cbmem log, EC software sync still works. Change-Id: I6e9858f29d079140ec43341de90f222b03986edb Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-28mb/google/dedede/var/drawcia: Change power sequencing of Camera and VCMVarshit B Pandya
Drawcia's MIPI camera sensor and VCM both share the same reset GPIO from the PCH. The current power sequence does not take this into account, and this leads to an unbalanced ref count of the reset GPIO, which can cause one or the other of the devices to reset unexpectedly. This patch corrects that by explicitly sequencing the reset GPIO for both devices, which the builtin refcounting of this driver will automatically handle. BUG=b:214665783 TEST=Build, boot to OS and check VCM once camera stream off Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: Ib676fd1f43dbd9cf75e4aff01baab4a4bb4e2a89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-27soc/amd/sabrina/chipset.cb: update USB portsFelix Held
The corresponding mainboard design guide was used as a reference here. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie61af7dab35b560d2eec1ea62058f3a4dad5cb0f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-27soc/amd/sabrina: update PCI devices in devicetree.cbFelix Held
Also update mb/amd/chausie accordingly. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idb4dcffa48c3dbdcffb66f1398b99ee96562efb9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-27mb/google/brya/var/taniks: Enable Bayhub LV2 driverJoey Peng
Some SKUs of google/taniks have a Bayhub LV2 card reader chip, therefore enable the corresponding driver for the mainboard. BUG=b:215487382 TEST=Build FW and checking SD card reader register is correct. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I34adb122bd2edc343e894a53bc12e105f4225984 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-27mb/google/kukui: Add DRAM support for burnet/escheKevin Chiu
0x18 MICRON 4GB LP4X MT53E1G32D2NP-046 WT:B 0x19 HYNIX 4GB LP4X H54G56CYRBX247 0x1a SAMSUNG 4GB LP4X K4UBE3D4AB-MGCL 0x1b HYNIX 8GB LP4X H54G68CYRBX248 BUG=b:165768895 BRANCH=kukui TEST=emerge-jacuzzi coreboot Change-Id: Ib1c09ff2b88bf121de702985680b2388c0fb8427 Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-01-27mb/google/kukui: Add dedicated memory map for kappaKevin Chiu
Add a dedicated memory mapping table starting at index 0x40: 0x40 SAMSUNG 4GB LP4X K4UBE3D4AA-MGCR 0x41 HYNIX 4GB QDP LP4X H9HCNNNCPMALHR-NEE 0x42 MICRON 4GB LP4X MT53E1G32D4NQ-046 WT:E 0x43 MICRON 4GB LP4X MT53E1G32D2NP-046 WT:A 0x44 MICRON 4GB LP4X MT53E1G32D2NP-046 WT:B 0x45 HYNIX 4GB LP4X H54G56CYRBX247 0x46 SAMSUNG 4GB LP4X K4UBE3D4AB-MGCL 0x48 SAMSUNG 4GB LP4X K4UBE3D4AA-MGCL 0x49 MICRON 8GB LP4X MT53E2G32D4NQ-046 WT:A 0x4A HYNIX 4GB QDP LP4X H9HCNNNCPMMLXR-NEE 0x4B Micron MT29VZZZAD9GQFSM BUG=b:162379736 BRANCH=kukui TEST=emerge-jacuzzi coreboot Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I97f296cb8c35fd2f979a05d0b97a0562c1b472f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-01-27mb/google/dedede/var/metaknight: Set core display clock to 172.8 MHzDavid Wu
When using the default initial core display clock frequency, Metaknight has a rare stability issue where the startup of Chrome OS in secure mode may hang. Slowing the initial core display clock frequency down to 172.8 MHz as per Intel recommendation avoids this problem. The CdClock=0xff is set in dedede baseboard,and we overwrite it as 0x0 (172.8 MHz) for metaknight. BUG=None BRANCH=dedede TEST=Build firmware and verify on fail DUTs. Check the DUTs can boot up in secure mode well. Change-Id: I987277fec2656fe6f10827bc6685d3d04093235e Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-01-27mb/google/brya/variants/volmar: Init devicetree for volmarDavid Wu
Init basic override devicetree based on schematics BUG=b:211891086 TEST=FW_NAME="volmar" emerge-brya coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I40b364e3df2f04a6b828f4f288667b96b6e0bd22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61299 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-01-27mb/google/brya/var/brask: set tcc_offset value to 10℃David Wu
Set tcc_offset value to 10 in devicetree for Thermal Control Circuit (TCC) activation feature. This value is suggested by Thermal team. BUG=b:214890058 BRANCH=None TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I86acb172ed427d45973b9360e0413978cbd46645 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-27mb/google/zork/var/vilboz: Add new memory K4AAG165WB-BCWEFrank Wu
Add new ram_id:1100 for memory part K4AAG165WB-BCWE. BUG=b:212507858 TEST=Generate new spd file and build coreboot. Then boot from the DUT with new memory K4AAG165WB-BCWE Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I4e409a5a5a3b3d1b0013d2c020eeb4c0aeec51ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/60191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-01-26Revert "mb/google/brya/var/brask: Configure the ISOLATE pin of LAN"Alan Huang
This reverts commit 2bf2e6d1ccd87cdd8d9c189972eae89e47e542c8. According to the latest schematics, Brask supports D3-Hot for RTL8125 and does not need to operate the ISOLATE pin. BUG=b:193750191 BRANCH=None TEST=emerge-brask coreboot chromeos-bootimage Test with command suspend_stress_test Change-Id: Ica6bfb810887861f6b17ff527373824547e2406c Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-26mb/google/brya/var/kano: Reduce reset delay time to 20ms for ELAN TSDavid Wu
Set register "reset_delay_ms" to 20 to reduce power resume time. BUG=b:204009580 TEST=tested on kano Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ib0695edd7c342c65df9138b1590281c5f442769b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-26mb/google/guybrush/var/dewatt: Update Elan touchpad interrupt triggerKenneth Chan
Update Elan touchpad interrupt trigger to level low from edge low to keep consistency with Synaptics touchpad. Checked with Elan PM Iris and other projects(spherion), the touchpad can be set to edge or level low trigger. Sepherion Elan touchpad IRQ setting: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/kernel/v5.4/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi;l=415?q=mt8192-asurada.dtsi&ss=chromiumos%2Fchromiumos%2Fcodesearch:src%2Fthird_party%2Fkernel%2F BUG=b:214143249 TEST=emerge-guybrush coreboot chromeos-bootimage; Tested Elan and Synaptics touchpad wakeup from s0i3 well with proto build. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: Ifac49b131cadc1f8838bb6243ad6d17feb272bd2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-01-26mb/google/guybrush/var/dewatt: Update touchpad GPIO configurationKenneth Chan
Update GPIO configuration to fix Synaptics touchpad can't wakeup system from s0i3. BUG=b:214143249 TEST=emerge-guybrush coreboot chromeos-bootimage; Tested Synaptics touchpad wakeup from S3 with proto build. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I29734595d37283adc6fd4a0ed17f51a5c9061796 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-01-26mb/google/guybrush/dewatt: Add variant to disable HDMIZheng Bao
For one specific type of APU, it doesn't have HDMI. When we detect this APU, we need to explicitly disable HDMI in DDI settings, otherwise the system would freeze. get_cpu_count() == 4 && get_threads_per_core() == 2: This case is for 2 Core and 4 Thread CPU (2C/4T for short). get_cpu_count() == 2: This is for 2C/2T. This is for a possible future case. BUG=b:208677293 Change-Id: I8d0fa96818a768b7960d92821b927dbc622675ae Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
2022-01-25mb/google/guybrush/var/nipperkin: Add Board values for eDP tuningZheng Bao
Reference test document, update tuning registers from pass experiment setting of phy_settings. The document about eDP tuning can be gotten from the issue tracker of this ticket, at the issue tracker b/203061533#comment6. BUG=b:203061533 Change-Id: I7aa8c594d9f5caa6b2523dac079aef89e623c56f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-01-25mb/system76: Enable SrcClk pin for CPU PCIe RPsTim Crawford
This reverts commit bd9b044a96cc ("mb/system76: rtd3: Remove SrcClk pin on CPU RP"). Previously, RTD3 expected a PCH index for the root port and did not work with the CPU PCIe RP present on TGL, so SrcClk pin was disabled. Set them now that RTD3 supports mapping the index for the CPU RP. Change-Id: Ia7519b9f5a2be52cd5575615c28d20371a26996b Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2022-01-25mb/google/brya/var/taniks: Modify DPTF settings for taniksJoey Peng
Update DPTF settings provided by thermal team BUG=b:215033682 TEST=build and tested on taniks board Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Ic6860980b06e876dd4c21af26752ab6c1a3f7fff Reviewed-on: https://review.coreboot.org/c/coreboot/+/61337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-25mb/google/brya/var/taniks: swap TPM i2c with TS i2c for next buildJoey Peng
Taniks is going to exchange i2c port for touchscreen and cr50. BUG=b:215039999 TEST=emerge-brya coreboot Cq-Depend:chromium:3397562 Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I179949887f6d8f4bbdff7d806319e2ac368ebc2c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-25mb/google/brya/var/taniks: Run time probe for NVMe SSD and MMCJoey Peng
Taniks will use two PCIE port signals with one slot, one CLK and one CLKREQ at next build. In order to accommodate this, probe statements are added to the devicetree. This only affects NVME SSD and EMMC. BUG=b:215040000 TEST=Build FSP with debug output enabled, and observe the correct root ports being initialized depending on the FW_CONFIG values for BOOT_EMMC and BOOT_NVME. Cq-Depend:chromium:3397561 Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I2ead505088f19fd3bf9768b541838395c82ef051 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-01-25mb/siemens/mc_ehl: Prevent reset when TCO expiresWerner Zeh
In order to guarantee data integrity an expired TCO must not hard reset the board. Select the Kconfig switch to prevent this reset. Change-Id: I04080c6bcd486e3a406438cc7a703165bb6945a0 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-01-25soc/intel/adl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik
Since Tiger Lake platform, the HECI1 device can be disabled on Alder Lake platform using two different mechanism: A. Using PMC IPC command 0xA9. B. Sending SBI message under SMM. In current scope of Alder Lake the default implementation is using (B) sending sbi message under SMM. A follow up patch to add the possible options and let platform to choose the applicable one. List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. 3. Default enable HECI1 device in `chipset.cb` to ensure the HECI1 device can undergo the PCI enumeration and later based on the mainboard policy the HECI1 device can be disabled. Mainboards that choose to make HECI1 enable during boot don't override `DISABLE_HECI1_AT_PRE_BOOT` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie673e634fbc0bdece419c379d417b08dfb4819e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-25mb/google/brya/var/volmar: Enable EC keyboard backlightDavid Wu
Enable EC keyboard backlight for volmar. BUG=b:211891086 TEST=FW_NAME=volmar emerge-brya coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I24ec7c8ca770cb438aabcf16b252032eef6d734d Reviewed-on: https://review.coreboot.org/c/coreboot/+/61298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-01-25mb/google/brya/variants/volmar: Configure GPIOs according to schematicsDavid Wu
Update initial gpio configuration for volmar BUG=b:211891086 TEST=FW_NAME=volmar emerge-brya coreboot Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I1bd3f1b3807b546d5a827ac89f0dc9bc8aaec40a Reviewed-on: https://review.coreboot.org/c/coreboot/+/61206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-01-25mainboard/asus/p8x7x-series: Add new variant P8Z77-MKeith Hui
Constructed out of a mix of autoport results, p8z77-m_pro, and tool dumps. Working: - Core i7-3770K CPU - SeaBIOS 1.13.0 boot to Linux 5.4.24 and Windows 10 1903 (all further tests are under these versions) - USB2 / USB3 - SATA - Gigabit ethernet - CPU temp sensors (memtest86+ 5.0.1) - Hardware monitoring under Linux - Native and MRC raminit - PCIe GPU in both "PCIEX16" slots (16x/4x, nVidia Quadro 600) - Integrated graphics with Intel OpROM and libgfxinit (all ports) - Serial port - Windows with libgfxinit framebuffer - 2ch sound playback, Linux and Windows Not working: - PS/2 mouse - 6ch analog audio out - PCI POST card in PCI slot Untested: - PS/2 keyboard - Internal USB3 ports - Digital audio out Change-Id: If756e791ddce747cb1706414be8e41e83f88922b Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-25mb/amd/chausie: add mainboard as copy of mb/amd/majolicaFelix Held
To have the new AMD Sabrina SoC code tested, add the AMD Chausie mainboard as a copy of Majolica. This patch also changes the name from Majolica to Chausie, selects the Sabrina SoC instead of the Cezanne SoC and comments out the APCB_SOURCES since those aren't available in the 3rdparty/blobs repository yet. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic7b18f7a6ae5b8365234dd1227e0b1f7f37279da Reviewed-on: https://review.coreboot.org/c/coreboot/+/61079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-24mb/google/brya/var/banshee: Configure TPM I2C BUSIvy Jian
Add I2C bus for banshee in Kconfig BUG=b:214871796 TEST=emerge-brya coreboot Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I67592051b367d5a5715f8d1253ea0c11d2deb1c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-24mb/google/brya/var/banshee: update overridetreeIvy Jian
Update override devicetree based on schematics BUG=b:214871796 TEST=emerge-brya coreboot Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I05b63ebcded2f37dfb0f6c428e1fb993f476006a Reviewed-on: https://review.coreboot.org/c/coreboot/+/61269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-24mb/google/brya: Alphabetize BOARD_GOOGLE_* in Kconfig.nameTim Wawrzynczak
Change-Id: I624dd67b6ce9b87a6031b5467eacb9a8d7cda1cd Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-24mb/google/brya/var/{taeko, taeko4es}: Modify touchpad i2c signalJoey Peng
Modify i2c signal to meet touchpad vendor spec. Please see issue tracker for more details. BUG=b:215487482 TEST=emerge-brya coreboot and check measured waveform in spec Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Ib3797d4e232654ada97092d9f2742ca040d0f0e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-24mb/system76/lemp10: Remove incorrect SPD address 0x50Tim Crawford
The Lemur Pro, with its mixed memory topology, only has a DIMM at address 0x52. Change-Id: Iecea8c70c7fd40943d86f8918f8e3b384538b5c3 Fixes: 4dcee4f21db5 ("mb/system76/lemp10: Add System76 Lemur Pro 10") Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-01-24mb/google/guybrush: Change DDI settings for guybrush variantsZheng Bao
Like the variant function to change DXIO settings, add a similar weak function to modify the DDI settings. Currently we follow the old way. Later we will find out a better way to avoid using weak function. Change-Id: I9898d717bc3025ea1ddc3b0db41325083324ed57 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
2022-01-22mb/system76/lemp9: Make GPIO for touchpad interrupt level triggeredJeremy Soller
Fixes commit 6bcaf6f (mb/system76/lemp9: Configure IRQs as level triggered for HID over I2C), which changed the interrupt configuration in the device tree but not in the GPIO definitions. Tested on a System76 Lemur Pro (lemp9), multi-touch I2C-HID was working. Signed-off-by: Jeremy Soller <jeremy@system76.com> Change-Id: I7f0559675a65453a1ad071f96049549a2dc21378 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-01-22mb/google/guybrush/var/nipperkin: turn on WLAN ASPM L1ssKevin Chiu
BUG=b:198258604 BRANCH=guybrush TEST=emerge-guybrush coreboot WLAN works properly in OS Change-Id: Ie1f295eaa57af7c2942e1807b3a0c4dcd89cd696 Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-01-22mb/intel/adlrvp: Add missing CAM1 RST GPIO for ADL-NUsha P
Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I79f2206bee5403c3fb1c999918fbd2177d0d07ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/61163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-01-21mb/system76/*: Enable measured bootTim Crawford
Tested by checking PCR-2 data is recorded in cbmem log. Change-Id: I70cb9a93de44e75f3a3ed24979c243fccea1213d Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-01-21mb/prodrive/atlas: Configure GPIO as per Atlas boardLean Sheng Tan
Update GPIO settings as per schematics v3. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I685d0b7274e3a6e707fec37d051f4818860169ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/61116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-21mb/system76/gaze15: Set _UID for touchpad devicesTim Crawford
The _UID must be unique as these devices use the same _HID. Fixes BSOD when booting Windows 10. Change-Id: I67fda892a496dc9e5a6fa5e133ff0b35cde8fce7 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-01-21mb/google/brya/var/gimble{4es}: Decrease touchscreen T3 timing to 200msScott Chao
We set T3 as 300ms to meet Elan's spec, but the resume/suspend times are greater than 500ms, which is the spec for Chromebooks. The actual kernel timing has been measured, and given the ACPI delay after deasserting reset in addition to the delay until the kernel driver accesses the device, delaying only 200ms in the ACPI method is also sufficient to meet the 300ms requirement. BUG=b:210772498 BRANCH=none TEST=build and test touchscreen function on DUT. TEST=suspend, wake DUT and check touchscreen function. Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I4bb4eda09686cb59b6e19c741aa2b78d84332d2a Reviewed-on: https://review.coreboot.org/c/coreboot/+/60270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-01-21mb/google/brya/var/kano: Prevent camera LED blinking during bootJim Lai
Camera LED blinks as sensor is being probed during kernel boot, which misleads user to belive camera has been turned on. Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips initial probe during kernel boot and prevent privacy LED blink. BUG=b:214155527 TEST=Build and boot Kano to OS. Verify entries in SSDT and monitor LED during boot. Signed-off-by: Jim Lai <jim.lai@intel.com> Change-Id: I92f1e88d0fcce49660a95d4402c8c4161e320168 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61109 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-21mb/google/puff/var/dooly: Add fw_config probe for ALC5682-VD/ALC5682-VSTony Huang
ALC5682-VD/ALC5682-VS use different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:210501484 BRANCH=puff TEST=build Change-Id: I84bc378d6b00828366309be7dbf56a61702a14da Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2022-01-21soc/intel/ehl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik
The only option to make HECI1 function disable on Elkhart Lake SoC platform is using SBI under SMM mode. List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I76c625e6221fdef1343599e7dbc7739caa91bf98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
2022-01-20mb/google/brya/var/banshee: update gpio settingsIvy Jian
Configure GPIOs according to schematics BUG=b:214871796 TEST=emerge-brya coreboot Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: Id6862ff442310953b4749cef7880814f3c3f6d60 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-20mb/google/brya/var/banshee: Add SODIMM supportEric Lai
Banshee will use SODIMM. Add memory.c to override baseboard. BUG=b:208910227 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I4d2fe986b786b3553b67910b589fce12647ee69a Reviewed-on: https://review.coreboot.org/c/coreboot/+/61192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-20mb/google/brya: Add MEMORY_SODIMM and MEMORY_SOLDERDOWN configEric Lai
MEMORY_SOLDERDOWN puts SPD in cbfs and read part number from CBI. MEMORY_SODIMM puts SPD cache in FMAP. BUG=b:208910227 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Idab48293fb5b584ecb4c8f270d2c376456954553 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-20mb/google/brya: Create banshee variantIvy Jian
Create the banshee variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:214871796 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_BANSHEE Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: Ib4f943a109f945204a9b0a8de9b99580bf01c87e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-19mb/google/brya/var/{taeko, taeko4es}: Add gpio.c in romstageKevin Chang
Add file gpio.c in romstage. BUG=b:213828931 TEST=Build FW and system can power on normally. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: Ie868fe7ada9deb8918d6c7ba538332cbe539ee44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-19mb/google/cherry: add configuration for dojoKevin Chiu
BUG=b:211528578 TEST=emerge-cherry coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I3bd9803b4e47882df9fe351229478e4cb1630363 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-01-19mb/google/dedede/var/bugzzy: Add SAR sensorSeunghwan Kim
Present the Semtech SX9360 SAR sensor that protects the LTE antenna. The sensor is connected to i2c bus I2C1. BUG=b:194318328 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Change-Id: I9feef9d132c60738bafb22ceb7d3468c798fab9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59609 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-18mb/intel/adlrvp: Add wake events for AC connect/disconnectKrishna Prasad Bhat
Enable S3/S0ix wake events for AC connect/disconnect on Alder Lake RVP. BUG=None BRANCH=None TEST=Verify board wakes from S0ix on AC connect/disconnect. Change-Id: Iaf92821fd69a59624e58cb8af3896e2b6998723f Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-01-18mb/intel/adlrvp_n: Configure EC in RW GPIOKrishna Prasad Bhat
EC_IN_RW signal from EC GPIO is connected to GPIO E7 of SOC. This GPIO can be used to check EC status trusted (LOW: in RO) or untrusted (HIGH: in RW). BRANCH=None BUG=None TEST=Issue manual recovery and confirm DUT is entering recovery mode. Change-Id: Ib8b6be9fcda24bd2bb479b5b6c01f24a6e9c7b1f Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-01-18mb/google/brya/var/brask: Turn on I2C1 for TPMAlan Huang
The latest schematics changes the TPM I2C from I2C3 to I2C1. This patch turns on I2C1 and turns off I2C3. BUG=b:211886429 TEST=Test if proto 1 can boot into Chrome OS successfully. Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Change-Id: I0e94c900b48adf10880aae2abb47e08d1bd9e19b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-01-17mb/google/auron: Remove addition of EC firmware to buildTim Wawrzynczak
In https://crrev.com/c/3069716, the samus EC firmware was removed from the `main` branch, therefore in order to update the `chromeec` 3rdparty submodule, the automatic build and inclusion of samus EC firmware into coreboot's `master` branch has to be dropped as well. Change-Id: I6fcdd3b7925b6ec33ba48892ed750c29bb60634c Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-01-17mb/google/brya/variants/*: Add cpu pcie rp flagsTracy Wu
Along with commit f94405219c (soc/intel/alderlake: Hook up FSP-S CPU PCIe UPDs), we need to set cpu pcie rp flags in devicetree now. This CL is to add proper cpu pcie flags (PCIE_RP_LTR and PCIE_RP_AER) in all intel projects or system will be blocked at PKGC2R with root port LTR not enable. BUG=b:214009181 TEST=Build and DUT (Kano) can enter deeper PKGC state normally. Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com> Change-Id: I0d8721bf1454448b7fc14655f0e4513001469a18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-17mb/google/brya/var/taeko4es: Enable Bayhub LV2 driverKevin Chang
Some SKUs of google/taeko4es have a Bayhub LV2 card reader chip, therefore enable the corresponding driver for the mainboard. BUG=b:204343849 TEST=Build FW and checking SD card reader register is correct. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I3d2ea3db9df38e7b0cac4c32e1fca579ff43e5bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/61115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-17mb/google/dedede/var/bugzzy: Set core display clock to 172.8 MHzSeunghwan Kim
When using the default initial core display clock frequency (648MHz), Jasper Lake board might have a rare stability issue where the startup of Chrome OS in secure mode may hang during re-initializing display in kernel graphic driver. Bugzzy didn't show this problem so far, but Intel recommends slowing the initial core display clock frequency down to 172.8 MHz to prevent this potential problem. Depend on CL: https://review.coreboot.org/c/coreboot/+/60009 The CdClock=0xff is set in dedede baseboard, and we overwrite it as 0x0 (172.8 MHz) for bugzzy. BUG=None BRANCH=dedede TEST=Build firmware and check the DUTs can boot up in secure mode well. Change-Id: I592b2d7c814881074bd2fef9906f2450326c1fcd Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-01-17soc/intel/cnl: Use Kconfig to disable HECI1Subrata Banik
This patch makes DISABLE_HECI1_AT_PRE_BOOT=y default for Cannon Lake and ensures disable_heci1() is guarded against this config. Also, makes dt CSE PCI device `on` by default. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Idd57d2713fe83de5fb93e399734414ca99977d0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/60725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-01-17Revert "mb/google/dedede/var/beadrix: Remove SD controller"Teddy Shih
This reverts commit bcd7873ea80be0ee576a10e6a11b7dcf8294ffb5. Reason for revert: It makes beadrix can't boot to os without depthcharge change. The depthcharge change related with fw_config and will effect other variants. ================ error log ================ ... Starting depthcharge on Beadrix... src/vboot/util/flag.c:50 flag_install(): Gpio already set up for flag 5. =========================================== BUG=b:204882915 BRANCH=None TEST=Build and boot into OS. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: Id5e76fc78a56d30caf9f805a8a430f176a653bbe Reviewed-on: https://review.coreboot.org/c/coreboot/+/60849 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Henry Sun <henrysun@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-17mb/google/dedede/var/beadrix: Add memory part and generate DRAM IDTeddy Shih
This change adds memory part used by variant beadrix to mem_part_used.txt and generates DRAM ID allocated to the part. BUG=b:204882915, b:210123929 BRANCH=None TEST=Run part_id_gen to generate SPD id Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: Ibff150bb4e742f32641da661cfca6594d18c52e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60242 Reviewed-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-17mb/google/brya/var/agah: update gpio overrideTony Huang
Configure GPIOs according to schematics BUG=b:210970640 TEST=emerge-brya coreboot Change-Id: Icfd1e09761e51aca9c23f3ab340adac7a66a3ada Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-17src: Remove unused <cbfs.h>Elyes HAOUAS
Found using: diff <(git grep -l '<cbfs.h>' -- src/) <(git grep -l 'cbfs_allocator_t\|cbfs_load\|cbfs_ro_load\|cbfs_type_load\|cbfs_ro_type_load\|cbfs_unverified_area_load\|cbfs_map\|cbfs_ro_map\|cbfs_type_map\|cbfs_ro_type_map\|cbfs_unverified_area_map\|cbfs_alloc\|cbfs_ro_alloc\|cbfs_type_alloc\|cbfs_ro_type_alloc\|cbfs_unverified_area_alloc\|cbfs_cbmem_alloc\|cbfs_ro_cbmem_alloc\|cbfs_type_cbmem_alloc\|cbfs_ro_type_cbmem_alloc\|cbfs_unverified_area_cbmem_alloc\|cbfs_preload\|cbfs_unmap\|cbfs_prog_stage_load\|cbfs_get_size\|cbfs_ro_get_size\|cbfs_get_type\|cbfs_ro_get_type\|cbfs_type\|cbfs_file_exists\|cbfs_ro_file_exists\|mem_pool\|cbfs_cache\|cbfs_boot_device\|cbfs_boot_device_find_mcache\|cbfs_boot_device\|cbfs_get_boot_device\|cbfs_init_boot_device\|cbfs_boot_lookup\|cbfs_alloc\|cbfs_unverified_area_alloc\|cbfs_default_allocator_arg\|cbfs_default_allocator\|cbfs_cbmem_allocator\|cbfs_alloc\|cbfs_ro_alloc\|cbfs_type_alloc\|cbfs_ro_type_alloc\|cbfs_unverified_area_alloc\|cbfs_map\|cbfs_ro_map\|cbfs_type_map\|cbfs_ro_type_map\|cbfs_unverified_area_map\|cbfs_load\|cbfs_type_load\|cbfs_ro_load\|cbfs_ro_type_load\|cbfs_unverified_area_load\|cbfs_cbmem_alloc\|cbfs_ro_cbmem_alloc\|cbfs_type_cbmem_alloc\|cbfs_ro_type_cbmem_alloc\|cbfs_unverified_area_cbmem_alloc\|cbfs_get_size\|cbfs_ro_get_size\|cbfs_get_type\|cbfs_ro_get_type\|cbfs_file_exists\|cbfs_ro_file_exists\|cbfs_mdata\|cbfs_find_attr\|cbfs_file_hash' -- src/)|grep "<" Change-Id: Ib4dca6da1eb66bbba5b6e94fd623f4fcfc2f0741 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-16soc/intel/skl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik
List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. 3. Make dt CSE PCI device `on` by default. 4. Mainboards set DISABLE_HECI1_AT_PRE_BOOT=y to make Heci1 function disable at pre-boot instead of the dt policy that uses `HeciEnabled = 0`. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I5c13fe4a78be44403a81c28b1676aecc26c58607 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-14mb/google/brya/var/redrix{4es}: Add host device event supportWisley Chen
Adding this host event to the EC SCI event and wake masks allows the system to generate an SCI and/or wake when this event happens. BUG=b:206012072 TEST=build Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I4f48244a4fca750a9de2ecc20f24786034d45b8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/61072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-14mb/google/brya/var/redrix{4es}: Set tcc_offset value to 3Wisley Chen
The redrix thermal team has determined that the TCC circuit trip temperature should be set to 97C, therefore, because the offset is subtracted from 100C, set the `tcc_offset` register in the devicetree to 3. BUG=b:200134784 TEST=build and verified by thermal team Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: Ifb63d63bc741b2a402328f256b43bc83e0a88a9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-14mb/google/brya/var/anahera{4es}: Set tcc_offset value to 3Wisley Chen
The anahera thermal team has determined that the TCC circuit trip temperature should be set to 97C, therefore, because the offset is subtracted from 100C, set the `tcc_offset` register in the devicetree to 3. BUG=b:214088543 TEST=build and verified by thermal team Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I25b8a3d9e5fe28e9497b735c50a09994092b2243 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-14mb/google/brya/var/felwinter: Update USB Type-C PLDEric Lai
After kernel change landed on Chromium tree. https://lore.kernel.org/r/20210407065555.88110-5-heikki.krogerus@linux.intel.com USB driver will use PLD to match the Type-C port. PLD needs to start from 1. BUG=b:214460183 TEST=boot into OS without kernel panic. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I1493e46f8881b2f688f41f32755d4cf5a87e7656 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-14mb/google/brya/var/felwinter: Update audio_amp fw config field nameEric Lai
https://github.com/thesofproject/linux/pull/3271 Felwinter will use the OEM string for SOF tplg loading. Update the name that match to the kernel driver. BUG=b:210061842 TEST=dmidecode can show AUDIO_AMP-MAX98360_ALC5682VS_I2S_2WAY. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib6114d047762ba26071c9cdc6c43d80f933c1eb9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61070 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-14mb/google/brya0: Enable CNVi DDR RFIM for brya0 variantRonak Kanabar
DDR interfaces emit electromagnetic radiation which can couple to the antennas of various radios that are integrated in the system, and cause radio frequency interference (RFI). The DDR Radio Frequency Interference Mitigation (DDR RFIM) feature is primarily aimed at resolving narrowband RFI from DDR4/5 and LPDDR4/5 technologies for the Wi-Fi high and ultra-high bands (~5-7 GHz). This patch sets CnviDdrRfim UPD and enables CNVI DDR RFIM feature for brya0 variant. Refer to Intel doc:640438 and doc:690608 for more details. BUG=b:201724512 BRANCH=None TEST=Build and boot with debug FSP and verify CnviDdrRfim UPD value. Change-Id: I6ad826d0039e400f219c2d407c51762c1751a909 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-01-14mb/google/brya: move SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES to commonEric Lai
ADL support USB4/TBT. Select it will reserve PCI buses and hotplug mem and prefetch mem. BUG=b:206739931 TEST=build PASS. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I1171981c1318c2ecb65ba7959c4de9b5e179514e Reviewed-on: https://review.coreboot.org/c/coreboot/+/60885 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-14soc/intel/jsl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik
List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib9fb554c8f3cfd1e91bbcd1977905e1321db0802 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-14soc/intel/tgl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik
List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4a81fd58df468e2711108a3243bf116e02986316 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-14mb/google/brya/var/agah: update overridetreeTony Huang
Init basic override devicetree based on initial schematics BUG=b:210970640 TEST=emerge-brya coreboot Change-Id: I7b7badacce27dd7da4f138c6f2465af518715e7f Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60837 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-14soc/amd/cezanne: factor out eSPI SPI2 pads configuration functionsFelix Held
verstage_mainboard_espi_init in mb/guybrush/verstage.c still accesses some of the registers directly. BUG=b:183149183 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2f48d1c62b48866d8d942f1586bcb72017b8dd72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-01-14soc/intel/tigerlake: add devicetree option PcieRpSlotImplementedMichael Niewöhner
Add the UPD PcieRpSlotImplemented as devicetree option. To keep the PI bit set for any slots of already existing boards, add set the option PcieRpSlotImplemented=1 where appropriate. Change-Id: Ia6f685df3c22c74ae764693329a69817bf3cd01d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-13mb/google/brya: Adjust CSE RO and Data partition in the CSE regionSridhar Siricilla
The patch adjusts CSE region's internal partitions' (CSE RO and Data partition) sizes to match with sizes of MFIT generated CSE Region's internal partitions. BUG=b:213993778 TEST=Generate coreboot for Brya and verify with MFIT generated coreboot. Cq-Depend: chrome-internal:4452789 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I5418c02f83134814e3f9959ee8c8da32ce8c7bec Reviewed-on: https://review.coreboot.org/c/coreboot/+/60951 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-13mb/google/brya: Variants with ESx SoC use NEM for CARSubrata Banik
This patch ensures all brya variants with Alder Lake ESx SoC are using NEM by default for CAR set up. Default CAR configuration for QS SoC is eNEM. BUG=b:168820083 TEST=Able to build and boot brya0 variant using eNEM mode. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib04bec188bdfde67c408fcd6b0603a5c2fb0fc97 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-13mb/google/brya/var/felwinter: Update ELAN touch HIDEric Lai
Per customer spec, change ELAN touch HID from ELAN9050 to ELAN9008. BUG=b:214010928 TEST=touch screen is functional. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ia95fdb378aaf241e38c0beb8ec392d57d77dc4db Reviewed-on: https://review.coreboot.org/c/coreboot/+/61027 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-12mb/google/brya/var/taeko: Modify power sequence for SSD deviceKevin Chang
In order to avoid having the FSP fail to detect the SSD device downstream of the RP, its PERST# must be deasserted earlier in the boot flow, therefore move PERST# deassertion to a romstage GPIO table. BUG=b:213828931 TEST=Build FW and run stress exceed 1000 cycles. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I4e5eed7db16e1420ccbc22a5c30b00bedd190a2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/60956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-12mb/google/glados/variants/sentry: Increase CPU critical temp threshold to 105CSumeet Pawnikar
During certain kind of test scenario, observed that CPU temperature spikes till 98C and based on current thermal critical policy temperature threshold of CPU set to 98C, it initiates the system wide abrupt shutdown. To avoid this kind of abrupt system shutdown, update cpu critical temperature threshold from 98C to 105C. BUG=b:213476881 BRANCH=glados TEST=Built and booted on glados Change-Id: I56df9285b3c247866a5bfa6dc59d1856544de41c Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-12mb/prodrive/atlas: Add new mainboard based on adlrvpLean Sheng Tan
This is a initial mainboard code cloned from adlrvp aimed to serve as base for further mainboard check-ins. This commit copies the mainboard directory and adjusts the naming to match the new board's name. Besides, This commit also trims down major parts of adlrvp code except some of ADL-P DDR5 RVP as Atlas is using it as main reference. Follow-up commits will introduce the needed changes for the new mainboard. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Ia3129f68c73969604edcd290c3e50ad219cf88d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60899 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-12mb/google/dedede/var/beadrix: Configure GPIO settingsTeddy Shih
Override GPIO pad configurations based on the beadrix's schematic. BUG=b:204882915 BRANCH=None TEST=Built test coreboot image Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I53fc8088ff8ebb2790ac8cd68186cf9de908b414 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-01-12mb/google/dedede/var/beadrix: Correct memory settingsTeddy Shih
Based on the beadrix's schematic, generate memory settings. BUG=b:204882915, b:210123929 BRANCH=None TEST=Built test coreboot image Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I935581fbf21be4820b03a608ea5bd60b1c000baa Reviewed-on: https://review.coreboot.org/c/coreboot/+/60244 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-12mb/google/brya: Move gpio_pm settings for brya variants to baseboardsTim Wawrzynczak
The factory versions (minor version 22) of cr50 FW have an issue with producing short interrupt pulses, which can be missed by the ADL PCH if autonomous GPIO power management is enabled, therefore instead of continually adding the setting to all the variants, move it to the baseboard instead. Change-Id: I337f1e9e8f958c02bb73e6701a06c0b88a4757d7 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-12mb/google/guybrush/var/dewatt: Update unused GPIO pinsKenneth Chan
According to H/W schematics, fingerprint, SD controller, WWAN/LTE and PEN modules are not stuffed and hence the following GPIOs are marked as not connected: GPIO_3 : TP247 GPIO_4 : TP218 GPIO_5 : TP220 GPIO_8 : TP245 GPIO_11: TP244 GPIO_17: TP194 GPIO_18: TP195 GPIO_21: TP243 GPIO_24: TP196 GPIO_31: TP50 GPIO_42: TP219 GPIO_69: TP217 GPIO_115: TP235 GPIO_116: TP205 GPIO_140: TP226 GPIO_142: TP225 GPIO_144: TP227 BUG=b:204155627 TEST=emerge-guybrush coreboot chromeos-bootimage Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I552fd6af1cd827e4e41be1a954bf95c3afbb6a86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-01-12mb/google/guybrush/var/dewatt: Support ALC5682I-VS codecKenneth Chan
ALC5682I-VS codec will be used in EVT, replacing ALC5682I-VD. BUG=b:211835769 TEST=emerge-guybrush coreboot chromeos-bootimage; HW reworked a proto MB with ALC5682I-VS, build and check "i2cdetect -r -y 2", dmesg. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: Ib1a82285b60c6d5d474ead8643a826e36f56f5b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-01-11mb/google/brya/var/volmar: Generate SPD ID for supported partsDavid Wu
Add supported memory parts in mem_parts_used.txt, and generate SPD id for these parts. MT53E512M32D1NP-046 WT:B (Micron) MT53E1G32D2NP-046 WT:B (Micron) H54G46CYRBX267 (Hynix) H54G56CYRBX247 (Hynix) K4U6E3S4AB-MGCL (Samsung) K4UBE3D4AB-MGCL (Samsung) BUG=none TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ic5b45ec83d0d7e0e1d16cb1afae501f06ee1f36a Reviewed-on: https://review.coreboot.org/c/coreboot/+/60962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-01-11soc/intel/alderlake: Factor out A0 stepping workaroundAngel Pons
Move the `configure_pmc_descriptor()` function to SoC scope instead of having two identical copies in mainboard scope. Add a Kconfig option to allow mainboards to decide whether to implement this workaround. Change-Id: Ib99073d8da91a93fae9c0cebdfd73e39456cdaa8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-11mb/google/brya: Check if descriptor is writableAngel Pons
Copy the `is_descriptor_writeable()` function from the `intel/adlrvp` mainboard and use it in the `configure_pmc_descriptor()` function. With this change, this function is now identical for both mainboards. Change-Id: I2ff39682ed98c6b8bc60cc2218f36f4934b9903c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
2022-01-11mb/google/brya/bootblock.c: Sync cosmetics with adlrvpAngel Pons
Adjust the cosmetics of the `configure_pmc_descriptor()` function to match the code for the `intel/adlrvp` mainboard. The only difference is that adlrvp checks if the descriptor is writable. Tested with BUILD_TIMELESS=1, Google Brya0 remains identical. Change-Id: I9c524d5c422c765db200a15f484c2b8827ebd40b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
2022-01-11mb/google/brya: Restructure PMC descriptor updateAngel Pons
Restructure the code in the `configure_pmc_descriptor()` so that it matches the code for the `intel/adlrvp` mainboard. This change does not reindent the contents of the original if-block intentionally as this will be taken care of in a reproducible follow-up. Change-Id: I8c9d9087cb2d0668f6a4afbb566d830bb9febd89 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
2022-01-11mb/google/brya/(brya0,taeko): Use eNEM for CAR by defaultSubrata Banik
More Brya variants like Brya0 and Taeko have migrated to use Alder Lake QS SoC which enables eNEM feature by default. Hence, select eNEM for CAR by default for these variants. BUG=b:168820083 TEST=Able to build and boot brya0 variant using eNEM mode. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I63be166c8e428f052999fe29c8ebe1238e1a12ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/60912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-10src/mainboard/emulation/qemu-i440fx: Fix struct packingPatrick Rudolph
On x86_64 the struct isn't packed, causing the fw_cfg parser to return invalid memory entries (possible others as well) through fw_cfg. Fix that by packing all structs. Change-Id: Id1bab99f06be99674efe219dda443fb7d44be560 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-10src/mainboard/google: Remove unused <acpi/acpi.h>Elyes HAOUAS
Change-Id: I67fc65c5e01bb134e2e3068dc6da03de1183f785 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-10src/mainboard/{jetway,lenovo,msi,ocp}: Remove unused <console/console.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<" Change-Id: I74264aa04d819b26c6ee91ded88b5578784a0732 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-10src/mainboard/{elmex,gizmosphere}: Remove unused <console/console.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<" Change-Id: I656ca220180261b7af10297ab2c3d2d8693666c7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-10src/mainboard/{bap,biostar}: Remove unused <console/console.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<" Change-Id: I1b5cec8fe3a8d6b4947cf67c3284a37789600188 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-10src/mainboard/{siemens,starlabs}: Remove unused <console/console.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<" Change-Id: I9116965512a5b3241fd7e28537d96637008b31e4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-10src/mainboard/{hp,intel}: Remove unused <console/console.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<" Change-Id: I0345aa22b2330d002c3a4bbe5fbadc57d83d73b0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-25 13:29:55 +0000