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authorFelix Held <felix-coreboot@felixheld.de>2022-01-13 00:00:15 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-01-27 22:21:39 +0000
commit1c3b2a706e536c0ed11fd1d7073131fcf4a2029a (patch)
tree25b65528213fd446a13417ff584b2bf2e979ecde /src/mainboard
parent9517ae9f699822682aeb9ed56e5445949cdeec2a (diff)
soc/amd/sabrina: update PCI devices in devicetree.cb
Also update mb/amd/chausie accordingly. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idb4dcffa48c3dbdcffb66f1398b99ee96562efb9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/amd/chausie/devicetree.cb1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/amd/chausie/devicetree.cb b/src/mainboard/amd/chausie/devicetree.cb
index 0494f5b6f7..98030f73db 100644
--- a/src/mainboard/amd/chausie/devicetree.cb
+++ b/src/mainboard/amd/chausie/devicetree.cb
@@ -25,7 +25,6 @@ chip soc/amd/sabrina
device domain 0 on
device ref iommu on end
- device ref gpp_gfx_bridge_0 on end # MXM
device ref gpp_bridge_0 on end # NVMe
device ref gpp_bridge_1 on end
device ref gpp_bridge_2 on end # WWAN