diff options
| author | Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> | 2022-01-10 13:56:53 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-01-12 19:50:08 +0000 |
| commit | ae3f90b8f308b1b86012b52f69f34b2009db57a0 (patch) | |
| tree | 83f372fea139f934a998b16daa0dc369478599af /src/mainboard | |
| parent | 778851366705579631f23b650edf3bc860f499e4 (diff) | |
mb/google/brya/var/taeko: Modify power sequence for SSD device
In order to avoid having the FSP fail to detect the SSD device
downstream of the RP, its PERST# must be deasserted earlier in
the boot flow, therefore move PERST# deassertion to a romstage
GPIO table.
BUG=b:213828931
TEST=Build FW and run stress exceed 1000 cycles.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I4e5eed7db16e1420ccbc22a5c30b00bedd190a2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/brya/variants/taeko/gpio.c | 21 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/taeko4es/gpio.c | 21 |
2 files changed, 32 insertions, 10 deletions
diff --git a/src/mainboard/google/brya/variants/taeko/gpio.c b/src/mainboard/google/brya/variants/taeko/gpio.c index a390604669..4d93e549e1 100644 --- a/src/mainboard/google/brya/variants/taeko/gpio.c +++ b/src/mainboard/google/brya/variants/taeko/gpio.c @@ -140,6 +140,8 @@ static const struct pad_config override_gpio_table[] = { static const struct pad_config early_gpio_table[] = { /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), /* * D1 : ISH_GP1 ==> FP_RST_ODL * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. @@ -169,11 +171,6 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* H13 : I2C7_SCL ==> EN_PP3300_SD */ PAD_CFG_GPO(GPP_H13, 1, DEEP), - /* - * B4 : PROC_GP3 ==> SSD_PERST_L - * B4 is programmed here so that it is sequenced after EN_PP3300_SSD. - */ - PAD_CFG_GPO(GPP_B4, 1, DEEP), /* CPU PCIe VGPIO for PEG60 */ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), @@ -197,6 +194,14 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), }; +static const struct pad_config romstage_gpio_table[] = { + /* + * B4 : PROC_GP3 ==> SSD_PERST_L + * B4 is programmed here so that it is sequenced after EN_PP3300_SSD. + */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), +}; + const struct pad_config *variant_gpio_override_table(size_t *num) { *num = ARRAY_SIZE(override_gpio_table); @@ -208,3 +213,9 @@ const struct pad_config *variant_early_gpio_table(size_t *num) *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/taeko4es/gpio.c b/src/mainboard/google/brya/variants/taeko4es/gpio.c index aa778fc9f2..5d8badf64b 100644 --- a/src/mainboard/google/brya/variants/taeko4es/gpio.c +++ b/src/mainboard/google/brya/variants/taeko4es/gpio.c @@ -140,6 +140,8 @@ static const struct pad_config override_gpio_table[] = { static const struct pad_config early_gpio_table[] = { /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ @@ -169,11 +171,6 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* H13 : I2C7_SCL ==> EN_PP3300_SD */ PAD_CFG_GPO(GPP_H13, 1, DEEP), - /* - * B4 : PROC_GP3 ==> SSD_PERST_L - * B4 is programmed here so that it is sequenced after EN_PP3300_SSD. - */ - PAD_CFG_GPO(GPP_B4, 1, DEEP), /* CPU PCIe VGPIO for PEG60 */ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), @@ -197,6 +194,14 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), }; +static const struct pad_config romstage_gpio_table[] = { + /* + * B4 : PROC_GP3 ==> SSD_PERST_L + * B4 is programmed here so that it is sequenced after EN_PP3300_SSD. + */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), +}; + const struct pad_config *variant_gpio_override_table(size_t *num) { *num = ARRAY_SIZE(override_gpio_table); @@ -208,3 +213,9 @@ const struct pad_config *variant_early_gpio_table(size_t *num) *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} |