diff options
| author | Alan Huang <alan-huang@quanta.corp-partner.google.com> | 2022-01-17 10:37:22 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-18 16:13:10 +0000 |
| commit | db8afc70ba3d4399d16e76e9e6cf71fb86f63dd9 (patch) | |
| tree | 70b183a82df9d0a7a091fe5cf1a1bab957b7e475 /src/mainboard | |
| parent | 5338a16b2ec2908150085cd435a02241e87e17db (diff) | |
mb/google/brya/var/brask: Turn on I2C1 for TPM
The latest schematics changes the TPM I2C from I2C3 to I2C1. This patch
turns on I2C1 and turns off I2C3.
BUG=b:211886429
TEST=Test if proto 1 can boot into Chrome OS successfully.
Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com>
Change-Id: I0e94c900b48adf10880aae2abb47e08d1bd9e19b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index a7328a9bbe..346b98eef2 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -44,9 +44,9 @@ chip soc/intel/alderlake register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoDisabled, - [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, [PchSerialIoIndexI2C4] = PchSerialIoDisabled, [PchSerialIoIndexI2C5] = PchSerialIoDisabled, }" |