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2022-02-17mb/google/herobrine: Disable fingerprint sensor on CRD devicesRavi Kumar Bokka
Qualcomm CRD devices do not have a fingerprint sensor so removing the QUP configuration for it. This QUP also coincidentally is the same as the one used for the TPM, so this initially was also causing TPM communication issues during bootup as the QUP was being reconfigured during the later stages after QcLib execution. BUG=b:206581077 BRANCH=None TEST=Boot to kernel without any CR50 communication errors Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Change-Id: I8d13b67796b70b0b7e9a4721cca0b8a54b2b27c1 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61716 Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-17mb/google/brya/var/vell: Add Wifi SAR for vellRobert Chen
Add wifi sar for vell BUG=b:218992598 TEST=emerge-brya coreboot-private-files-baseboard-brya coreboot chromeos-bootimage Change-Id: I74fddd1dbcb7019fd5fe394da291f125f0d4960f Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-17mb/google/brya/var/vell: Correct the DQ mappingGaggery Tsai
This patch corrects the DQ mapping and enable ECT. In Vell design, the DQS is swapped in Mc0.ch1, Mc0.ch3, Mc1.ch0, Mc1.ch1 and Mc1.ch2 but the DQ mappings are not swapped and that causes ECT training failure. BUT=b:208719081 TEST=emerge-brya coreboot chromeos-bootimage && ensure the system passes ECT training and all the way booting to the OS. Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Change-Id: Idd2ad16151f0b2b93b00295b75a66ba65cba23cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/61981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-16mb/google/herobrine: Add Gigadevice SPI PartShelley Chen
BUG=b:182963902 BRANCH=None TEST=emerge-herobrine coreboot Change-Id: I73dc695afb7aa2b32aa966070eb057c828073d47 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-02-16mb/google/herobrine: Alphabetize SPI_FLASH configsShelley Chen
BUG=b:182963902 BRANCH=None TEST=None Change-Id: Ia73460d335e859644511b7e9ca80111a919baf2c Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-02-16Use the fallthrough statement in switch loopsArthur Heymans
Clang does not seem to work with 'fall through' in comments. Change-Id: Idcbe373be33ef7247548f856bfaba7ceb7f749b5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-16mb/google/brya/var/agah: Select PCIEXP_SUPPORT_RESIZABLE_BARSTim Wawrzynczak
The google/agah variant will use a peripheral that will require the use of the PCIe Resizable BAR feature from the PCIe spec. Thus, select the new Kconfig option to enable it. The appropriate Resizable BAR size will be updated later. BUG=b:214443809 TEST=build Change-Id: I9cf86ba3160ae5018655b5d366e89f4273b30b94 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-16mb/google/brya/var/agah: Change ELAN touchpad driver for eKT3744Tony Huang
Change to use i2c/generic to match ELAN FW update script. BUG=b:210970640 TEST=emerge-draco coreboot chromeos-bootimage Change-Id: Ib416da6000d9e99f9c37cf497fb1c43e3fca0220 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-16mb/google/brya: Update memory DQ mapEric Lai
Follow latest schematic to update the DQ map. BUG=b:218939997 TEST=boot into OS without issue. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: If29cc22b1749fb5d602d3ce64bcc1182593d673f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-15soc/intel/cnl: Move selection of DISABLE_HECI1_AT_PRE_BOOT back to mainboardMatt DeVillier
Commit 805956bce [soc/intel/cnl: Use Kconfig to disable HECI1] moved HECI1 disablement out of mainboard devicetree and into SoC Kconfig, but in doing so inadvertently disabled HECI1 for Puff-based boards which previously had HECI1 enabled by default. To correct this, move the Kconfig selection back into the mainboard Kconfig, and set defaults to match values prior to refactoring in 805956bce. Test: run menuconfig for boards google/{drallion,hatch,puff,sarien} and ensure Disable HECI1 option defaults to selected for all except Puff. Change-Id: Idf7001fb8b0dd94677cf2b5527a61b7a29679492 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-15mb/google/dedede/var/beadrix: Add LTE power off sequenceTeddy Shih
This change adds LTE power off sequence for beadrix. BUG=b:204882915 BRANCH=dedede TEST=FW_NAME=beadrix emerge-dedede coreboot Change-Id: I11370bf69438465d2230e2633044ba42685a152b Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61329 Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-15mb/google/guybrush: Add a mainboard specific SPL tableZheng Bao
Chromebook needs to do some additional check, which is not available in the AMD's PI released SPL table. BUG=b:216096562 Change-Id: Ib8074641b9fc9b38239a6e3837b8569e14af3342 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-15mb/google/brya/var/nereid: Disable LTE-related GPIOsReka Norman
Nereid does not support the LTE sub-board, so disable the LTE-related GPIOs. BUG=b:197479026 TEST=abuild -a -x -c max -p none -t google/brya -b nereid Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I6d6b5babeefb7c4b79adab5e756f37616c2338d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-15mb/google/brya/var/nereid: Initialise overridetreeReka Norman
Add an initial overridetree for nereid based on the pre-proto schematic and build matrix. BUG=b:197479026 TEST=abuild -a -x -c max -p none -t google/brya -b nereid Change-Id: I7d313439337c84ab1024b3570cc7b57b4255af5d Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-15mb/google/brya/var/nereid: Add H9JCNNNBK3MLYR-N6E for P1 buildReka Norman
Nereid P1 will also use Hynix H9JCNNNBK3MLYR-N6E. Add it to the parts list and regenerate the memory IDs using part_id_gen. BUG=b:217096008 TEST=abuild -a -x -c max -p none -t google/brya -b nereid Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Ibacb9dfb336967dd7fffe351d785cbbff9ba8b7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-15mb/google/brya: Create kinox variantDtrain Hsu
Create the kinox variant of the brask reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:215049181 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_KINOX Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I68cac421f6299a5f82f2ab51633173648c993060 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61789 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-15herobrine: update SPI-NOR config optionsT Michael Turney
Configuration support for 4k-byte addressing mode BUG=b:215605946 TEST=Validated on qualcomm sc7280 developement board Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com> Signed-off-by: Shaik Sajida Bhanu <quic_c_sbhanu@quicinc.com> Signed-off-by: T Michael Turney <quic_mturney@quicinc.com> Change-Id: If82de6204446251dded1b83684677e6eb536e6fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/61279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-02-14mb/google/brya/var/vell: update gpio for DMICShon Wang
Data on channel 0 & 1 are normal (from DMIC) but there is noise on channel 2 & 3, so change to NF PAD_CFG_NF(GPP_R6, NONE, DEEP, NF4) to PAD_NC(GPP_R6, NONE), PAD_CFG_NF(GPP_R7, NONE, DEEP, NF4) to PAD_NC(GPP_R7, NONE), BUG=b:210802722 TEST=FW_NAME=vell emerge-brya coreboot Change-Id: I1b5ccd2c239e526e4f1ce2d5ed6c1386303590c8 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61033 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-14mb/google/guybrush: Enable power resource for BTRaul E Rangel
The `reset` gpio is currently being consumed by the btusb kernel driver. The functionality was added in https://crrev.com/c/3342774. The goal of the patch was to reset the BT device when command timeouts occur. This works, but it doesn't support the case where the BT device is having problems with USB enumeration. In that case the device can't enumerate so the driver can't help resetting the device. If we instead switch to using an ACPI power resource, the kernel can control the BT device's power. This is beneficial when the device is having USB communication problems since the kernel will try and power cycle the device. We don't lose the ability to reset the device on command timeouts either since `btusb_qca_cmd_timeout` will enqueue a USB port reset if there is no `reset` GPIO. So win / win. This results in the following power resource: PowerResource (PR02, 0x00, 0x0000) { Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x01) } Method (_ON, 0, Serialized) // _ON_: Power On { \_SB.CTXS (0x84) Sleep (0x01F4) } Method (_OFF, 0, Serialized) // _OFF: Power Off { \_SB.STXS (0x84) Sleep (0x0A) } } I switched the device tree entry from using reset_gpio to enable_gpio because the acpi_device_add_power_res method asserts the reset in the _ON method unconditionally. This results in a small glitch on the line. By using the enable_gpio we get the correct behavior. I don't have a datasheet right now, so I just picked some values for the reset timing. The kernel driver was using 200ms. We can revisit the numbers when we get a datasheet. BUG=b:218295688 TEST=Suspend stress test on nipperkin with 600+ cycles. Verify power resource is created on the kernel. This should allow the kernel to power cycle the device via usb_acpi_set_power_state. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib1eff86db76929f76432cd6f765880c892e7a786 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-02-14mb/google/brya: Adjust FMD file for some boardsTracy Wu
When brya boards that use ChromeOS autoupdate update their firmware, devices with SOC_INTEL_CSE_SUB_PART_UPDATE will end up attempting to replace IOM and NPHY BPDT firmware in the CSE region. However, because of the way the autoupdate works, the CSE RO will not be updated during autoupdate. This means that these boards now have different stitching schemes between CSE RO and RW and this causes the sub-partition update to fail and the boot hangs. To remedy the situation for these boards, a separate FMD files is provided so they can continue to use the cse_serger tool for stitching. The only boards affected were kano and brask, so they are updated here. BUG=b:218376385 TEST=use flashrom to downgrade to 14474 then use futility to update to image with this patch and system boots. Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com> Change-Id: Ia8bdf6b28d952f6d983b84e39da96e159027a822 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-14mb/google/brya/var/brask: Enable ASPM of RTL8125Alan Huang
Brask cannot pass powerd_dbus_suspend test because the NIC does not enter ASPM L1.2. Here we add "enable_aspm_l1_2" in devicetree for RTL8125 to enable ASPM L1.2. BUG=b:204309459 BRANCH=None TEST=emerge and test with command powerd_dbus_suspend Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Change-Id: I9a56df1d68696f409f9ee681d37de6759a588d80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-12mb/google/dedede/var/beadrix: Add LTE modem supportTeddy Shih
This change adds LTE modem for beadrix. BUG=b:204882915 BRANCH=dedede TEST=Build and boot beadrix, check with command modem status Change-Id: I7acb88634478ff486810b2c3fc14d6739c3268e1 Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61328 Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-12mb/google/brya/var/agah: Update Aux settingsTony Huang
Agah port 0 does not have a retimer so the port needs to be configured for the SOC to handle Aux orientation flipping. Add the "TcssAuxOri" and "typec_aux_bias_pads" to lets the SoC IOM firmware control the Aux DC bias voltages. BUG=b:210970640 BRANCH=NONE TEST=emerge-draco coreboot chromeos-bootimage Change-Id: I1fa5c4574b1a0e8dd2f66f3f6382436337c530fa Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-12mb/google/nissa: Set half_populated trueKrishna Prasad Bhat
Alder Lake N has single memory controller with 64-bit bus width. Alder Lake common meminit block driver considers bus width to be 128-bit and populates the meminit data accordingly. By setting half_populated to true, only the bottom half is populated. Ideally, half_populated is used in platforms with multiple channels to enable only one half of the channel. Alder Lake N has single channel, and it would require for new structures to be defined in meminit block driver for LPx memory configurations. In order to avoid adding new structures, set half_populated to true. This has the same effect as having single channel with 64-bit width. Change-Id: I414e5dc82caf47b6b96c474b3ef6e01c2ce0226e Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-12mb/google/guybrush/var/nipperkin: Add _HID for privacy screen deviceKevin Chiu
BUG=b:204401306 BRANCH=guybrush TEST=emerge-guybrush coreboot dump SSDT, see _HID instead of _ADR Change-Id: I3f45fabac1548cca39379f91cc42fed0cd04f8a3 Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-11mb/google/brya/var/primus4es: reconfig USE_PM_ACPI_TIMERCasper Chang
Config USE_PM_ACPI_TIMER to y for primus4es only as commit 1ce0f3aab7 (mb/google/brya: Fix S0i3 regression) breaks suspend stress test on ES CPU SKU. BUG=b:211377699 TEST=USE="project_primus emerge-brya coreboot" and verified the suspend stress test works on primus4es. Change-Id: I8d19c10e2029e233542a8ceec272f8ede2b4bfac Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-02-11mb/google/brya/variants/primus: add dram part idMalik_Hsu
This change adds mem_parts_uesd.txt that contains the new memory parts used (H54G46CYRBX267,H54G56CYRBX247) by primus and Makefile.inc generated by gen_part_id using mem_parts_used.txt. BUG=b:218415732 Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I0d236c51f0c996a22954046876f3494ba9e62693 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-11soc/amd/cezanne,picasso,sabrina: Fix incorrect values of CBFS amdfw position ↵Robert Zieba
makefile variables Currently apu/amdfw_a-position and apu/amdfw_b-position currently depend on CEZANNE_FW_A_POSITION and CEZANNE_FW_B_POSITION. This causes error messages from awk as these variables are sourced from fmap_config.h and these variables are expanded before fmap_config.h is built. However these variables should not be set to CEZANNE_FW_*_POSITION. These files end up in the FW_MAIN_* fmap regions. These regions are placed at the proper locations through the chromeos.fmd file. The apu/amdfw_*-position variables are the positions within these regions where the files end up. These variables should be set to 0x40 to coincide with the beginning of the FW_MAIN_* regions, accounting for the size of struct cbfs_file + filename + metadata, aligned to 64 bytes. Currently they end up in the correct locations only because fmap_config.h does not exist when the apu/amdfw_*-position variables are expanded. This change explicity sets the value of these variables to 0x40, removing the errors from awk and ensuring that these files end up in the correct location in the resulting image. These changes are also applied to the Picasso and Sabrina makefiles as well. BUG=b:198322933 TEST=Verified that the apu/amdfw_* files end up in the correct locations as reported by cbfstool during the build, did timeless builds and confirmed that coreboot.rom images were identical, tested AP firmware on guybrush and zork devices Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: If1c2b61c5be0bcab52e19349dacbcc391e8aa909 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-02-11mb/google/brya/var/nivviks: Implement WWAN power sequencingReka Norman
Nissa is using the FM101, which has the following power sequencing requirements: Power on: assert WWAN_EN, delay 20 ms, deassert WWAN_RST_L Power off: assert WWAN_RST_L, delay 20 ms, deassert WWAN_EN Add a power resource to the USB device, and use wwan_power.asl to handle the power off sequence. BUG=b:217092522 TEST=abuild -a -x -c max -p none -t google/brya -b nivviks Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Ibe1b863a550c6af1ac3eb98f2aaa3db15b149ada Reviewed-on: https://review.coreboot.org/c/coreboot/+/61694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-11mb/google/brya: Support power sequencing for USB-only WWANReka Norman
Nissa is using the FM101 which is USB only. To allow us to reuse the existing wwan_power.asl for power sequencing, move the PCIe-specific part behind a new Kconfig HAVE_PCIE_WWAN. BUG=b:217092522 TEST=Build brya0 and check that generated dsdt.asl doesn't change. Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Icb6db91ce00deb2b30379f5ff7a974d1feb62ea8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-11mb/google/brya/var/nivviks: Disable LTE-related GPIOs based on fw_configReka Norman
If the LTE USB DB is not connected, disable the LTE-related GPIOs. BUG=b:197479026 TEST=abuild -a -x -c max -p none -t google/brya -b nivviks Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I86251d8ad58d82ff2112ac5f2dfafdabbff4c76f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-11mb/google/brya/var/nivviks: Initialise overridetreeReka Norman
Add an initial overridetree for nivviks based on the pre-proto schematic and build matrix. BUG=b:197479026 TEST=abuild -a -x -c max -p none -t google/brya -b nivviks Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Id3ecd184415a20a3a52da8bb5e60fe2ce0495b44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-02-10mb/google/octopus,reef: Align SMMSTORE region in default.fmdArthur Heymans
The SMMSTORE region needs to be 64K aligned or error will be thrown. Change-Id: I5d4f71f80c3219ac2c7000e1fa95fd04100d9cfe Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-10mb/google/reef: Add VBTs for all variantsMatt DeVillier
Adjust Kconfig so all variants use proper VBTs. Add Makefile entries for variants which use multiple VBTs. extracted from ChromeOS firmwares: Google_Coral.10068.113.0 Google_Pyro.9042.233.0 Google_Reef.9042.233.0 Google_Sand.9042.220.0 Google_Snappy.9042.253.0 Change-Id: I46ad4ec321e32d019e44f0741956b18a464fb8ae Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-02-10mb/google/reef/coral/mainboard.c: Drop break after return inside switchMatt DeVillier
Drop unnecessary switch break after return, to alleviate linter warnings. Change-Id: I7cc49caaeafb490cb62b75ec5c3ca4822573464b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-02-10mb/google/reef/coral: Sync mainboard.c with Chromium forkMatt DeVillier
Several commits were made to the Chromium coral branch (firmware-coral-10068.B) which were not committed upstream first. Pull them in here: 486ce56 mainboard/google/coral: Override VBT selection for babymako c1d7720 Babymako: add touchpad i2c speed config 911d547 mainboard/google/coral: Override VBT selection for babytiger 730a5af Babytiger: add touchpad i2c speed config 724711e rabbid: add the touchpad i2c speed config 80c5d16 mainboard/google/coral: Override VBT selection for babymega e8931a4 Babymega: add touchpad i2c speed config These add support for additional coral sub-variants. The I2C speed config changes were adapted to account for upstream changes not present in the coral Chromium branch. Change-Id: Idf2a53a351138aff310385f4026197d74ab6848b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2022-02-10mb/google/reef: drop nasher variantMatt DeVillier
Release firmware on Nasher/Nasher360 are built as coral sub-variants; remove the old/unused code Change-Id: Ie8d10a31e663230b7deabf92e1c06cd991bbdccb Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-02-10mb/google/brya: Create moli variantRaihow Shi
Create the moli variant of the brask reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:214439135 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_MOLI Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I3f3bfd3db12cba8b73b351e7c700b6a58797c906 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-02-10mb/google/dedede/var/magolor: Add custom Wifi SAR for magnetoTyler Wang
Add wifi sar for magneto. Due to fw-config cannot distinguish between magolor and magneto. Using sku_id to decide to load magneto custom wifi sar. BUG=b:208261420 TEST= emerge-dedede coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I77f141372ba8e7b8f5849b00e115ad8bb1e7ca00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2022-02-10mb/google/volteer/var/drobit: Add fw_config probe for ALC5682-VD & VSFrankChu
ALC5682-VD/ALC5682I-VS load different kernel driver by different _HID name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. Define FW_CONFIG bits 41 - 43 (SSFC bits 9 - 11) for codec selection. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:204517112 BRANCH=volteer TEST=ALC5682-VD/ALC5682I-VS audio codec can work Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I5c1c9819af1e0bc2278dadeffb6b19c3f9068f30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-10mb/google/volteer/var/copano: Add fw_config probe for ALC5682-VD & VSFrankChu
ALC5682-VD/ALC5682I-VS load different kernel driver by different _HID name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. Define FW_CONFIG bits 41 - 43 (SSFC bits 9 - 11) for codec selection. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:218245715 BRANCH=volteer TEST=ALC5682-VD/ALC5682I-VS audio codec can work Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I081dcf5451c82c03592f954ee25267b31ad81753 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-10mb/google/volteer/var/delbin: update fw_config probe for ALC5682-VD & VSFrankChu
use DEV_PTR to get codec HID for simplify the variant.c code ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:204523176 BRANCH=volteer TEST=ALC5682-VD/ALC5682I-VS audio codec can work Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Idf5b3661e74a189390d25381e03448c28a966f38 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61671 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-10mb/google/brya/variants/brask: Enable Bluetooth offload supportMac Chiang
Add fw_config NAU88L25B_I2S field, I2S2 configuration and enabling CnviBtAudioOffload UPD bit. BUG=none TEST=temerge-brask coreboot Signed-off-by: Mac Chiang <mac.chiang@intel.com> Change-Id: Id5da8c5c471be176bc0fe1eda4da7faf8ed2e8d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61404 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-09mb/google/var/volmar: Add gpios to lockEric Lai
Variant should honor locked gpios from baseboard, but not the last. Variant can add more gpios to lock if needed. BUG=b:216583542 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that volmar boots successfully to kernel. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I36355af771fbf97e655f2fd6e0505c657e0420b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-09mb/google/var/vell: Add gpios to lockEric Lai
Variant should honor locked gpios from baseboard, but not the last. Variant can add more gpios to lock if needed. BUG=b:216583542 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that vell boots successfully to kernel. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I0c39d06e3b2f39db88d924205786bfa1b27df3fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/61704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-09mb/google/var/taniks: Add gpios to lockEric Lai
Variant should honor locked gpios from baseboard, but not the last. Variant can add more gpios to lock if needed. BUG=b:216583542 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that taniks boots successfully to kernel. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Icf6cb0d057f9ad3cbcc1155423ed7efa58a46d0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-09mb/google/var/taeko4es: Add gpios to lockEric Lai
Variant should honor locked gpios from baseboard, but not the last. Variant can add more gpios to lock if needed. BUG=b:216583542 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that taeko4es boots successfully to kernel. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I82bdf8a1bfe2df0fc1d50d154def8742714321ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/61702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-09mb/google/var/taeko: Add gpios to lockEric Lai
Variant should honor locked gpios from baseboard, but not the last. Variant can add more gpios to lock if needed. BUG=b:216583542 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that taeko boots successfully to kernel. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib30815dbe99342b6afd9af9f1aa9ff61c9a4fe80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-09mb/google/var/redrix4es: Add gpios to lockEric Lai
Variant should honor locked gpios from baseboard, but not the last. Variant can add more gpios to lock if needed. BUG=b:216583542 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that redrix boots successfully to kernel. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ifd69a9c2f1a71aefc19adf6931e10de62d05fb2c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-09mb/google/var/redrix: Add gpios to lockEric Lai
Variant should honor locked gpios from baseboard, but not the last. Variant can add more gpios to lock if needed. BUG=b:216583542 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that redrix boots successfully to kernel. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: If08ae5c96232efd03d77090c3c6979c77f95c998 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-09mb/google/var/primus4es: Add gpios to lockEric Lai
Variant should honor locked gpios from baseboard, but not the last. Variant can add more gpios to lock if needed. BUG=b:216583542 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that primus boots successfully to kernel. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I71f7391df6d827b75f87e54e17f6f7983a9e829b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-09mb/google/var/primus: Add gpios to lockEric Lai
Variant should honor locked gpios from baseboard, but not the last. Variant can add more gpios to lock if needed. BUG=b:216583542 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that primus boots successfully to kernel. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I3133a992617c833fd13df97795c46ec04ebb8bf9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-09mb/google/var/kano: Add gpios to lockEric Lai
Variant should honor locked gpios from baseboard, but not the last. Variant can add more gpios to lock if needed. BUG=b:216583542 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that kano boots successfully to kernel. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I1d8c003b19381e6a76aff8c844546694c5710e53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-09mb/google/var/gimble4es: Add gpios to lockEric Lai
Variant should honor locked gpios from baseboard, but not the last. Variant can add more gpios to lock if needed. BUG=b:216583542 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that gimble boots successfully to kernel. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: If71ceb07a9894a0571a9983d008058598693986f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-09mb/google/var/gimble: Add gpios to lockEric Lai
Variant should honor locked gpios from baseboard, but not the last. Variant can add more gpios to lock if needed. BUG=b:216583542 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that gimble boots successfully to kernel. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Idd398d819dcb30a3ec588ce2ef4562a728f99405 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-09mb/google/var/felwinter: Add gpios to lockEric Lai
Variant should honor locked gpios from baseboard, but not the last. Variant can add more gpios to lock if needed. BUG=b:216583542 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that felwinter boots successfully to kernel. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ic1e0bfc53b74bd5af9ac8d598bb80833499dd997 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-09mb/google/var/banshee: Add gpios to lockEric Lai
Variant should honor locked gpios from baseboard, but not the last. Variant can add more gpios to lock if needed. BUG=b:216583542 TEST='emerge-brya coreboot chromeos-bootimage' Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Id5a2136e57e842fbd0b2c2836833106e7344afee Reviewed-on: https://review.coreboot.org/c/coreboot/+/61663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-09mb/google/var/anahera4es: Add gpios to lockEric Lai
Variant should honor locked gpios from baseboard, but not the last. Variant can add more gpios to lock if needed. Also fix the gpio order of GPP_F19. BUG=b:216583542 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that anahera4es boots successfully to kernel. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I9a73aca1c364dcbc3f3957cd4193d86f399a40bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/61661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-09mb/google/var/anahera: Add gpios to lockEric Lai
Variant should honor locked gpios from baseboard, but not the last. Variant can add more gpios to lock if needed. Also fix the gpio order of GPP_F19. BUG=b:216583542 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that anahera boots successfully to kernel. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ie50ba20a10ded184fd880be9ed288b90d346c22b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-09mb/google/var/agah: Add gpios to lockEric Lai
Variant should honor locked gpios from baseboard, but not the last. Variant can add more gpios to lock if needed. BUG=b:216583542 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that agah boots successfully to kernel. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ia9272f704e5656e6d0dc318dd1b51d50fc549839 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-09mb/google/brask: Add more gpios to lockEric Lai
Add rest of soc sensitive gpios to lock for brask. BUG=b:216583542 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that brask boots successfully to kernel. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Iad87d13d3df0ad87c075027e3fcc4c75aa711159 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-09mb/google/brya: Add more gpios to lockEric Lai
Add rest of soc sensitive gpios to lock for brya. BUG=b:216583542 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that brya0 boots successfully to kernel. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I41393e7a0e8bacb3cc98610f7101dabe66308f94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-09mb/google/brya: Mark the WWAN device as an UntrustedDeviceTim Wawrzynczak
The ChromiumOS kernel has the ability to restrict devices to their own IOMMU security domains when ACPI passes this property to a device downstream of a PCIe RP. BUG=b:215424986 TEST=verified the property is found and WWAN is restricted to its own IOMMU domain as expected. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I1717c0976d1d961772245fd420368fe5a9c1262e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-09mb/google/brya/var/taeko: Add new FW_CONFIG option for DB_USBJoey Peng
Enable USB Port A on daughterboard for Taeko BUG=b:216533764 TEST=emerge-brya coreboot Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I1a43c256757f3fc4b53ba1f794587d6a00ba0aa5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-09mb/google/volteer/var/collis: Add fw_config probe for ALC5682-VD & VSFrankChu
ALC5682-VD/ALC5682I-VS load different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. Define FW_CONFIG bits 41 - 43 (SSFC bits 9 - 11) for codec selection. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:192535692 BRANCH=volteer TEST=ALC5682-VD/ALC5682I-VS audio codec can work Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Ia6089441dc1ba04c3f7427dda065b85bd295af0d Reviewed-on: https://review.coreboot.org/c/coreboot/+/60415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Mac Chiang <mac.chiang@intel.com>
2022-02-09mb/google/brya/var/volmar: enable RTD3 for PCIe-eMMC bridgeDavid Wu
1. Enable RTD3 driver for PCIe-eMMC bridge 2. Add fw_config entries for boot device. BUG=b:211362308 TEST=Build and boot into eMMC storage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ic9ef372fa963b040c5196aaf13f2ffde27c168d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61712 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-09mb/google/brya: Use USB2_PORT_MAX_TYPE_C for Type-C USB2 portSridhar Siricilla
The patch selects USB2_PORT_MAX_TYPE_C macro for usb2 port#2 in the device tree of Gimble DVT and Gimble EVT. The macro modifies the USB2 configuration to indicate the port is mapped to Type-C and sets Max TX and Pre-emp settings. The change is required to enable port reset event on the USB2 port#2. This event is passed to USB3 upstream ports to upgrade back to super speed (USB3) after a downgrade during low power state. The change is done for Gimble DVT and EVT boards. BUG=b:193287279 TEST=Built coreboot for Gimble and tested type A pen drive detect as super speed device on both the Type-C ports. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: If54faa63a983c859bf26a6a779751a6c3c85c43d Reviewed-on: https://review.coreboot.org/c/coreboot/+/61586 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-09mb/google/brya/var/nivviks: Add MT62F512M32D2DR-031 WT:B for P1 buildReka Norman
Nivviks P1 will also use Micron MT62F512M32D2DR-031 WT:B. Add it to the parts list and regenerate the memory IDs using part_id_gen. BUG=b:217095281 TEST=abuild -a -x -c max -p none -t google/brya -b nivviks Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I2b56b0844e70a2712923b197436dd2d668e58a27 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-09mb/google/brya: Add custom PLD fields to devicetree for brya variantsWon Chung
BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: If610e6b3c849d982345ed1b8607ffd2af105dc51 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-02-08mb/google/brya/var/taeko: Add WiFi SAR table for taekoKevin Chang
Add WiFi SAR table for taeko. BUG=b:212405459 TEST=build FW and checked SAR table can load by WiFi driver. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I061dc798ae7177d05bc50648cfda46a3eec2c912 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-08mb/google/guybrush: Fix trackpad SCI configKarthikeyan Ramasubramanian
Trackpad GPIO configuration does not align with the IRQ configuration in the devicetree. Configure the trackpad GPIO to generate SCI on falling edge. BUG=None TEST=Build and boot to OS in Nipperkin. Ensure the trackpad is functional. Suspend the device and wake it using trackpad. Perform suspend/resume sequence for 100 iterations. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: If4324e09535d2676c8a8c6643604227eeaba0fe8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-02-08mb/google/brya: Add custom PLD fields to devicetree for brya referenceWon Chung
For USB ports, we want to use custom PLD fields with more details to indicate physical location. Custom PLD will also be added to other brya variants in the future as we figure out physical port locations on those devices. Type A port on MLB is removed since it is no longer used. BUG=b:216490477 TEST=emerge-brya coreboot & SSDT dump in Brya test device Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Iea975a4f436a204d4edd19fad0f5652fb44c6301 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-08mb/google/guybrush: Enable CONSOLE_CBMEM_DUMP_TO_UARTRaul E Rangel
This will make debugging boot failures with a non-serial firmware easier. If we encounter an error that requires a reboot, this will dump the entire CBMEM contents onto the UART. This is especially helpful during S0i3 resume because the PSP verstage console logs are not exposed anywhere. BUG=b:215599230 TEST=Cause verstage error in S0i3 with non-serial firmware and see that the verstage logs were dumped to the UART before rebooting. Entering PSP verstage S0i3 resume tpm_setup failed rv:1 VB2:vb2api_fail() Need recovery, reason: 0x3f / 0xcc Saving nvdata Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I908037527206cc7bed2302fab60b2912d6dabc73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-08mb/google/kahlee/ec.c: Fix log messageElyes HAOUAS
Change-Id: Ic42d5c05938c060ccaa7b1a260cd584b6e1bb1f3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-07treewide: Remove "ERROR: "/"WARN: " prefixes from log messagesJulius Werner
Now that the console system itself will clearly differentiate loglevels, it is no longer necessary to explicitly add "ERROR: " in front of every BIOS_ERR message to help it stand out more (and allow automated tooling to grep for it). Removing all these extra .rodata characters should save us a nice little amount of binary size. This patch was created by running find src/ -type f -exec perl -0777 -pi -e 's/printk\(\s*BIOS_ERR,\s*"ERROR: /printk\(BIOS_ERR, "/gi' '{}' ';' and doing some cursory review/cleanup on the result. Then doing the same thing for BIOS_WARN with 's/printk\(\s*BIOS_WARNING,\s*"WARN(ING)?: /printk\(BIOS_WARNING, "/gi' Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I3d0573acb23d2df53db6813cb1a5fc31b5357db8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Lance Zhao Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-02-07mb/google/brya: Add 5G WWAN ACPI support for Brya and RedrixCliff Huang
Add FM350GL 5G WWAN support using drivers/wwan/fm and addtional PM features from RTD3. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I6413f106ce6ef6c895d4861f4dbe26ac9a507d25 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-07mb/google/brya/var/kano: adjust I2C3 speedDavid Wu
This change adjusts I2C3 speed to lower then 400KHz. BUG=b:215095284 BRANCH=None TEST=built and verified adjusted I2C3 speed < 400KHz Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ief6773bc37931a5393b5b1b8beaeda61d235f133 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-07mb/google/brya/var/{taeko, taeko4es}: Configure Acoustic noise mitigationKevin Chang
- Enable Acoustic noise mitigation - Set slow slew rate VCCIA and VCCGT to 8 - Set FastPkgCRampDisable VCCIA and VCCGT to 1 BUG=b:201818726 TEST=build FW and system power on. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I881ded944530b21d1c5e306089d32387c9c258b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-07mb/google/cyan: Fix variant GPIOsMatt DeVillier
- set GPSE-77 (Maxim jack detect) to NC for variants using Realtek audio - set GPSW-37 to NC for all variants (not used for LPE audio) - set GPSW-95 (Realtek jack detect) to NC for variant using Maxim audio - set GPSE-77 as maskable on variant using Maxim audio, to match mask setting for jack detect GPIO on other variants - set GPSE-81 as maskable on CELES to prevent interrupt storm (likely due to change in cherryview pinctrl driver circa kernel v3.18 which no longer masks all interrupts at init) Change-Id: I50d4b3516eba8906042bb8dea768b229afcf11ea Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar Organization <coolstarorganization@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-07mb/google/fizz: update VBT for karma variantMatt DeVillier
Extracted from firmware image: bios-karma.ro-11343-22-0.rw-11343-22-0.bin Change-Id: Ic4165523a9114f748174c272ee206dfea80f4541 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-07mb/google/guybrush/var/dewatt: Add ALC5682I-VS and ALC1019 supportChris Wang
Add ID "AMDI5619" for machine driver to support ALC5682I-VS + ACL1019 combination. BUG=b:211835769 TEST=Build dewatt, codec is functional with new machine driver. Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ic6cb3bda7b8f1b96485f7b868200c94e6c720c7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Yu-hsuan Hsu <yuhsuan@google.com>
2022-02-07mb/google/nissa: Add devicetreeKangheui Won
Fill in devicetree for nissa baseboard based on schematics. BUG=b:197479026 TEST=abuild -a -x -c max -p none -t google/brya -b nivviks TEST=abuild -a -x -c max -p none -t google/brya -b nereid Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I6cd332fd05fde19078ebc4bd2797580abfb76f3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-04mb/google/brya: Enable UntrustedDevice wifi property for brask & bryaTim Wawrzynczak
The CNVi Wifi controller is considered an untrusted device for ChromeOS, therefore enable the new UntrustedDevice property for the cnvi_wifi device on all brya & brask boards. BUG=b:215424986 TEST=dump SSDT on google/redrix, verify it contains the expected UntrustedDevice property Change-Id: Ieff6eea0865125a7c0f626e1981dda1c9532ebb1 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-04Hoglin: Switch to using i2c TPMShelley Chen
Redefine Hoglin to be used for Qualcomm's CRD 3.0 board, which uses i2c for TPM instead of SPI. From now on, the Piglin board will be used for all the Qualcomm reference boards that use SPI for TPM. BUG=b:206581077 BRANCH=None TEST=hacked an 8MB image and make sure boots on herobrine board Change-Id: Ie1d71ec8b01f305c1c8fa815a0fb9b7ee022cc19 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-02-03mb/google/skyrim: Add new mainboardKarthikeyan Ramasubramanian
Skyrim is a new Google mainboard with AMD Sabrina SOC. BUG=b:214413553 TEST=util/abuild/abuild -t GOOGLE_SKYRIM --clean Change-Id: I008fea4aa163b8aa66e86735b29b3fdc4e08a327 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-02-03soc/amd/*/i2c: factor out common I2C pad configurationFelix Held
The I2C pad control registers of Picasso and Cezanne are identical and the one of Sabrina is a superset of it, so factor out the functionality. To avoid having devicetree settings that contain raw register bits, the i2c_pad_control struct is introduced and used. The old Picasso code for this had the RX level hard-coded for 3.3V I2C interfaces, so keep it this way in this patch but add a TODO for future improvements. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1d70329644b68be3c4a1602f748e09db20cf6de1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-03mb/google/guybrush: Separate nipperkin and dewatt mem_parts_used tableRob Barnes
With the APCB edit tool enabled in commit 6a3ecc5 (guybrush: Inject SPDs into APCB), DeWatt and Nipperkin can have independent mem_parts_used tables. Copied common table from guybrush and ran part_id_gen to make sure it's synced to latest. BUG=b:209486191 BRANCH=guybrush TEST=Boot on nipperkin Change-Id: Id30b596c2466902dfcc59dcc88dcaa00748a3949 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-03mb/google/brya/variants/gimble: Disable PCIE RP 6 and TCSS Port 1Meera Ravindranath
Gimble does not use WWAN and TCP Port 1 according to the schematics. Hence disabling it. BUG=b:216533766 TEST=Boot to kernel and verify WWAN and TCSS Port 1 disabled Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> change-Id: I0e7ae72620da39fc18ff253c440d006e83c576f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-03mb/google/brya: Implement variant_cros_gpios() for nissa baseboardReka Norman
BUG=b:197479026 TEST=Build test nivviks and nereid Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Ib49164cf51965228c65c6566b0711ae690b6cb50 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-03mb/google/brya: Override memory ID to 0 for nivviks and nereid P0Reka Norman
In the nivviks and nereid pre-proto builds, the memory straps used don't match those generated by spd_tools. Each pre-proto build only supports a single memory part, and each of these parts should have ID 0 (see CB:61443). Therefore, for nivviks and nereid board ID 0, hard code the memory IDs to 0 instead of reading them from the memory strap pins. From P1 onwards, the memory straps will be assigned based on the IDs generated by spd_tools. BUG=b:197479026 TEST=Build test nivviks and nereid Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Ic0c6f3f22d7a94f9eed44e736308e5ac4157163d Reviewed-on: https://review.coreboot.org/c/coreboot/+/61496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-03mb/google/brya: Add SPD configs for nivviks and nereidReka Norman
Add a mem_parts_used.txt for each of nivviks and nereid, containing the memory parts used in their pre-proto builds. Generate Makefile.inc and dram_id.generated.txt using part_id_gen. nivviks: Micron MT62F1G32D4DR-031 WT:B nereid: Samsung K3LKBKB0BM-MGCP BUG=b:197479026 TEST=Build nivviks and nereid. Use cbfstool to check that coreboot.rom contains an spd.bin. Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Ia3e5ee22199371980d3c1bf85e95e067d3c73e67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-03mb/google/brya: Fill in ec.h for nissa baseboardReka Norman
BUG=b:197479026 TEST=abuild -a -x -c max -p none -t google/brya -b nivviks abuild -a -x -c max -p none -t google/brya -b nereid Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I322a94569d8a63e8c0da68a8feb394ade4ce7999 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-03mb/google/brya: Add memory config for nissaReka Norman
Fill in the memory config based on the the schematic and doc #573387. BUG=b:197479026 TEST=abuild -a -x -c max -p none -t google/brya -b nivviks abuild -a -x -c max -p none -t google/brya -b nereid Change-Id: I6958c7b74851879dbea41d181ef8f1282bf0101d Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-03mb/google/brya: Fill in gpio.h for nissa baseboardReka Norman
BUG=b:197479026 TEST=abuild -a -x -c max -p none -t google/brya -b nivviks abuild -a -x -c max -p none -t google/brya -b nereid Change-Id: I7ec4b9368e0a63c0c0c9a92c8367a89d57f10d51 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-03mb/google/brya: Add Kconfig for SLP_S0_GATEReka Norman
Nissa doesn't have a SLP_S0_GATE signal, so we shouldn't generate the related ACPI code. Therefore, move this behind a Kconfig which is currently selected by the brya and brask baseboards. BUG=b:197479026 TEST=Build brya0, check that there's no change to the generated dsdt.asl Change-Id: I5a73c6794f6d3977cbff47aeff571154e41944cc Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-03mb/google/brya: Add GPIO table for nissaReka Norman
Fill in the nissa baseboard GPIO table based on the nivviks P0 and nereid P0 schematics. Also, add an override GPIO table for each of nivviks and nereid. The differences between nivviks and nereid are: - WFC: nivviks has a MIPI WFC and nereid has a USB WFC, so the MIPI-related pins are overriden to NC on nereid. - The DMIC pins and speaker I2S pins were swapped after nivviks P0. The baseboard reflects the new configuration, which will be used in nivviks P1 onwards, nereid, and future variants. For now, nivviks overrides the pins to the old configuration. Once nivviks P1 is released, this will need to be updated to handle both. BUG=b:197479026 TEST=abuild -a -x -c max -p none -t google/brya -b nivviks abuild -a -x -c max -p none -t google/brya -b nereid Change-Id: Ic923fd22abcaf7da0c607f66705a6e16c14cf8f2 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-02mb/google/guybrush: Enable PSP port 80sRaul E Rangel
Let's re-enable PSP post codes when running PSP verstage. The original reason we disabled POST codes was that it was causing problems during eSPI init in bootblock. Since we now init eSPI in PSP verstage, it's safe to re-enable them. We can now see post codes during S0i3 enter and exit. This will help when debugging resume or suspend hangs. Port 80 writes on suspend: ef000020 ef00ed00 ef00ed01 ef000021 <--new Port 80 writes on resume: 05 eea80025 eea90000 eea90100 eea90200 eea50000 eeae0000 eeae0004 eeaf0000 eeb00000 eec00000 eec00100 eec10000 eec40000 eec40500 eec40200 eefc0000 eefc0100 eec50000 ea00e0fc ea00abc1 ea00e60b ea00e60c ea00abe1 ea00abe2 ea00abe4 ea00abe5 ea00abeb ea00abec ea00abed ea00abee ea00abef ea00e10f ea00e098 ea00e099 ea00abf0 ea00abf2 ea00e10e ea00e60c ea00e101 ea00e090 ea00e091 ea00e098 ea00e099 ea00e098 ea00e099 ea00e100 ea00e60c ea00e0b0 ea00e0b4 ea00e0b7 ea00e60c ea00e0c2 ea00e0c4 ea00e0d3 ea00e60c ea00e10d ea00e0c1 ea00e10c ea00e60c ea00e0c4 e000 eec60000 eec20000 eec20800 b40000 eeb50000 eefc0000 eefc0300 ee070000 eed90000 eed90700 eeda0600 eedd0000 eecb0000 eecf0000 eecf0200 eee30000 eee30900 eee40000 ef000025 BUG=b:215425753 TEST=Boot/suspend/resume guybrush and verify post codes are printed Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ie759f66be2b8ffac19145491a227752d4762a5b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-02mb/google/brya/var/vell: Enable SaGvGaggery Tsai
This patch enables SaGv since somehow it was accidently removed by commit a52b9c3. BUG=b:208719081 TEST=FW_NAME=vell emerge-brya coreboot Fixes:a52b9c3 ("mb/google/brya: Move gpio_pm settings for brya variants to baseboards") Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Change-Id: Ideae3dbd9746590db104d93afadbd8d574298b83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-02mb/google/brya: Remove `mb_gpio_lock_config()` override functionSubrata Banik
This patch removes `lockable_brya_gpios` lists and `mb_gpio_lock_config` override function from brya baseboard directory as the variant GPIO pad configuration table is now capable of locking GPIO PADs. BUG=b:208827718 TEST=Able to built and boot brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ifc7354f2ae3817459b5494d572c603eba48ec66a Reviewed-on: https://review.coreboot.org/c/coreboot/+/61503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-02-02mb/google/brya: Lock FPMCU pins in brask and brya baseboardsSubrata Banik
This applies a configuration lock to the FPMCU SPI and IRQ GPIOs for all brya and brask variants. BUG=b:208827718 TEST=cat /sys/kernel/debug/pinctrl/INTC1055\:00/pins suggests `FPMCU_*` (F11-F13 and F15-F16) are locked. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1d0b8a5aed6ea54bcfaa267cae5ca78595396ce5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>