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authorEric Lai <ericr_lai@compal.corp-partner.google.com>2022-02-08 11:11:50 +0800
committerFelix Held <felix-coreboot@felixheld.de>2022-02-09 23:26:40 +0000
commit6c10007b4208769540c37c4eaf17383522ee277d (patch)
tree4f67a6ddd4396ab49d961855ce2f12c2170d969b /src/mainboard/google
parent0bcf771cd22a9ef92101ad2211b9ef300fada7dd (diff)
mb/google/var/primus4es: Add gpios to lock
Variant should honor locked gpios from baseboard, but not the last. Variant can add more gpios to lock if needed. BUG=b:216583542 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that primus boots successfully to kernel. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I71f7391df6d827b75f87e54e17f6f7983a9e829b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/brya/variants/primus4es/gpio.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/google/brya/variants/primus4es/gpio.c b/src/mainboard/google/brya/variants/primus4es/gpio.c
index 42d2bcb4f7..c5b6708c60 100644
--- a/src/mainboard/google/brya/variants/primus4es/gpio.c
+++ b/src/mainboard/google/brya/variants/primus4es/gpio.c
@@ -23,13 +23,13 @@ static const struct pad_config override_gpio_table[] = {
/* B2 : VRALERT# ==> NC */
PAD_NC(GPP_B2, NONE),
/* B3 : PROC_GP2 ==> eMMC_PERST_L */
- PAD_CFG_GPO(GPP_B3, 1, DEEP),
+ PAD_CFG_GPO_LOCK(GPP_B3, 1, LOCK_CONFIG),
/* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG),
/* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG),
/* B15 : TIME_SYNC0 ==> NC */
- PAD_NC(GPP_B15, NONE),
+ PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG),
/* C3 : SML0CLK ==> NC */
PAD_NC(GPP_C3, NONE),
@@ -37,17 +37,17 @@ static const struct pad_config override_gpio_table[] = {
PAD_NC(GPP_C4, NONE),
/* D3 : ISH_GP3 ==> NC */
- PAD_NC(GPP_D3, NONE),
+ PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
/* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
/* D6 : SRCCLKREQ1# ==> NC */
PAD_NC(GPP_D6, NONE),
/* D13 : ISH_UART0_RXD ==> NC */
- PAD_NC(GPP_D13, NONE),
+ PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG),
/* D14 : ISH_UART0_TXD ==> USB_A1_RT_RST_ODL */
- PAD_CFG_GPO(GPP_D14, 1, DEEP),
+ PAD_CFG_GPO_LOCK(GPP_D14, 1, LOCK_CONFIG),
/* D18 : UART1_TXD ==> SD_PE_RST_L */
- PAD_CFG_GPO(GPP_D18, 1, PLTRST),
+ PAD_CFG_GPO_LOCK(GPP_D18, 1, LOCK_CONFIG),
/* E3 : PROC_GP0 ==> NC */
PAD_NC(GPP_E3, NONE),