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authorTony Huang <tony-huang@quanta.corp-partner.google.com>2022-02-10 16:19:03 +0800
committerFelix Held <felix-coreboot@felixheld.de>2022-02-12 17:26:15 +0000
commit489300358114fe6f9f43aaf02d72c64bf8bc54aa (patch)
tree0bab6fa59bbe57378f601eb89f048e8ca34a703f /src/mainboard/google
parentb2e9193231e002b2a3bb33a80d18f76b9abc0a10 (diff)
mb/google/brya/var/agah: Update Aux settings
Agah port 0 does not have a retimer so the port needs to be configured for the SOC to handle Aux orientation flipping. Add the "TcssAuxOri" and "typec_aux_bias_pads" to lets the SoC IOM firmware control the Aux DC bias voltages. BUG=b:210970640 BRANCH=NONE TEST=emerge-draco coreboot chromeos-bootimage Change-Id: I1fa5c4574b1a0e8dd2f66f3f6382436337c530fa Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/brya/variants/agah/overridetree.cb5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/mainboard/google/brya/variants/agah/overridetree.cb b/src/mainboard/google/brya/variants/agah/overridetree.cb
index 3856df2039..f890582ee5 100644
--- a/src/mainboard/google/brya/variants/agah/overridetree.cb
+++ b/src/mainboard/google/brya/variants/agah/overridetree.cb
@@ -1,5 +1,4 @@
chip soc/intel/alderlake
- register "SaGv" = "SaGv_Enabled"
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
@@ -31,6 +30,10 @@ chip soc/intel/alderlake
},
}"
+ register "SaGv" = "SaGv_Enabled"
+ register "TcssAuxOri" = "1"
+ register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
+
register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2_C1
register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable M.2 WWAN
register "usb2_ports[4]" = "USB2_PORT_EMPTY" #