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2023-11-22google/*: Clean up Kconfig board selection for non-MTK Google Arm boardsJulius Werner
This patch unifies and simplifies the Kconfig selection model for the Gru, Herobrine, Trogdor and Veyron boards according to the model discussed in CB:78972. Also add missing license headers to two Kconfig files while I'm here. Change-Id: If679a05afd10869afba9c2a33b54862e102b5f40 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79022 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-17mb/google/herobrine: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I25b7adccf60abe515d129f8d00383165eccf6431 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79028 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-17soc/qualcomm/{sc7180,sc7280}: Allow building without QC blobs repoFelix Singer
Building coreboot for the Qualcomm SoCs SC7180 and SC7280 requires to include the Qualcomm blobs, which requires to accept their license. However, for various reasons it makes sense to build without blobs, e.g. static analysis or just build-testing. So in order to do that, run the steps integrating the Qualcomm blobs into the coreboot binary only if USE_QC_BLOBS is enabled and also remove guards which prevent building related mainboards when USE_QC_BLOBS is not enabled. Change-Id: I249ac477b8f10e7fa0848e967c23a3b3b9bbd27d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79026 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-06drivers/tpm: Move tis_plat_irq_status to cr50 driverGrzegorz Bernacki
tis_plat_irq_status() function is used only by Google TPM. It should be moved to drivers/tpm/cr50.c. The name of the function was changed to cr50_plat_irq_status(). BUG=b:277787305 TEST=Build all affected platforms Change-Id: I78dc39f2c7b44232b06947d3dfe6afa52807ced8 Signed-off-by: Grzegorz Bernacki <bernacki@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75917 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-05-03Drop many cases of CONFIG_MAINBOARD_PART_NUMBERKyösti Mälkki
We have largely dropped from filling in mainboard_ops.name as unnecessary. A common place should be decided where or if this information is added in the console log. Change-Id: I917222922560c6273b4be91cd7d99ce2ff8e4231 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-02-09mb/google/herobrine: Enable early eMMC init in corebootShelley Chen
Move eMMC init from depthcharge into coreboot to remove it from the critical boot path. Doing so saves us almost 35ms on villager: before change: finished storage device initialization 50,783 after change: finished storage device initialization 16,255 BUG=b:254092907,b:218406702 BRANCH=None TEST=flash new FW onto villager and make sure can boot from eMMC Change-Id: I1af1ec162029120332e7f531f75c3780266d322b Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13soc/qualcomm/sc7280: Update Skuid to support pro/non-proSudheer Kumar Amrabadi
Tranferring a bit to DC through Skuid to update the regulator node in order to support pro and non-pro BUG=b:248187555 TEST=Validate boards are detected correctly on PRO and NON_PRO SKUs Signed-off-by: Sudheer Kumar Amrabadi <quic_samrabad@quicinc.com> Change-Id: Iec392c03c2e2c79d20b1fcb79236ca9e048bfd07 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68385 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09mb/google/{herobrine,peach_pit,trogdor}: Use {read,write}32p()Elyes Haouas
Change-Id: I2e1978f20b085f609cbeb0907374383f2d11fbf0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70474 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-03mb/google/herobrine: NVMe id determined by logical (not physical) bitShelley Chen
NVMe is determined by a logical bit 1, not the physical SKU pin. Thus, (logical) sku_id & 0x2 == 0x2 would mean that the device has NVMe enabled on it. Previously, I thought that it was tied to a physical pin, but this is not correct. BUG=b:254281839 BRANCH=None TEST=flash and boot on villager and make sure that NVMe is not initialized in coreboot. Change-Id: Iaa75d2418d6a2351d874842e8678bd6ad3c92526 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70230 Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02mb/google/herobrine: Update FMD file for multiple ROM sizesMartin Roth
The Piglin & Hoglin boards were built with a couple of different sizes of ROM chips. Despite this, the desire was to use just a single FMD file. The different sizes are already accounted for in Kconfig, so add the Kconfig size here to be used. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Ia75725b0c4d61e832c94160fa4cd455e89c60274 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-30mb/google/herobrine: Mask out upper bits from sku_id()Shelley Chen
When retrieving the SKU id value through the sku_id() function in mainboard_needs_pcie_init(), we only want the values in the lower 5 bits as we can only represent SKU id up to 27. Everything in the higher bits should be masked out because they are not needed. BUG=b:254281839 BRANCH=None TEST=Make sure that NVMe is not initialized Tested on a herobrine board with SKU id 0 Change-Id: I0e786ec392b5e1484cb2ff6d83a8d4fdd698950c Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70164 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-30mb/google/herobrine: Only retrieve sku_id from EC onceShelley Chen
Currently, we are getting the sku id from the EC every time we call the sku_id() function. However, this will never change so we only need to retrieve it once. Inserting exit condition if sku id is already set, then don't get it from the EC again. Also, removing the ram_code function, which does nothing right now. There is already a weak stub_function for this in src/lib/coreboot_table.c that already does the same thing. BUG=b:260740438,b:182963902 BRANCH=None TEST=make sure image still boots to login on herobrine device Change-Id: Ia787968100baf58a41ccce0cf95ed3ec9ce1758a Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Doug Anderson <dianders@chromium.org>
2022-11-18mb/google/herobrine: Implement mainboard_needs_pcie_initShelley Chen
Implement mainboard_needs_pcie_init() for herobrine in order to determine if we need to initialize the pcie links. When the SKU id is unknown or unprovisioned (for example at the beginning of the factory flow), we should still initialize PCIe. Otherwise the devices with NVMe will fail to boot. BUG=b:254281839 BRANCH=None TEST=emerge-herobrine coreboot Change-Id: I8972424f0c5d082165c185ab52a638e8b134064c Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-11-17Revert "mb/google/herobrine: Remove NVMe from device tree"Shelley Chen
This reverts commit d164feb72602da958b644643b44e754f04a1f281. Reason for revert: Herobrine program decided that we wanted to be able to boot from NVMe if one exists. Change-Id: I2d3217c514734608e2ff049b620f4c7acf86de89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69720 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-12ec/google/chromeec: Deprecate dev_index from google_chromeec_rebootCaveh Jalali
This removes the dev_index argument from the google_chromeec_reboot API. It's always set to 0, so don't bother passing it. BUG=b:258126464 BRANCH=none TEST=none Change-Id: Iadc3d7c6c1e048e4b1ab8f8cec3cb8eb8db38e6a Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69373 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-10mb/google/herobrine: Update comment of modem status infoVenkat Thogaru
Updated comment as per guidelines. BUG=b:232302324 TEST=none Signed-off-by: Venkat Thogaru <quic_thogaru@quicinc.com> Change-Id: I6a925477a926e7e9d54e42d662768536318ec8e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-11-07soc/qualcomm/sc7280: Move AOP load and reset handle to RomstageSudheer Kumar Amrabadi
As AOP takes 500 msec delay to get up, moving aop load and reset to romstage improves the performance. BUG=b:218406702 TEST=reboot from AP console (on CRD3) prior to fix (from cbmem dump): 1000:depthcharge start 1,139,809 (152,679) after fix (from cbmem dump): 1000:depthcharge start 1,041,109 (46,353) Signed-off-by: Sudheer Kumar Amrabadi <samrabad@codeaurora.org> Change-Id: Iabc8ee8f6e7b14d237b0aeaae42da8077f9dafc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-10-20mb/google/herobrine: Remove NVMe from device treeShelley Chen
We need to boot eMMC for modem calibration, there is not need for BIOS to initialize NVMe anymore as the kernel will do so. Removing the pci device from the device tree as a first step. BUG=b:185426670, b:254281839 BRANCH=None TEST=Boot after removing from the herobrine device tree. Change-Id: I802dd1361bc56a24ab3d65e6782bc611b7b75ee3 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-10-13mb/google/herobrine: Create zombie variantMaulik Vaghela
Create the zombie variant of the herobrine reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:249180463 BRANCH=None TEST=util/abuild/abuild -p none -t google/herobrine -x -a make sure the build includes GOOGLE_ZOMBIE Signed-off-by: Maulik Vaghela <maulikvaghela@google.com> Change-Id: Ifecf0a6323b20012defbf14bd16ce2f1f41f4714 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Shelley Chen <shchen@google.com>
2022-08-14mb/google/herobrine: Update modem status with skuid infoSudheer Kumar Amrabadi
BUG=b:232302324 TEST=Validated on qualcomm sc7280 development board Observing 9th bit of skuid with below values, 1 means Modem device 0 means non-modem device Signed-off-by: Venkat Thogaru <quic_thogaru@quicinc.com> Change-Id: If62b272a43a4588f96e49c8b2b1d75862d401d31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-08-03mb/google/herobrine: Add support to enable displayVinod Polimera
This change adds support to enable edp gpios, display init for herobrine. BUG=b:182963902,b:216687885 TEST=Validated on qualcomm sc7280 development board. Monitor name: LQ140M1JW49 Change-Id: I01dbe23afbb3d41d87f24cb7dcfa456cb7f133fb Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64885 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-01mb/google/herobrine: Add PCIe domain supportVeerabhadrarao Badiganti
Add PCIe domain support for herobrine by enabling it in the devicetree. BUG=b:182963902,b:216686574,b:181098581 TEST=Verified on Qualcomm sc7280 development board with NVMe card (Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is getting detected in response to 'storage init' command in depthcharge CLI prompt. Output logs: ->dpch: storage init Initializing NVMe controller 1e0f:0001 Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0 * 0: NVMe Namespace 1 1 devices total Also verified NVMe boot path, that is depthcharge is able to load the kernel image from NVMe storage. Change-Id: Ied8fbbc8d20698ee081d93ba184b7d0291bb6a76 Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65137 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-22herobrine: Create Zoglin variantShelley Chen
Zoglin is like Hoglin, but with a smaller flash size, which requires us to create a new variant. BUG=b:239851866 BRANCH=None TEST=Make sure BOARD_GOOGLE_ZOGLIN builds Change-Id: Id1401a052061dcfc1d1ee41b88ce4a11fd9f3d01 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-07-20google/herobrine: Add Evoker variantSheng-Liang Pan
BUG=b:238571507 BRANCH=None TEST=emerge-herobrine coreboot Change-Id: Ie596e5c4b72de84d16571043db4291bbd0825c78 Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Bob Moragues <moragues@chromium.org>
2022-07-18google/herobrine: Support hardware watchdog loggingKshitiz Godara
Add support for hardware watchdog event logging BUG=b:221393157 TEST=Validated on qualcomm sc7280 development board by manually triggering watchdog event and event was logged at next bootup. Signed-off-by: Kshitiz Godara <quic_kgodara@quicinc.com> Change-Id: I94971ab583f49c8a5ac232833215dbdad3a4d272 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65528 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-24sc7280: Enable RECOVERY_MRC_CACHEShelley Chen
Enable caching of memory training data for recovery as well as normal mode. We had HAS_RECOVERY_MRC_CACHE selected in the sc7280 Kconfig, but never allocated a RECOVERY_MRC_CACHE in the herobrine fmap so it never worked. Adding RECOVERY_MRC_CACHE and also removing RO_DDR_TRAINING, RO_LIMITS_CFG, RW_LIMITS_CFG entries which have been deprecated. BUG=b:236995289 BRANCH=None TEST=run dut-control power_state:rec twice and make sure that DDR training doesn't run on the second boot. Change-Id: I39ac7eca4ae94075874324b13c69eef59522e3c5 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-06-01sc7280: Improve performance by removing delays in cpucp initSudheer Kumar Amrabadi
As cpucp prepare takes 300 msec moving to before ramstage BUG=b:218406702 TEST=Validated on qualcomm sc7280 development board observed total timestamp as 1.73 sec from 1.97 sec Change-Id: I1a727514810a505cd1005ae7f52e5215e404b3bb Signed-off-by: Sudheer Kumar Amrabadi <quic_samrabad@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-04-24mainboard/google: Remove unused <boardid.h>Elyes Haouas
Found using: diff <(git grep -l '#include <boardid.h>' -- src/) <(git grep -l 'UNDEFINED_STRAPPING_ID\|BOARD_ID_UNKNOWN\|BOARD_ID_INIT\|board_id(\|ram_code(\|sku_id(' -- src/) |grep "<" Change-Id: I2611be41e8730a9b189b1b0aa3fe62be0757b371 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-21tpm: Refactor TPM Kconfig dimensionsJes B. Klinke
Break TPM related Kconfig into the following dimensions: TPM transport support: config CRB_TPM config I2C_TPM config SPI_TPM config MEMORY_MAPPED_TPM (new) TPM brand, not defining any of these is valid, and result in "generic" support: config TPM_ATMEL (new) config TPM_GOOGLE (new) config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE) config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE) What protocol the TPM chip supports: config MAINBOARD_HAS_TPM1 config MAINBOARD_HAS_TPM2 What the user chooses to compile (restricted by the above): config NO_TPM config TPM1 config TPM2 The following Kconfigs will be replaced as indicated: config TPM_CR50 -> TPM_GOOGLE config MAINBOARD_HAS_CRB_TPM -> CRB_TPM config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE Signed-off-by: Jes B. Klinke <jbk@chromium.org> Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-02herobrine: fix emmc and sd card clocksShelley Chen
Found an issue where emmc and sd clocks were being misconfigured due to using incorrect integer values when called instead of the defined enums. Fixing by splitting the clock_configure_sdcc() function into two (sdcc1 and sdcc2) as there was no commonality between the two cases anyway. As a result, we can also get rid of the clk_sdcc enum. BUG=b:198627043 BRANCH=None TEST=build herobrine image and test in conjunction with CB:63289 make sure assert is not thrown. Change-Id: I68f9167499ede057922135623a4b04202f4da9b5 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-14mb/google/herobrine: consolidate hoglin/herobrine QUP initsShelley Chen
Hoglin and Herobrine (proto1) should share majority of GPIOs. Conslidating the QUP initializations in mainboard. Also, putting fingerprint init in a conditional as not all devices will have an FP sensor. BUG=b:182963902,b:223826899 BRANCH=None TEST=booted BIOS on hoglin and check for i2c errors in dmesg Change-Id: I48ce42760f2c75f04619b967a05909d2b3f28e2c Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-10mb/google/herobrine: Add trackpad initializationRavi Kumar Bokka
Initialize trackpad on Qualcomm reference boards BUG=b:182963902,b:223826899 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Change-Id: I93e866d92cf37887a98de88b4b2d768562515670 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62226 Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25herobrine: Add Villager variantShelley Chen
BUG=b:218415722 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_VILLAGER -x -a -B Change-Id: I84935ea280023cb0df1dd51fcd2a83d80db17710 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-02-17mb/google/herobrine: Disable fingerprint sensor on CRD devicesRavi Kumar Bokka
Qualcomm CRD devices do not have a fingerprint sensor so removing the QUP configuration for it. This QUP also coincidentally is the same as the one used for the TPM, so this initially was also causing TPM communication issues during bootup as the QUP was being reconfigured during the later stages after QcLib execution. BUG=b:206581077 BRANCH=None TEST=Boot to kernel without any CR50 communication errors Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Change-Id: I8d13b67796b70b0b7e9a4721cca0b8a54b2b27c1 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61716 Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-16mb/google/herobrine: Add Gigadevice SPI PartShelley Chen
BUG=b:182963902 BRANCH=None TEST=emerge-herobrine coreboot Change-Id: I73dc695afb7aa2b32aa966070eb057c828073d47 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-02-16mb/google/herobrine: Alphabetize SPI_FLASH configsShelley Chen
BUG=b:182963902 BRANCH=None TEST=None Change-Id: Ia73460d335e859644511b7e9ca80111a919baf2c Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-02-15herobrine: update SPI-NOR config optionsT Michael Turney
Configuration support for 4k-byte addressing mode BUG=b:215605946 TEST=Validated on qualcomm sc7280 developement board Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com> Signed-off-by: Shaik Sajida Bhanu <quic_c_sbhanu@quicinc.com> Signed-off-by: T Michael Turney <quic_mturney@quicinc.com> Change-Id: If82de6204446251dded1b83684677e6eb536e6fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/61279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-02-04Hoglin: Switch to using i2c TPMShelley Chen
Redefine Hoglin to be used for Qualcomm's CRD 3.0 board, which uses i2c for TPM instead of SPI. From now on, the Piglin board will be used for all the Qualcomm reference boards that use SPI for TPM. BUG=b:206581077 BRANCH=None TEST=hacked an 8MB image and make sure boots on herobrine board Change-Id: Ie1d71ec8b01f305c1c8fa815a0fb9b7ee022cc19 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-28mb/google/herobrine: Add senor support QUP FW for I2C and SPIRavi Kumar Bokka
Add senor board to QUP FW load for: APPS I2C, ESIM SPI & fingerprint SPI. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board. Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Change-Id: I6fdd09bb437547e6d12eb60c4b2917d2a3074618 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-01-10src/mainboard/google: Remove unused <console/console.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<" Change-Id: I3a6a64273e3883942655272a544c41e90ef519fd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-08mb/google/herobrine: Add support for audioSrinivasa Rao Mandadapu
Add GPIO configuration for target specific i2s ports. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Boot on herobrine board (no speakers to test yet) Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org> Change-Id: I2ce95332f892d5d4acb2755307df84d37feb8002 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-07mb/google/herobrine: Initialize EC and TPM devicesShelley Chen
Initialize EC and H1/TPM instances on herobrine devices. BUG=b:182963902 BRANCH=None TEST=Validated on qualcomm sc7280 development board and verified booting on herobrine. Change-Id: I8cbdd1d59a0166688d52d61646db1b6764879a7c Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-06mb/google/herobrine: Fix board idShelley Chen
The board id assignment CL (CB:56642) landed after BOARD_GOOGLE_HEROBRINE has been deprecated to BOARD_GOOGLE_HEROBRINE_REV0 (CB:60284). Fix it to accomodate for the GOOGLE_HEROBRINE_REV0 board updates. BUG=b:211644878 BRANCH=None TEST=built all variants of herobrine to make sure it compiles. For reference: ============= CB:56642: commit 8b63dac06184e56ce40d82d982e983ac79163551 Author: Ravi Kumar Bokka <rbokka@codeaurora.org> Date: Tue Jul 27 19:29:18 2021 +0530 google/herobrine: configure gpio to detect board ID ============= CB:60284: commit 8bdbe23a93008597d99472747ba3415617f8c074 Author: Shelley Chen <shchen@google.com> Date: Tue Dec 21 13:17:33 2021 -0800 mb/google/herobrine: Transition BOARD_HEROBRINE to BOARD_HEROBRINE_REV0 ============= Change-Id: I6dab994e65eadff303eb88a63b8dd81e19694678 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-05mb/google/herobrine: Initialize `pins` to fix the compilation issueSubrata Banik
Fix compilation issue introduced with commit 8b63dac0 (google/herobrine: configure gpio to detect board ID) by initialising the gpio pins. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I084fec777b56f402efb3b04a1d358cd5b0891846 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2022-01-05google/herobrine: configure gpio to detect board IDRavi Kumar Bokka
BUG=b:182963902, b:193807794 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Change-Id: I6de2a7e7b11ecce8325e0fd44dc7221d73729390 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-01-04mb/google/herobrine: Transition BOARD_HEROBRINE to BOARD_HEROBRINE_REV0Shelley Chen
Deprecating Herobrine Rev0 board. The next board is very different from the Rev0 board (ie: Most GPIOs have been remapped). Deprecating and reusing the GOOGLE_BOARD_HEROBRINE Kconfig for next board and reslotting the old GOOGLE_BOARD_HEROBRINE source under GOOGLE_BOARD_HEROBRINE_REV0 config. Want to keep the code around in case somebody needs it but we can remove this code in future after we recall all the Rev0 devices. Also updating the remapped GPIOs to match those of the current herobrine board. BUG=b:211644878 BRANCH=None TEST=emerge-herobrine coreboot Change-Id: I67a0b282710031b927ce9022c7c535bd8d4ca1aa Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Douglas Anderson <dianders@chromium.org>
2022-01-01src: Remove duplicated includesElyes HAOUAS
Change-Id: I50cdffca34a6150ac11c3e83e1a603b766d1b84e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-12-01herobrine: Assert gpio for USB_HUB_LDO_ENSandeep Maheswaram
Some herobrine variants have USB hub powered by discrete LDO that is controlled by USB_HUB_LDO_EN gpio. Assert the GPIO on boot. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board. Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Change-Id: Ia94e046f9eb0d3ce593f3445e0203a7391c14de2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-30mb/google/herobrine: Initialize USB by calling SOC methodRavi Kumar Bokka
Initialize by calling `setup_usb_host0()` from SOC code BUG=b:182963902 TEST=Validated USB enumeration on qcom sc7280 development board Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Change-Id: Ic378352a97e4f3ed89089f1f7545f8ebb172b1f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-11-15mb/google/herobrine: Use same I2C/SPI configs for piglin and hoglinShelley Chen
As Hoglin variant was recently added, need to make sure that it uses the same configs as piglin. BUG=b:197366666 BRANCH=None TEST=create hoglin image and make sure that it boots on CRD 2.0 Change-Id: I14497a205262ac1081c24631e4fd8d39bb804fce Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59273 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-15Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"Hsuan-ting Chen
This reverts commit adb393bdd6cd6734fa2672bd174aca4588a68016. This relands commit 6260bf712a836762b18d80082505e981e040f4bc. Reason for revert: The original CL did not handle some devices correctly. With the fixes: * commit 36721a4 (mb/google/brya: Add GPIO_IN_RW to all variants' early GPIO tables) * commit 3bfe46c (mb/google/guybrush: Add GPIO EC in RW to early GPIO tables) * commit 3a30cf9 (mb/google/guybrush: Build chromeos.c in verstage This CL also fix the following platforms: * Change to always trusted: cyan. * Add to early GPIO table: dedede, eve, fizz, glados, hatch, octopus, poppy, reef, volteer. * Add to both Makefile and early GPIO table: zork. For mb/intel: * adlrvp: Add support for get_ec_is_trusted(). * glkrvp: Add support for get_ec_is_trusted() with always trusted. * kblrvp: Add support for get_ec_is_trusted() with always trusted. * kunimitsu: Add support for get_ec_is_trusted() and initialize it as early GPIO. * shadowmountain: Add support for get_ec_is_trusted() and initialize it as early GPIO. * tglrvp: Add support for get_ec_is_trusted() with always trusted. For qemu-q35: Add support for get_ec_is_trusted() with always trusted. We could attempt another land. Change-Id: I66b8b99d6e6bf259b18573f9f6010f9254357bf9 Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-10-15Revert "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"Hsuan-ting Chen
This reverts commit 6260bf712a836762b18d80082505e981e040f4bc. Reason for revert: This CL did not handle Intel GPIO correctly. We need to add GPIO_EC_IN_RW into early_gpio_table for platforms using Intel SoC. Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: Iaeb1bf598047160f01e33ad0d9d004cad59e3f75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57951 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-07sc7280: Add SHRM firmware supportRavi Kumar Bokka
SHRM is a system hardware resource manager. It is used to manage run time DDRSS activities. DDRSS stands for DDR subsystem. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board by trying DDR clocks which through SHRM RSI command. Change-Id: I44484573a829eaefbd34907c6fe78d427506a762 Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-29herobrine: Initialize SAR sensor QUPShelley Chen
Initializing SAR sensor (QUP2, address 0x988000) BUG=b:198456205 BRANCH=None TEST=Boot into kernel and make sure no i2c errors for 0x988000 in dmesg Change-Id: I75b0e9173d4c49b5e7308158a678964d6637b225 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-09-29mb/google/herobrine: Change preprocessor to C codeShelley Chen
BUG=b:182963902 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_HEROBRINE -x -a -c max -B Change-Id: I10f8a9682200b883474dc385331c5dae84cbdb08 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-09-29herobrine: Add fingerprint power sequencingShelley Chen
For Herobrine variants that include a finger print sensor, we will need to power sequence it. We are using the same FP sensor as trogdor, so we will follow the timings used for trogdor from CL:2695676. BUG=b:198474942 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_HEROBRINE -x -a -c max -B Change-Id: Ica6eafc47cf1b95eeb8d94c6e0a8c88519665e3f Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58021 Reviewed-by: Alexandru Stan <amstan@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-21src/mainboard/herobrine: Load GSI FW in ramstageRavi Kumar Bokka
Load GSI FW in ramstage and make it part of RW BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board. Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I3d9caa0921fcf9ad67f1071cdf769a99fb6d1a30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-21src/mainboard/herobrine: Load respective QUP FW for I2C and SPIRajesh Patil
Loading QUP FW as per herobrine and piglin configuration for I2C, SPI and UART. As part of the code clean up, update the header files of the QUP drivers with the correct path. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board. Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: Ic218c6a91ffc4484830446d707d1f3403e2dc46b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-20herobrine: Add Hoglin variantShelley Chen
Create a variant for the QC CRD device. BUG=b:197366666 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_HOGLIN -x -a -B Change-Id: I883d17b3ad3c7e44a00f0d0e7007c119417c5028 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-09-16vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_mainHsuan Ting Chen
vboot_reference is introducing a new field (ctx) to store the current boot mode in crrev/c/2944250 (ctx->bootmode), which will be leveraged in both vboot flow and elog_add_boot_reason in coreboot. In current steps of deciding bootmode, a function vb2ex_ec_trusted is required. This function checks gpio EC_IN_RW pin and will return 'trusted' only if EC is not in RW. Therefore, we need to implement similar utilities in coreboot. We will deprecate vb2ex_ec_trusted and use the flag, VB2_CONTEXT_EC_TRUSTED, in vboot, vb2api_fw_phase1 and set that flag in coreboot, verstage_main. Also add a help function get_ec_is_trusted which needed to be implemented per mainboard. BUG=b:177196147, b:181931817 BRANCH=none TEST=Test on trogdor if manual recovery works Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: I479c8f80e45cc524ba87db4293d19b29bdfa2192 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57048 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-16mainboard/google: Update the TLMM registers for sdhcShaik Sajida Bhanu
Update the TLMM register values for eMMC and SD card on Trogdor, Herobrine and Mistral boards. BUG=b:196936525 TEST=Validated on qualcomm sc7280 and sc7180 development board and checked basic boot up. Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org> Change-Id: Iccdb7757027c6de424a82e4374bad802501ac83c Reviewed-on: https://review.coreboot.org/c/coreboot/+/57450 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-16mb/google: Unify all variants to start with "-> "Martin Roth
All variants originally had been changed to start with an arrow with two spaces following it to line up with the platform name. A number of recent platforms were added only using a single space. This change updates them all to have two spaces so they line up again. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Iab9e6207fff5a7d2f6d76e5ca33eeaca721a224f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-16mb/google/herobrine: Increase the ROM size to 64 MBShaik Sajida Bhanu
SPI NOR size should match with coreboot ROM size. On QCOM Piglin board SPI NOR size is 64MB and the default coreboot ROM size is 8MB. So, update the coreboot ROM size to match with SPI NOR size. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board and checked basic boot up. Change-Id: I78f3f402b383bbad303f26c31d3d973c5f20d172 Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-03soc/qualcomm/sc7280: DDR One-Time-Training SupportRavi Kumar Bokka
Introduce DDR One-Time-Training Support Device reboots without training from second iteration and also DDR training data is 32kb size, hence update required in memlayout and to sync with upstream changes the Fmap size even got bumped up. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Change-Id: I81038c5c7802c154f4310509c6c64710580b8ce4 Signed-off-by: Sudheer Kumar Amrabadi <samrabad@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-03mainboard/google/herobrine: Configure SDCC clockShaik Sajida Bhanu
Configure 384MHz for eMMC clock and 50MHz for SD card clock. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Change-Id: I8acbce58614add0228adc39289762da10937cbe2 Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-07-26mb/*: Specify type of `MAINBOARD_PART_NUMBER` onceAngel Pons
Specify the type of the `MAINBOARD_PART_NUMBER` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: I3692f9e82fe90af4d0da1d037018a20aa1b45793 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56554 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `MAINBOARD_DIR` onceAngel Pons
Specify the type of the `MAINBOARD_DIR` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: If1cc538b0c4938dac193699897b690e402b3c1e8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56553 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-23herobrine: get boardid from GPIO configurationRavi Kumar Bokka
Getting boardid information for the different SKU variants BUG=b:182963902, b:193807794 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Change-Id: I2b7625f9b98563438d1ac20e6f29411ef1058cf4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-07-22mainboard/google/herobrine: Add configuration for SD card detect pinShaik Sajida Bhanu
Without this configuration, even though there is no SD card it shows as SD card is present and host controller waits for card to respond. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board with SD card and without SD card, make sure if SD card not present then host controller should not wait for card to respond. Change-Id: I5dc5ba10c98d606d98e7d4f4c41c3e4f45e94452 Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-07-21mb/google/herobrine: Retrieve SKU ID from ECPhilip Chen
BUG=b:186264627 BRANCH=none TEST=build herobrine Signed-off-by: Philip Chen <philipchen@google.com> Change-Id: Id3faf7af64c0129ec646a01085adc43b561225d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-06-29mb/google/herobrine: Add Senor and Piglin variantsShelley Chen
Add configs for Herobrine variants. Also enable ec sw sync as this should not be disabled by default. BUG=b:182963902 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_SENOR -x -a -B ./util/abuild/abuild -p none -t GOOGLE_PIGLIN -x -a -B Change-Id: Ide4e375aa0236dce65a954a2f68455d05fa841eb Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-05-19herobrine: Enable macronix SPI configShaik Sajida Bhanu
Enable macronix SPI config on herobrine board. BUG=b:182963902 Change-Id: I505ee95d9f2ca16baf244135b3e2e8fe72f93491 Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-04-15herobrine: sc7280: Provide initial mainboard supportT Michael Turney
BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board Change-Id: I428cf1a461ee63215f5683abbfed90202d1b2a88 Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-24 20:36:41 +0000