diff options
| author | Sudheer Kumar Amrabadi <samrabad@codeaurora.org> | 2022-03-22 20:00:29 +0530 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2022-06-01 00:54:08 +0000 |
| commit | dfe817e45165fdbb8f4f7f83de83710cc46e75d6 (patch) | |
| tree | 63d67295912e286202f49645d0636e451dcfae6c /src/mainboard/google/herobrine | |
| parent | 363202b43589ec240c4a0c8f5b449fbd5c1333f8 (diff) | |
sc7280: Improve performance by removing delays in cpucp init
As cpucp prepare takes 300 msec moving to before ramstage
BUG=b:218406702
TEST=Validated on qualcomm sc7280 development board observed
total timestamp as 1.73 sec from 1.97 sec
Change-Id: I1a727514810a505cd1005ae7f52e5215e404b3bb
Signed-off-by: Sudheer Kumar Amrabadi <quic_samrabad@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Diffstat (limited to 'src/mainboard/google/herobrine')
| -rw-r--r-- | src/mainboard/google/herobrine/romstage.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/herobrine/romstage.c b/src/mainboard/google/herobrine/romstage.c index 2ea78b8f91..97ce5a7c77 100644 --- a/src/mainboard/google/herobrine/romstage.c +++ b/src/mainboard/google/herobrine/romstage.c @@ -5,6 +5,7 @@ #include <soc/qclib_common.h> #include "board.h" #include <soc/shrm.h> +#include <soc/cpucp.h> static void prepare_usb(void) { @@ -18,6 +19,7 @@ static void prepare_usb(void) void platform_romstage_main(void) { shrm_fw_load_reset(); + cpucp_prepare(); /* QCLib: DDR init & train */ qclib_load_and_run(); prepare_usb(); |