diff options
author | Shelley Chen <shchen@google.com> | 2022-11-16 16:59:27 -0800 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2022-11-18 15:46:22 +0000 |
commit | b5af064f5493b6959d74dfbd948a4666d2a5cdc2 (patch) | |
tree | 18228580a39ca7e01e3cd4087ab638a16313b1ef /src/mainboard/google/herobrine | |
parent | ce4dc66319809fb9002ceb8df9c96894df26709f (diff) |
mb/google/herobrine: Implement mainboard_needs_pcie_init
Implement mainboard_needs_pcie_init() for herobrine in order to
determine if we need to initialize the pcie links. When the SKU id is
unknown or unprovisioned (for example at the beginning of the factory
flow), we should still initialize PCIe. Otherwise the devices with
NVMe will fail to boot.
BUG=b:254281839
BRANCH=None
TEST=emerge-herobrine coreboot
Change-Id: I8972424f0c5d082165c185ab52a638e8b134064c
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/mainboard/google/herobrine')
-rw-r--r-- | src/mainboard/google/herobrine/mainboard.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/src/mainboard/google/herobrine/mainboard.c b/src/mainboard/google/herobrine/mainboard.c index ece6d6859a..2648392227 100644 --- a/src/mainboard/google/herobrine/mainboard.c +++ b/src/mainboard/google/herobrine/mainboard.c @@ -8,10 +8,12 @@ #include <delay.h> #include <device/device.h> #include <device/mmio.h> +#include <ec/google/chromeec/ec.h> #include <edid.h> #include <soc/clock.h> #include <soc/display/mdssreg.h> #include <soc/display/edp_ctrl.h> +#include <soc/pcie.h> #include <soc/qupv3_config_common.h> #include <soc/qup_se_handlers_common.h> #include <soc/qcom_qup_se.h> @@ -82,6 +84,30 @@ static void display_startup(void) } } +/* + * Determine if board need to perform PCIe initialization. On Herobrine, + * resistor strapping will be such that bit 0 will be assigned 2 (high Z) if it + * is an NVMe enabled platform. + */ +bool mainboard_needs_pcie_init(void) +{ + uint32_t sku = sku_id(); + + if (sku == CROS_SKU_UNKNOWN) { + printk(BIOS_WARNING, "Unknown SKU (%#x); assuming PCIe", sku); + return true; + } else if (sku == CROS_SKU_UNPROVISIONED) { + printk(BIOS_WARNING, "Unprovisioned SKU (%#x); assuming PCIe", sku); + return true; + } + + if ((sku % 3) == 2) + return true; + + /* Otherwise, eMMC */ + return false; +} + static void mainboard_init(struct device *dev) { /* Configure clock for eMMC */ |