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2022-03-24drivers/net/r8168: Add support for Realtek RTL8111KRaihow Shi
The Realtek RT8168 and RTL8111K have a similar programming interface, therefore add the PCI device ID for the RTL8111K into driver for support. BUG=b:226253265 TEST=emerge-brask coreboot chromeos-bootimage. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I5ad8f14483393d6f25026847cc0d4229d362bba0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-23soc/intel/adl-n: Add device ID for TCSS XHCIMaulik V Vaghela
This patch adds TCSS XHCI device ID for ADL-N CPU which is required for USB3 port enumeration. Document Reference: 645548 revision 1.0 (Chapter 2.3) BUG=None BRANCH=None TEST=Check if device is detected correctly and ACPI entries are generated for device 0d.0 Change-Id: Id5d42d60eb05137406ef45b9e87e27948fc3b674 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-09soc/intel/common: Include Meteor Lake device IDsWonkyu Kim
Reference: chapter2 in Meteor Lake EDS vol1 (640228) Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ie71abb70b88db0acec8a320c3e2c20c54bbb4a8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/62581 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-08device/mmio.h: Move readXp/writeXp helpers to device/mmio.hJianjun Wang
These helpers are not architecture dependent and it might be used for different platform. Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: Ic13a94d91affb7cf65a2f22f08ea39ed671bc8e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62561 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-07src: Make PCI ID define names shorterFelix Singer
Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with PCI_{DID,VID}_ using the commands below, which also take care of some spacing issues. An additional clean up of pci_ids.h is done in CB:61531. Used commands: * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g' * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g' Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-02-28soc/amd/sabrina: Add XHCI configurationJon Murphy
Add xhci 2 controller support for additional USB port/ Dummy setting BUG=b:214413631 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I5c8885bf46ddbfc85b31585a4da7f746c1a6bcd5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-21include/device/dram/ddr3.h: Don't redefine 'printram(x, ...)'Elyes HAOUAS
'printram(x, ...)' is already defined in 'include/device/dram/common.h' file Change-Id: I75e19065b9e713df3190202b7ca9e9cd8f3f44a6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-16device: Add support for PCIe Resizable BARsTim Wawrzynczak
Section 7.8.6 of the PCIe spec (rev 4) indicates that some devices can indicates support for "Resizable BARs" via a PCIe extended capability. When support this capability is indicated by the device, the size of each BAR is determined in a different way than the normal "moving bits" method. Instead, a pair of capability and control registers is allocated in config space for each BAR, which can be used to both indicate the different sizes the device is capable of supporting for the BAR (powers-of-2 number of bits from 20 [1 MiB] to 63 [8 EiB]), and to also inform the device of the size that the allocator actually reserved for the MMIO range. This patch adds a Kconfig for a mainboard to select if it knows that it will have a device that requires this support during PCI enumeration. If so, there is a corresponding Kconfig to indicate the maximum number of bits of address space to hand out to devices this way (again, limited by what devices can support and each individual system may want to support, but just like above, this number can range from 20 to 63) If the device can support more bits than this Kconfig, the resource request is truncated to the number indicated by this Kconfig. BUG=b:214443809 TEST=compile (device with this capability not available yet), also verify that no changes are seen in resource allocation for google/brya0 before and after this change. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I14fcbe0ef09fdc7f6061bcf7439d1160d3bc4abf Reviewed-on: https://review.coreboot.org/c/coreboot/+/61215 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-16soc/intel/alderlake: Correct Alder Lake M/N ESPI device IDKrishna Prasad Bhat
Alder Lake M/N ESPI ID 18 was incorrectly assigned to be 0x5482. Assign it to the correct value. Reference documents: 619501, 645548. Change-Id: I08bd218fd128497825b96aa5b9496826afa620d2 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61947 Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-11soc/intel/common: Re-use Alder Lake-M device IDs for Alder Lake-NUsha P
Few of the Alder Lake-N Device IDs according to EDS, are named as ADL_M IDs in the current code. Hence rename those device IDs as ADL_M_N and use them for Alder Lake-N platform. Document Number: 619501, 645548 Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I6042017c6189cbc3ca9dce0e50acfb68ea4003f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-10soc/intel/common: Add Crash Log and PMC SRAM PCI device IDsTim Wawrzynczak
Add Alder Lake and Tiger Lake specific Crash Log and PMC SRAM device IDs. Document Number: 619501, 645548 Change-Id: I64b58b8c345bd54774c4dab7b65258714cd8dc9e Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-02-10device: Add pciexp_find_next_extended_cap functionTim Wawrzynczak
Some PCIe devices have extended capability lists that contain multiples instances of the same capability. This patch provides a function similar to pciexp_find_extended_cap that can be used to search through multiple instances of the same capability by returning the offset of the next extended capability of the given type following the passed-in offset. The base functionality of searching for a given capability from an offset is extracted to a local helper function and both pciexp_find_extended_cap and pciexp_find_next_extended_cap use this helper. Change-Id: Ie68dc26012ba57650484c4f2ff53cc694a5347aa Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-01-31soc/intel/alderlake: Add Alder Lake P IGD device IDsKane Chen
This patch adds additional IGD device IDs as per document 638514. BUG=b:216420554 TEST=coreboot is able to probe the IGD device during PCI enumeration. Change-Id: I0cafe92581c454da5e4aeafd7ad52f0e65370b11 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61441 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-25soc/intel/common: Include Alder Lake-N device IDsUsha P
Add Alder Lake-N System Agent, PCIE, UFS, IPU and CNVI device IDs. Document: Alder Lake N Platform EDS Volume 1 (Doc# 645548) Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I0a383816f818b794cf1211766c27937b3b8daa31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-01-24device: constify pciexp_find_extended_cap()Tim Wawrzynczak
The object pointed to by the struct device * argument is not modified, therefore it can be made const. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I300d2a59eb0513ddd08d4f1d2a3c6eb829e3f836 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-18soc/intel/common: Add Alder Lake N eMMC device IDKrishna Prasad Bhat
Add eMMC device ID for Alder Lake N SOC. Reference: Alder Lake N Platform EDS Volume 1 (Doc# 645548) Change-Id: Id35ec2d508bec8ff7d6f1c5fbfaf209d42b25c72 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-01-17pci_ids.h: Make Denverton IDs consistent with other Intel SoCsJeff Daly
Align Denverton PCI ID define names with other Intel SoCs. Also, update the names in SoC code accordingly. Signed-off-by: Jeff Daly <jeffd@silicom-usa.com> Change-Id: Id4b4d971ef8f4b3ec5920209d345edbbcfae4dec Reviewed-on: https://review.coreboot.org/c/coreboot/+/60879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-12include/device/pci_ids.h: add PCI IDs for AMD Family 17h Model A0h SoCFelix Held
The PCI IDs of the ACP (audio co-processor), the non-GPU HDA audio, the SMBus and the LPC devices haven't changed from the previous generations of Zen-based APUs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I41e0a57671b9ef2938b7798d5826de43bea8fe12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-10soc/intel/alderlake: Update the ADL-P SKU parameters for VR domainsCurtis Chen
We support all the ADL-P 15W/28W/45W SKU's and map them with the latest VR configurations. These config values are generated by iPDG application with ADL-P platform package tool. RDC Kit ID for the iPDG tools * Intel(R) Platform Design Studio Installer: 610905 * Intel(R) Platform Design Studio - Libraries: 613643 * Intel(R) Platform Design Studio - Platform ADL-P (Partial): 627345 * Intel(R) Platform Design Studio - Platform ADL-P (Full): 630261 BUG=b:211365920 TEST=Build and check fsp log to confirm the settings are set properly. Signed-off-by: Curtis Chen <curtis.chen@intel.com> Change-Id: Ida7a6df0422a9a3972646cb3bdd0112b5efa2755 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-12-22device: Make pciexp_get_ltr_max_latencies a public functionTim Wawrzynczak
Some device drivers may need to get access to the LTR values for their respective devices, therefore export this function instead of marking it static. BUG=b:204343849 Change-Id: Id372600e8adec0d55d3483726bb9353139685774 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2021-12-03drivers/net/r8168: Add support for Realtek RT8125Alan Huang
The Realtek RT8168 and RT8125 have a similar programming interface, therefore add the PCI device ID for the RT8125 into driver for support. BUG=b:193750191 TEST=emerge-brask coreboot chromeos-bootimage. Test on brask whose NIC is RT8125. Check if the default MAC is written into the NIC. Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Change-Id: Iaa4c41f94fd6e5fd6393abbb30bfc22a149f5d71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-29soc/intel/common: Include Alder Lake-N device IDsUsha P
Add Alder Lake-N specific CPU, System Agent, PCH (Alder Point aka ADP), IGD device IDs. Document Number: 619501, 645548 Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I0974fc6ee2ca41d9525cc83155772f111c1fdf86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-11-29pci_mmio_cfg: Rename pcicfg to pci_map_busJianjun Wang
Rename pcicfg to pci_map_bus and add prototype for the platforms not supporting ECAM. Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: Id9517c5ec4fa6b7c7a34552bfdc6d509927f6730 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-29device/pci_device.c: Scan only one device for PCIeJianjun Wang
Only scan one device if it's a PCIe downstream port. A PCIe downstream port normally leads to a link with only device 0 on it. As an optimization, scan only for device 0 in that case. Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: Id184d03b33e1742b18efb3f11aa9b2f81fa03806 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-25soc/intel/elkhartlake: Update SA DIDs TableRick Lee
Update SA table as per latest EDS (Doc no: 601458). Add extra SKUs accordingly. Signed-off-by: Rick Lee <rick.lee@intel.com> Change-Id: Ia2bb9e54456dbea634c2b8e192f9fe813b9e6706 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Lean Sheng Tan Reviewed-by: Praveen HP <praveen.hodagatta.pranesh@intel.com>
2021-11-23drivers/genesyslogic/gl9750: Add driver for Genesys Logic GL9750Ben Chuang
The device is a PCIe Gen1 to SD 3.0 card reader controller to be used in the Chromebook. The datasheet name is GL9750S and the revision is 01. The patch disables ASPM L0s. BUG=b:206014046 TEST=Verify GL9750 enters L1 by observing CLKREQ# de-asserts. Signed-off-by: Ben Chuang <benchuanggli@gmail.com> Change-Id: I6d60cef41baade7457a159d3ce2f8d2e6b66e71c Reviewed-on: https://review.coreboot.org/c/coreboot/+/59429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-15device/pci_rom: Add vga_oprom_preloadRaul E Rangel
This method will allow preloading the VGA_BIOS_FILE. By preloading the file, into cbfs_cache we reduce boot time. In the future we can also add support for loading the second VGA_BIOS_FILE and the DGPU VGA_BIOS_FILE. BUG=b:179699789 TEST=Boot guybrush to OS and verify 12 ms reduction in boot time Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Icb54fe3a942e9507ff6f1173ba5620a8f4ce6549 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-11-12soc/intel/common/block/pcie: Add ADL-P CPU PCIe Device IDsTracy Wu
List of changes: 1. Add PEG60/10/62 IDs (0x464d/0x460d/0x463d) into device/pci_ids.h 2. Add these new IDs into pcie_device_ids[] in pcie.c BUG=b:205668996 TEST=Build and check fsp log to confirm the settings are set properly. Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com> Change-Id: Idc8a09b0579e1e6053ed2e35b7556a180a5f0088 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-11-11device/azalia_device: Drop unused function parameterAngel Pons
The `dev` parameter of the `azalia_codecs_init()` function is not used. Remove it, and update all call sites accordingly. Change-Id: Idbe4a6ee5e81d5a7fd451fb83e0fe91bd0c09f0e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59119 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-11device/azalia_device: Adapt and export `codec_init()`Angel Pons
Make the `codec_init()` function non-static so that it can be used in other places. Rename it to `azalia_codec_init()` for consistency with the other functions of the API. Also, update the function's signature to make it more flexible. Remove the unused `dev` parameter and allow callers to pass the verb table to use. Update the original call site to preserve behavior. Change-Id: I5343796242065b5fedc78cd95bcf010c9e2623dd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59117 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-11device/azalia_device: Export `codecs_init()`Angel Pons
Make the `codecs_init()` function non-static so that it can be used in other places. Rename it to `azalia_codecs_init()` to avoid name clashes with static definitions in southbridge code (which will be removed in subsequent commits). Change-Id: I080a73102b0c4f9f8a283cd93bba9b3b23169be0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-11-11arch/x86: Refactor the SMBIOS type 17 write functionSubrata Banik
List of changes: 1. Create Module Type macros as per Memory Type (i.e. DDR2/DDR3/DDR4/DDR5/LPDDR4/LPDDR5) and fix compilation issue due to renaming of existing macros due to scoping the Memory Type. 2. Use dedicated Memory Type and Module type for `Form Factor` and `TypeDetail` conversion using `get_spd_info()` function. 3. Create a new API (convert_form_factor_to_module_type()) for `Form Factor` to 'Module type' conversion as per `Memory Type`. 4. Add new argument as `Memory Type` to smbios_form_factor_to_spd_mod_type() so that it can internally call convert_form_factor_to_module_type() for `Module Type` conversion. 5. Update `test_smbios_form_factor_to_spd_mod_type()` to accommodate different memory types. 6. Skip fixed module type to form factor conversion using DDR2 SPD4 specification (inside dimm_info_fill()). Refer to datasheet SPD4.1.2.M-1 for LPDDRx and SPD4.1.2.L-3 for DDRx. BUG=b:194659789 TEST=Refer to dmidecode -t 17 output as below: Without this code change: Handle 0x0012, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2048 MB Form Factor: Unknown .... With this code change: Handle 0x0012, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2048 MB Form Factor: Row Of Chips .... Change-Id: Ia337ac8f50b61ae78d86a07c7a86aa9c248bad50 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-10Rename ECAM-specific MMCONF KconfigsShelley Chen
Currently, the MMCONF Kconfigs only support the Enhanced Configuration Access mechanism (ECAM) method for accessing the PCI config address space. Some platforms have a different way of mapping the PCI config space to memory. This patch renames the following configs to make it clear that these configs are ECAM-specific: - NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT - MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT - MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS - MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER - MMCONF_LENGTH --> ECAM_MMCONF_LENGTH Please refer to CB:57861 "Proposed coreboot Changes" for more details. BUG=b:181098581 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max Make sure Jenkins verifies that builds on other boards Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-09pci_mmio_cfg: Always use pci_s_* functionsNico Huber
When MMIO functions are available, the pci_s_* functions do exactly the same thing. Drop the redundant pci_mmio_* versions. Change-Id: I1043cbb9a1823ef94bcbb42169cb7edf282f560b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-11-09pci_mmio_cfg: Gather everything MMCONF (ECAM) relatedNico Huber
To ease code sharing with other MMIO-based configuration mechanisms, move everything MMCONF (more specifically ECAM) related to one spot and guard it. Change-Id: Idda2320c331499dabbee7447f1ad3e81340f2a25 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-11-09pci_mmio_cfg: Move guard around pci_s_* functions to x86Nico Huber
There is no platform in our tree that requires the PCI MMIO ops but doesn't want the pci_s_* definitions. The only case where we include the `pci_mmio_cfg.h` header but don't want the pci_s_* functions to use MMIO is on older x86 platforms, so move the guard there. Change-Id: Iaeed6ab43ad61b7c0e14572b12bf4ec06b6a26af Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-11-04SMBIOS/SCONFIG: Allow devtree-defined Type 41 entriesAngel Pons
Introduce the `smbios_dev_info` devicetree keyword to specify the instance ID and RefDes (Reference Designation) of onboard devices. Example syntax: device pci 1c.0 on # PCIe Port #1 device pci 00.0 on smbios_dev_info 6 end end device pci 1c.1 on # PCIe Port #2 device pci 00.0 on smbios_dev_info 42 "PCIe-PCI Time Machine" end end The `SMBIOS_TYPE41_PROVIDED_BY_DEVTREE` Kconfig option enables using this syntax to control the generated Type 41 entries. When this option is enabled, Type 41 entries are only autogenerated for devices with a defined instance ID. This avoids having to keep track of which instance IDs have been used for every device class. Using `smbios_dev_info` when `SMBIOS_TYPE41_PROVIDED_BY_DEVTREE` is not enabled will result in a build-time error, as the syntax is meaningless in this case. This is done with preprocessor guards around the Type 41 members in `struct device` and the code which uses the guarded members. Although the preprocessor usage isn't particularly elegant, adjusting the devicetree syntax and/or grammar depending on a Kconfig option is probably even worse. Change-Id: Iecca9ada6ee1000674cb5dd7afd5c309d8e1a64b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-11-04device/azalia_device.h: Rewrite verb macrosAngel Pons
Introduce the `AZALIA_VERB_12B` macro to encode HDA commands with 12-bit verb identifiers and rewrite existing helper macros to use it. Tested with BUILD_TIMELESS=1, Purism Librem Mini remains identical. Change-Id: I5b2418f6d2faf6d5ab424949d18784ca6d519799 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-04device/azalia_device.h: Guard macro parametersAngel Pons
Add parentheses around macro parameters to avoid operation order issues. Change-Id: Ic984a82da5eb31fc2921cff3265ac5ea2be098c7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-11-03device/include: Fix potential build errorAlan Huang
Add include guard for usbc_mux.h BUG=none BRANCH=none TEST=Build Pass Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Change-Id: I47988edee84d17f0a15cfda1ac6f0187326bd331 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-02include/device/pci_ids,soc/amd/common/block/lpc: drop duplicate PCI IDsFelix Held
PCI_DEVICE_ID_AMD_FAM17H_LPC and PCI_DEVICE_ID_AMD_FAM17H_SMBUS redefine the same values that are already defined by PCI_DEVICE_ID_AMD_CZ_LPC and PCI_DEVICE_ID_AMD_CZ_SMBUS, so drop PCI_DEVICE_ID_AMD_FAM17H_LPC and PCI_DEVICE_ID_AMD_FAM17H_SMBUS. Also add some comments to the places in the code where the defines are used to clarify which ID is used on which hardware generation. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id0b3d7b5a886ccc76d82ada6be4145e85fd51ede Reviewed-on: https://review.coreboot.org/c/coreboot/+/58696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-26include/device/pci_ids: move AMD device IDs below AMD vendor IDFelix Held
Half of the AMD PCI device ID definitions were below the ATI vendor ID, so move those below the AMD PCI vendor ID definition. The entries are kept in the order they were before and added before the existing AMD device ID definitions below the AMD vendor ID definition. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I34ffdc49884737541b8653bebf023a68050375d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-26include/device/pci_ids: fix typo in PCI_DEVICE_ID_AMD_FE_GATE_700DFelix Held
The definitions isn't used in either spelling. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id6faea2b9c89f0bd3c164a6dc76fac5ea712d313 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-22include/device: ensure valid link/bus is passed to mp_cpu_bus_initFelix Held
When a chipset or mainboard devicetree doesn't have any LAPIC devices in its CPU cluster, not only the LAPIC device, but also the link/bus between the CPU cluster device and the LAPIC devices will be missing and the CPU cluster's dev->link_list will be NULL. This patch handles this case in the common code like commit 3c0ecd57c174b7391c66d22406effe18ce570cac (soc/intel/common/cpu: Handle non-zero BSP APIC ID in init_cpus) and commit ba936ce5db819d5ecb34e83a998b2390ecbdc4b9 (soc/intel/denverton_ns: Ensure CPU device has a valid link) already did in the common Intel SoC and the Denverton code. With this change all CPUs and SoC that use the common mp_cpu_bus_init as init function in the CPU cluster's device operations struct won't require having at least one LAPIC device in the chipset or mainboard device tree. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib0d85de5cafb6390b8fbd512186899d6a815e972 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-06include/device: Generic interface for USB-C mux operationsDerek Huang
Create a generic interface to allow any of the EC or other drivers to provide set of USB-C mux operations. Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com> Change-Id: Ic5435f2054d1c9f114b06c3b4643e34713290e0d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-10-05src/acpi to src/lib: Fix spelling errorsMartin Roth
These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I5b8ecdfe75d99028fee820a2034466a8ad1c5e63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58080 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-29soc/intel/alderlake: Add GFx Device ID 0x46c3Selma Bensaid
This CL adds support for new ADL-M graphics Device ID 0x46c3. TEST=boot to OS Change-Id: Ib55fb501f96fe9bcc328202511bbfe84a3122285 Signed-off-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-24device: Drop unused function `dev_find_matching_device_on_bus`Furquan Shaikh
With use of device pointers, `dev_find_matching_device_on_bus()` is now unused and hence this change drops the function. Change-Id: I30fcb2d9932d770ca614cceffb15646ce8256465 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-20device: Add helper macros for device pointers using alias namesFurquan Shaikh
This change provides helper macros for generating pointer name and weak pointer definition for devices using alias names. This will be helpful for developers to reference the device pointer with alias names used in the device tree. Change-Id: I3a5a3c7fdc2c521bac9ab3336f5a6ebecd621e04 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-20device/mmio: Make buffer_to_fifo32() take a const bufferJulius Werner
The input buffer to the buffer_to_fifo family of functions is only read, so it can be a const pointer. (Also, remove the MIPS check in libpayload for these functions... the MIPS architecture has been removed a while ago.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I021069680cf691590fdacc3d51f747f12ae3df31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-09-06device/device.h: Drop unused function declarationAngel Pons
The `dev_optimize()` function is neither defined nor used anywhere in the tree. Drop its unnecessary declaration. Change-Id: I902bda3244c6496a04f364fad3ecbbdd118dd543 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57398 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-26device/mipi: Move to drivers/mipiJulius Werner
Sounds like we prefer to have this under drivers/ instead of device/. Also move all MIPI-related headers out from device/ into their own directory. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ib3e66954b8f0cf85b28d8d186b09d7846707559d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-08-20soc/intel/adl: Update PCI ID for ADL-M SKUSumeet Pawnikar
Update PCI ID for ADL-M as per document 643775. BUG=None BRANCH=None Change-Id: Ia2c5ce270bc421d8a41cc4bc6ce0b51987d2aaec Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-19soc/intel/common: Add TGL-H PCI IDsJeremy Soller
Add TGL-H PCI IDs from the Processor and PCH EDS docs. Reference: - Intel doc 615985 - Intel doc 575683 Change-Id: I751d0d59aff9e93e2aa92546db78775bd1e6ef22 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-18device: Move MIPI panel library from mainboard/google/kukui into commonJulius Werner
All boards that are trying to use MIPI panels eventually run into the problem that they need to store physical parameters and a list of DCS initialization commands for each panel, and these commands can be very different (e.g. a large amount of very short commands, a few very large commands, etc.). Finding a data format to fit all these different cases efficiently into the same structures keeps being a challenge, and the Kukui mainboard already once put a lot of effort into designing a clean, flexible and efficient solution for this. This patch moves that framework into a common src/device/mipi/ library where it can be used by other boards as well. (Also, this will hopefully allow us to save some duplicated work when using the same panel on different boards at some point.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I877f2b0c7ab984412b288e2ed27f37cd93c70863 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-08-05soc/intel/alderlake: Add GFx Device ID 0x46aaBora Guvendik
This CL adds support for new ADL-M graphics Device ID 0x46aa. TEST=boot to OS Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ib24b494b0eedad447f3b2a3d1d80c9941680c25d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-02helpers: Add GENMASK macroYu-Ping Wu
The GENMASK is defined in multiple files (with various names such as MASKBIT), which sets certain consecutive bits to 1 and leaves the others to 0. To avoid duplicate macros, add GENMASK macro to helpers.h. GENMASK(high, low) sets bits from `high` to `low` (inclusive) to 1. For example, GENMASK(39, 21) gives us the 64-bit vector 0x000000ffffe00000. Remove duplicate macro definitions. Also utilize GENMASK for _BF_MASK in mmio.h. BUG=none TEST=make tests/commonlib/bsd/helpers-test TEST=emerge-cherry coreboot BRANCH=none Change-Id: If2e7c4827d8a7d27688534593b556a72f16f0c2b Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-07-20soc/intel/alderlake: Add support for I2C6 and I2C7Varshit B Pandya
As per the EDS revision 1.3 add support for I2C6 and I2C7. Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: Id918d55e48b91993af9de8381995917aef55edc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55996 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-17soc/amd/common/block/graphics: add GPU PCI ID for BarceloFelix Held
Also rename the existing PCI_DEVICE_ID_ATI_FAM19H_MODEL51H_GPU definition to PCI_DEVICE_ID_ATI_FAM19H_MODEL51H_GPU_CEZANNE to clarify that that is the one for Cezanne. BUG=b:193888172 Change-Id: I1c5446c1517f2e0cd708d3275b08d2bce4be0ea8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56396 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14src/device: Remove DEVICE_PATH_ESPI & DEVICE_PATH_LPCMartin Roth
The ESPI & LPC keywords were added for the zork program, but it was found that they weren't needed, so they were never used. The previous patch removes them from sconfig, so now they aren't needed in coreboot. BUG=None TEST=Build Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I9ae7817bb63d69ee272103b2d1186f125e188950 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56278 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/intel/alderlake: Add GFx Device ID 0x46a6Maulik V Vaghela
This CL adds support for new ADL graphics Device ID 0x46a6. TEST=Build and boot Adlrvp board Change-Id: I8ca875c7faf2997d207aff9e292f94a3b6311e94 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56026 Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-01device: Clean up resource utility function signaturesKyösti Mälkki
Drop extern declarations from functions. Declare resource arguments as const. Change-Id: I7684cc7813bad805c39a762892636818279ac134 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55475 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-21soc/intel/alderlake: Add GFx Device ID 0x46b3Meera Ravindranath
List of changes: 1. Add new GFx ID 0x46B3 into device/pci_ids.h 2. Update new GFx ID into common graphics.c 3. Add new GFx ID description into report_platform.c TEST=Build and boot brya Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I4343c7343875eb40c2955f6f4dd98d6446852dc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-06-21include/pci_def.h: Add some PCI Power Management CSR bitsTim Wawrzynczak
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I84c8470764a4e6e09220044966111ffe72078099 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55674 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-17device: Add helper function devfn_disable()Subrata Banik
devfn_disable() function is used to disable a device based on given bus, device function number. This function checks if the device is at enable state and disables the device. Change-Id: Ia4a8bfec7fc95c729a5bb156f88e9aab3bf5dd41 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-10device/pnp: Always provide `pnp_unset_and_set_config`Angel Pons
The `pnp_unset_and_set_config` function was only available when building with `ENV_PNP_SIMPLE_DEVICE` set. Add the complementary definition using device pointers, for the sake of completeness. Change-Id: I2a21e635f41f3f786057500fa96a2b3116e30d76 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Máté Kukri <kukri.mate@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-06-09device/dram: Add LPDDR4 utilitiesRob Barnes
Add lpddr4.c utility file with lpddr4_speed_mhz_to_reported_mts. Fill in lpddr4_speeds using JDEC 209-4C table 210. LPDDR4 SPD decoding utilities are not included since there isn't a present need. BUG=b:184124605 TEST=Build and run on guybrush Change-Id: Id8ddfc98fff4255670c50e1ddd4d0a1326265772 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-09device: Add helper function is_devfn_enabled()Subrata Banik
is_devfn_enabled() function helps to check if a device is enabled based on given device function number. This function internally called is_dev_enabled() to check device state. Change-Id: I6aeba0da05b13b70155a991f69a6abf7eb48a78c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-08soc/intel: Add Alder Lake's GT device IDSridhar Siricilla
Add Alder Lake specific graphics device ID. The document# 641765 lists the id 0x46a8. TEST=Verify boot on brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I6f36256505a3e07c6197079ea2013991e841401b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55256 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-26soc/intel/elkhartlake: Update SA & IGD DIDs TableTan, Lean Sheng
Update SA & IGD DIDs table as per latest EDS (Doc no: 601458). Add extra SKUs and fix the mismatched SKU numbers accordingly. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I62fd9e6a7cf0fc6f541f3d6d9edd31d41db7279f Reviewed-on: https://review.coreboot.org/c/coreboot/+/54863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-05-24device: Consider fw_config probing in `is_dev_enabled()`Furquan Shaikh
With the introduction of fw_config support in coreboot, it is possible for mainboards to control the state of a device (on/off) in ramstage using fw_config probe conditions. However, the device tree in immutable in all other stages and hence `is_dev_enabled()` does not really reflect the true state as in ramstage. This change adds a call to `fw_config_probe_dev()` in `is_dev_enabled()` when device tree is immutable (by checking DEVTREE_EARLY) to first check if device is disabled because of device probe conditions. If so, then it reports device as being disabled. Else, dev->enabled is used to report the device state. This allows early stages (bootblock, romstage) to use `is_dev_enabled()` to get the true state of the device by taking probe conditions into account and eliminates the need for each caller to perform their own separate probing. Change-Id: Ifede6775bda245cba199d3419aebd782dc690f2c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54752 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-21soc/intel/common: Add Alder Lake device IDsSumeet R Pawnikar
Add Alder Lake specific Host and Graphics device IDs. As per latest document number: 619501, these IDs got an update. Change-Id: I548a903714ccc7470f1425ac67c0c66522437365 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54674 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-14soc/intel/alderlake: Update CPU and IGD Device IDsMaulik V Vaghela
Updated CPU ID and IGD ID for Alder Lake as per EDS. TEST=Code compilation works and coreboot is able to boot and identify new device Ids. Change-Id: I2759a41a0db1eba5d159edfc89460992914fcc3c Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-10device: Drop unused `uma_memory_{base,size}` globalsAngel Pons
These global variables are not used anywhere. Drop them. Change-Id: I3fe60b970153d913ae7b005257e2b53647d6f343 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53977 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-03device: Switch pci_dev_is_wake_source to take pci_devfn_tTim Wawrzynczak
With the recent switch to SMM module loader v2, the size of the SMM for module google/volteer increased to above 64K in size, and thus failed to install the permanent SMM handler. Turns out, the devicetree is all pulled into the SMM build because of elog, which calls `pci_dev_is_wake_source`, and is the only user of `struct device` in SMM. Changing this function to take a pci_devfn_t instead allows the linker to remove almost the entire devicetree from SMM (only usage left is when disabling HECI via SMM). BUG=b:186661594 TEST=Verify loaded program size of `smm.elf` for google/volteer is almost ~50% smaller. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I4c39e5188321c8711d6479b15065e5aaedad8f38 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-28soc/intel: Add Z370, H310C and B365 device IDsAngel Pons
Intel document 335192-004 contains the PCI device IDs for Z370 and H310C, but lacks the ID for B365. The ID appears on some websites: https://linux-hardware.org/index.php?id=pci:8086-a2cc-1849-a2cc Change-Id: Iea3c435713c46854c5271fbc266f47ba4573db52 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52703 Reviewed-by: Timofey Komarov <happycorsair@yandex.ru> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28soc/intel: Add Kaby Lake PCH-U base device IDAngel Pons
Taken from Intel document 334658-003 (7th Generation Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel Processor Family I/O for U Quad Core Platforms, Datasheet - Volume 1 of 2). Change-Id: I1d48c8868e1e5d453d599ecec835938ce09935d0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52702 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Timofey Komarov <happycorsair@yandex.ru> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28soc/intel: Rename 200-series PCH device IDsAngel Pons
The code name for these PCHs is Union Point, abbreviated as `UPT`. There are some 300-series Union Point PCHs (H310C, B365, Z370) which are meant to be paired with Coffee Lake CPUs instead of Skylake or Kaby Lake CPUs, and referring to them as `KBP` (Kaby Point, I guess) would be confusing. Tested with BUILD_TIMELESS=1, HP 280 G2 remains identical. Change-Id: I1a49115ae7ac37e76ce8d440910fb59926f34fac Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52700 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Timofey Komarov <happycorsair@yandex.ru> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06soc/intel/alderlake: Add LPC and IGD device Ids for Alderlake MMaulik V Vaghela
Added new LPC and IGD device IDs for Alderlake M. Also, added entry for CPUID_ALDERLAKE_M_A0 in report_platform.c TEST=Check if platform information print is coming properly in coreboot Change-Id: If33c43da8cbd786261b00742e342f0f01622c607 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50138 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05device/dram/ddr3: Drop unused MRS helpersAngel Pons
These aren't used anywhere anymore. Change-Id: I4cf2fc0d07a772886e90fba4f66591a7b0a40e6c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-05device/dram/ddr4.h: Align with DDR3 and DDR2Angel Pons
Drop unnecessary typedefs and rename DDR4-specific definitions to avoid name clashes, as done for DDR3 in earlier commits. This allows including and using both DDR3 and DDR4 headers in the same compilation unit. Change-Id: I17f1cd88f83251ec23e9783a617f4d2ed41b07f0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51898 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05device/dram/ddr3: Rename DDR3 SPD memory typesAngel Pons
To avoid name clashes with definitions for other DRAM generations, rename the enum type and values to contain `ddr3` or `DDR3`. Change-Id: If3710149ba94b94ed14f03e32f5e1533b4bc25c8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51896 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05device/dram/ddr3: Get rid of useless typedefsAngel Pons
These typedefs are not necessary. Remove them, and rename some elements to avoid any confusion with other DRAM generations, such as DDR4. Change-Id: Ibe40f33372358262c540e371f7866b06a4ac842a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51895 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15pciexp_device: Rewrite LTR configurationNico Huber
I was bugged by spurious "Failed to enable LTR" messages for years. Looking at the the current algorithm, it is flawed in multiple ways: * It looks like the author didn't know they implemented a recursive algorithm (pciexp_enable_ltr()) inside another recursive algorithm (pciexp_scan_bridge()). Thus, at every tree level, everything is run again for the whole sub- tree. * LTR is enabled no matter if `.set_ltr_max_latencies` is implemented or not. Leaving the endpoints' LTR settings at 0: They are told to always report zero tolerance. In theory, depending on the root-complex implementation, this may result in higher power consumption than without LTR messages. * `.set_ltr_max_latencies` is only considered for the direct parent of a device. Thus, even with it implemented, an endpoint below a (non-root) bridge may suffer from the 0 settings as described above. * Due to the double-recursive nature, LTR is enabled starting with the endpoints, then moving up the tree, while the PCIe spec tells us to do it in the exact opposite order. With the current implementation of pciexp_scan_bridge(), it is hard to hook anything in that runs for each device from top to bottom. So the proposed solution still adds some redundancy: First, for every device that uses pciexp_scan_bus(), we enable LTR if possible (see below). Then, when returning from the bus- scanning recursion, we enable LTR for every device and configure the maximum latencies (if supported). The latter runs again on all bridges, because it's hard to know if pciexp_scan_bus() was used for them. When to enable LTR: * For all devices that implement `.set_ltr_max_latencies`. * For all devices below a bridge that has it enabled already. Change-Id: I2c5b8658f1fc8cec15e8b0824464c6fc9bee7e0e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51328 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-14device/pciexp_device.c: Remove CPP guardingArthur Heymans
Let the linker do its job. This fixes building with !CONFIG_PCIEXP_HOTPLUG on some platforms. Change-Id: I46560722dcb5f1d902709e40b714ef092515b164 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-12pci_def.h: Introduce PCI_EXP_DEVCAP2 & PCI_EXP_DEVCTL2 properNico Huber
Replace the existing, odd looking, unordered definitions used for LTR configuration with the usual names used by upstream libpci. TEST=Built google/brya0 with BUILD_TIMELESS=1: no changes. Fixes: Code looked like UEFI copy-pasta. Header file was a mess. Change-Id: Icf666692e22730e1bdf4bcdada433b3219af568a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51327 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-12device: Give `pci_ops.set_L1_ss_latency` a proper nameNico Huber
Rename `set_L1_ss_latency` to what it does: `set_ltr_max_latencies`. TEST=Built google/brya0 with BUILD_TIMELESS=1: no changes. Change-Id: I7008aa18bf80d6709dce1b2d3bfbb5ea407a0574 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51326 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-12soc/intel/*: drop UART pad configuration from common codeMichael Niewöhner
UART pad configuration should not be done in common code, because that may cause short circuits, when the user sets a wrong UART index. Since all boards do pad setup on their own now, finally drop the pad configuration from SoC common code. Change-Id: Id03719eb8bd0414083148471ed05dea62a895126 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao
2021-03-11soc/intel/common/block: Add PCI IDs for EmmitsBurg PCHJonathan Zhang
According to Intel EmmitsBurg EDS, doc# 606161: * Add PCI devid for SPI. * Add PCI devid for ESPI (LPC). EmmitsBurg (EBG) PCH is used in the chipset with Sapphire Rapids Scalable Processor (SPR-SP). Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ie8925cb739c95c34febf9002149de437d19c8234 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-05soc/intel/broadwell/pch: Use Lynx Point smbus.cAngel Pons
Continue unifying Lynx Point and Wildcat Point (PCH for Broadwell) code. Define the WPT-LP SMBus PCI device ID, add it to smbus.c of Lynx Point, and drop all now-unnecessary SMBus code from Broadwell. Change-Id: I864d7c2dd47895a3c559e2f1219425cda9fd0c17 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-27drivers/soundwire/alc1308 : Add ALC1308 soundwire deviceAnil Kumar
This patch adds new soundwire device ALC1308 The codec properties are filled out as best as possible with the datasheet as a reference. The ACPI address for the codec is calculated with the information in the codec driver combined with the devicetree.cb hierarchy where the link and unique IDs are extracted from the device path. The unique ID is calculated from schematics by referring to ASEL[1:0] strap settings. Datasheet of ALC1308 provides info about the mapping of ASEL strap settings to unique ID For example this device is connected to master link ID 1 and has strap settings configuring it for unique ID 2. chip drivers/soundwire/alc1308 register "desc" = ""Left Speaker"" device generic 1.2 on end end Bug=None Test=Build and boot on TGLRVP.Extract SSDT and confirm that the entries for PCI0.HDAS.SNDW are present for ALC1308 Test speaker out functionality Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: Ibf3f1d5c6881cbd106e96ad1ff17ca216aa272ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/51042 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Sathyanarayana Nujella Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-27sb/intel/ibexpeak: Add all PCI IDs for LPCAngel Pons
Taken from document 322170-028 (5 series specification update). Tested on out-of-tree HP ProBook 6550b (HM57), fixes several issues. Without this patch, EHCI controllers had no IRQ assigned and there were unexpected exceptions about NMIs. With this patch, the issues are gone. Change-Id: Icd31dd89ba49e38a5e4c108a8361dbf636332ab8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51066 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24soc/amd/picasso/data_fabric: add missing data fabric device function 7Felix Held
The device function is missing in the PCI device table in the PPR, but is present in the hardware. Verified on a Mandolin board with PCO APU. The corresponding ticket for the PPR is DESPCSOC-6667. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie91438bc905691d443ca4e7841549d1e3bca39ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/51041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-24device/device.c: Rename .disable to .vga_disableArthur Heymans
This makes it clear what this function pointer is used for. Change-Id: I2090e164edee513e05a9409d6c7d18c2cdeb8662 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51009 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-16device/dram: Move SPD manufacturer names out of arch/x86Patrick Rudolph
Move SPD manufacturer ID decoding to device/dram. Will be used by the following patch outside of SMBIOS scope as well. Change-Id: Iec175cd6ab1d20761da955785e4bc0e87ae02dbb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-10device/azalia_device: Add mainboard hook to program codecsAngel Pons
On some mainboards, codec configuration depends on settings that are only known at runtime, which is impossible to specify using one verb table. Add an optional `mainboard_azalia_program_runtime_verbs` hook where mainboards can program runtime-dependent codec verbs. Change-Id: I7efeba5c26051aeb5061cce191ace08c304a6c70 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-10device/azalia_device: Add function to program a verb tableAngel Pons
On some boards, Azalia configuration depends on config settings that are not known at compile-time. Expose a function to program a verb table, to be used in subsequent commits. Change-Id: Ie9607f6e733df66f0ca26a4bb70e0864ce1d4512 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-04drivers/generic/bayhub_lv2: Add driver for BayHub lv2John Su
Add a driver which puts the device into power-saving mode. BUG=b:177955523 BRANCH=zork TEST=boot and see this message: BayHub LV2: Power-saving enabled 110102 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Idc1340b1a6fe7063d16c8ea16488d6e2b8b308cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/49783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-03pci_ids/intel: Add missing CFL-S GT1 IGD IDsNico Huber
Change-Id: I372b6b2d602dfe116d5791bb6a6653454523b42b Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Timofey Komarov <happycorsair@yandex.ru>
2021-02-03pci_ids/intel: Correct 0x3e96, it's a CFL-S partNico Huber
Change-Id: Ibdddb3309f862f52c578e91ba3dc310dff8f70bc Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Timofey Komarov <happycorsair@yandex.ru> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-14 02:57:27 +0000