diff options
| author | Usha P <usha.p@intel.com> | 2022-01-17 20:06:38 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-25 16:10:46 +0000 |
| commit | 8f2df280e19f34a1c97adc29acee21a783e1e388 (patch) | |
| tree | 7fad3108749dbe6881a9f098b508cada02c144c9 /src/include/device | |
| parent | 7760fe4645c55c2025a4fc9de0b205b8fd7031d3 (diff) | |
soc/intel/common: Include Alder Lake-N device IDs
Add Alder Lake-N System Agent, PCIE, UFS, IPU and CNVI device IDs.
Document: Alder Lake N Platform EDS Volume 1 (Doc# 645548)
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I0a383816f818b794cf1211766c27937b3b8daa31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Diffstat (limited to 'src/include/device')
| -rw-r--r-- | src/include/device/pci_ids.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 30012d94c2..22962c3885 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3407,6 +3407,8 @@ #define PCI_DEVICE_ID_INTEL_ADP_M_PCIE_RP8 0x54bf #define PCI_DEVICE_ID_INTEL_ADP_M_PCIE_RP9 0x54b0 #define PCI_DEVICE_ID_INTEL_ADP_M_PCIE_RP10 0x54b1 +#define PCI_DEVICE_ID_INTEL_ADP_N_PCIE_RP11 0x54b2 +#define PCI_DEVICE_ID_INTEL_ADP_N_PCIE_RP12 0x54b3 /* Intel SATA device Ids */ #define PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_IDE 0x8c00 @@ -4022,6 +4024,8 @@ #define PCI_DEVICE_ID_INTEL_ADL_M_ID_2 0x460a #define PCI_DEVICE_ID_INTEL_ADL_N_ID_1 0x4617 #define PCI_DEVICE_ID_INTEL_ADL_N_ID_2 0x461B +#define PCI_DEVICE_ID_INTEL_ADL_N_ID_3 0x461c +#define PCI_DEVICE_ID_INTEL_ADL_N_ID_4 0x4614 /* Intel SMBUS device Ids */ #define PCI_DEVICE_ID_INTEL_LPT_H_SMBUS 0x8c22 @@ -4229,6 +4233,9 @@ #define PCI_DEVICE_ID_INTEL_JSP_EMMC 0x4dc4 #define PCI_DEVICE_ID_INTEL_ADP_EMMC 0x54c4 +/* Intel UFS device Ids */ +#define PCI_DEVICE_ID_INTEL_ADP_UFS 0x54ff + /* Intel Thunderbolt device Ids */ #define PCI_DEVICE_ID_INTEL_TGL_TBT_RP0 0x9a23 #define PCI_DEVICE_ID_INTEL_TGL_TBT_RP1 0x9a25 @@ -4285,6 +4292,7 @@ #define PCI_DEVICE_ID_INTEL_TGL_H_IPU 0x9a39 #define PCI_DEVICE_ID_INTEL_JSL_IPU 0x4e19 #define PCI_DEVICE_ID_INTEL_ADL_IPU 0x465d +#define PCI_DEVICE_ID_INTEL_ADL_N_IPU 0x462e /* Intel Dynamic Tuning Technology Device */ #define PCI_DEVICE_ID_INTEL_CML_DTT 0x1903 @@ -4318,6 +4326,10 @@ #define PCI_DEVICE_ID_INTEL_TGL_H_CNVI_BT_0 0x43f5 #define PCI_DEVICE_ID_INTEL_TGL_H_CNVI_BT_1 0x43f6 #define PCI_DEVICE_ID_INTEL_TGL_H_CNVI_BT_2 0x43f7 +#define PCI_DEVICE_ID_INTEL_ADL_N_CNVI_WIFI_0 0x54f0 +#define PCI_DEVICE_ID_INTEL_ADL_N_CNVI_WIFI_1 0x54f1 +#define PCI_DEVICE_ID_INTEL_ADL_N_CNVI_WIFI_2 0x54f2 +#define PCI_DEVICE_ID_INTEL_ADL_N_CNVI_WIFI_3 0x54f3 #define PCI_VENDOR_ID_COMPUTONE 0x8e0e #define PCI_DEVICE_ID_COMPUTONE_IP2EX 0x0291 |