coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2019-08-07	intel/nehalem,sandybridge: Move stage_cache support function	Kyösti Mälkki
2019-07-09	arch/x86: Avoid HAVE_SMI_HANDLER conditional with smm-class	Kyösti Mälkki
2019-07-01	Use 3rdparty/intel-microcode	Arthur Heymans
2019-05-27	cpu/intel/model_2065x: Put stage cache in TSEG	Arthur Heymans
2019-02-25	security/vboot: Add measured boot mode	Philipp Deppenwiese
2018-06-05	cpu/intel/model_2065x: Switch to POSTCAR_STAGE	Arthur Heymans
2018-06-05	cpu/intel/car/non-evict: Prepare for some POSTCAR_STAGE support	Arthur Heymans
2016-12-27	cpu/intel/common: Add/Use common function to set virtualization	Matt DeVillier
2016-06-22	intel/model_2065x: Prepare for dynamic CONFIG_RAMTOP	Kyösti Mälkki
2015-09-30	cpu: microcode: Use microcode stored in binary format	Alexandru Gagniuc
2015-09-04	x86: remove cpu_incs as romstage Make variable	Aaron Durbin
2015-06-10	model_2065x: Use common i945-ivy TSEG SMM init.	Vladimir Serbinenko
2015-05-28	Migrate 2065x to SMM_MODULES	Vladimir Serbinenko
2014-10-16	ACPI: Remove CONFIG_GENERATE_ACPI_TABLES	Vladimir Serbinenko
2013-11-13	intel/2065x: Use TSC for udelay()	Vladimir Serbinenko
2013-06-13	Add support for Intel Nehalem CPU	Vladimir Serbinenko