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authorVladimir Serbinenko <phcoder@gmail.com>2013-06-06 22:10:45 +0200
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-06-13 00:32:01 +0200
commit22dcdd914cf36ce657f5e72c975a96d577400a69 (patch)
tree6d356f4a0a3a7dbb09b5e3b91f4b19a79867841a /src/cpu/intel/model_2065x/Makefile.inc
parent3a09179f462ad3f6111c7b8ebbad7d78534f9234 (diff)
Add support for Intel Nehalem CPU
Change-Id: I7ecc394b1e5bc0b8b85a8afac22efc0befe2d36a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3395 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/intel/model_2065x/Makefile.inc')
-rw-r--r--src/cpu/intel/model_2065x/Makefile.inc16
1 files changed, 16 insertions, 0 deletions
diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc
new file mode 100644
index 0000000000..963fb1b3e3
--- /dev/null
+++ b/src/cpu/intel/model_2065x/Makefile.inc
@@ -0,0 +1,16 @@
+ramstage-y += model_2065x_init.c
+subdirs-y += ../../x86/name
+subdirs-y += ../../x86/cache
+subdirs-y += ../../x86/mtrr
+subdirs-y += ../../x86/lapic
+subdirs-y += ../../intel/turbo
+subdirs-y += ../../intel/microcode
+subdirs-y += ../../x86/smm
+
+ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
+
+cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+
+cpu_incs += $(src)/cpu/intel/model_2065x/cache_as_ram.inc