From 22dcdd914cf36ce657f5e72c975a96d577400a69 Mon Sep 17 00:00:00 2001 From: Vladimir Serbinenko Date: Thu, 6 Jun 2013 22:10:45 +0200 Subject: Add support for Intel Nehalem CPU Change-Id: I7ecc394b1e5bc0b8b85a8afac22efc0befe2d36a Signed-off-by: Vladimir Serbinenko Signed-off-by: Stefan Reinauer Reviewed-on: http://review.coreboot.org/3395 Reviewed-by: Alexandru Gagniuc Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/cpu/intel/model_2065x/Makefile.inc | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 src/cpu/intel/model_2065x/Makefile.inc (limited to 'src/cpu/intel/model_2065x/Makefile.inc') diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc new file mode 100644 index 0000000000..963fb1b3e3 --- /dev/null +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -0,0 +1,16 @@ +ramstage-y += model_2065x_init.c +subdirs-y += ../../x86/name +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/lapic +subdirs-y += ../../intel/turbo +subdirs-y += ../../intel/microcode +subdirs-y += ../../x86/smm + +ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c + +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c + +cpu_incs += $(src)/cpu/intel/model_2065x/cache_as_ram.inc -- cgit v1.2.3