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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-06-17 10:00:28 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-06-22 10:49:18 +0200
commit8431fcb8c8e248d777723e0a6651b9030d29cf8e (patch)
treec9b06b7c67c8f6fa54d5ae03c59887ada4f0c690 /src/cpu/intel/model_2065x/Makefile.inc
parentb4f827d45a08d849df9d15abd644e3a98a6f1932 (diff)
intel/model_2065x: Prepare for dynamic CONFIG_RAMTOP
Change-Id: I616143b55d7c5726dc2475434e3fcb08b8d69bda Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15230 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/intel/model_2065x/Makefile.inc')
-rw-r--r--src/cpu/intel/model_2065x/Makefile.inc1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc
index a13f5df26d..cdf9fed3e2 100644
--- a/src/cpu/intel/model_2065x/Makefile.inc
+++ b/src/cpu/intel/model_2065x/Makefile.inc
@@ -20,3 +20,4 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_2065x/microcode.bin
cpu_incs-y += $(src)/cpu/intel/model_2065x/cache_as_ram.inc
+romstage-y += ../car/romstage.c