diff options
| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2023-09-01 07:54:20 +0200 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2023-09-02 16:25:30 +0000 |
| commit | a52d38b637d08334cd5cf4e11750f2cf9d3dd849 (patch) | |
| tree | e354a16030fc0cdfcd54d6543b74cd3f1589e2e9 /src/mainboard/siemens/mc_apl1 | |
| parent | fd6908a748ad00aa6557e08309b9aad9abcdceb2 (diff) | |
mb/siemens/mc_apl2: Set Full Reset Bit into Reset Control Register
With the introduction of a new Linux version a problem has appeared
after a software initiated reset via CF9h register. The problem
manifests itself in the fact that the Linux kernel does not start after
the reboot. The problem is solved by setting bit 3 to 1 in Reset Control
Register (I/O port CF9h). This leads to the fact that the PCH will drive
SLP_S3 active low in the reset sequence. It leads to the same behavior
as in commit 04ea73ee78bc ("siemens/mc_apl3: Set Full Reset Bit into
Reset Control Register") explained.
Change-Id: Ibc6d538c939e38732f42995d5ec6c8b61f979a6a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77603
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/siemens/mc_apl1')
| -rw-r--r-- | src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c index 430e67e171..af9e25dc06 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <cf9_reset.h> #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> @@ -17,4 +18,9 @@ void variant_mainboard_final(void) pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); } } + + /* Set Full Reset Bit in Reset Control Register (I/O port CF9h). When Bit 3 is set to 1 + and then a warm reset is triggered the PCH will drive SLP_S3 active (low). SLP_S3 is + then used on the mainboard to generate the right reset timing. */ + outb(FULL_RST, RST_CNT); } |