diff options
| -rw-r--r-- | src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c index 430e67e171..af9e25dc06 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <cf9_reset.h> #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> @@ -17,4 +18,9 @@ void variant_mainboard_final(void) pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); } } + + /* Set Full Reset Bit in Reset Control Register (I/O port CF9h). When Bit 3 is set to 1 + and then a warm reset is triggered the PCH will drive SLP_S3 active (low). SLP_S3 is + then used on the mainboard to generate the right reset timing. */ + outb(FULL_RST, RST_CNT); } |