From a52d38b637d08334cd5cf4e11750f2cf9d3dd849 Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Fri, 1 Sep 2023 07:54:20 +0200 Subject: mb/siemens/mc_apl2: Set Full Reset Bit into Reset Control Register With the introduction of a new Linux version a problem has appeared after a software initiated reset via CF9h register. The problem manifests itself in the fact that the Linux kernel does not start after the reboot. The problem is solved by setting bit 3 to 1 in Reset Control Register (I/O port CF9h). This leads to the fact that the PCH will drive SLP_S3 active low in the reset sequence. It leads to the same behavior as in commit 04ea73ee78bc ("siemens/mc_apl3: Set Full Reset Bit into Reset Control Register") explained. Change-Id: Ibc6d538c939e38732f42995d5ec6c8b61f979a6a Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/77603 Reviewed-by: Werner Zeh Reviewed-by: Jan Samek Tested-by: build bot (Jenkins) --- src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/mainboard/siemens/mc_apl1') diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c index 430e67e171..af9e25dc06 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -17,4 +18,9 @@ void variant_mainboard_final(void) pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); } } + + /* Set Full Reset Bit in Reset Control Register (I/O port CF9h). When Bit 3 is set to 1 + and then a warm reset is triggered the PCH will drive SLP_S3 active (low). SLP_S3 is + then used on the mainboard to generate the right reset timing. */ + outb(FULL_RST, RST_CNT); } -- cgit v1.2.3