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2024-05-09arch/arm64/Makefile.mk: Switch linker to GNU GCCYidi Lin
TF-A migrates the default choice of linker to GCC in order to enable LTO. Change BL31_LDFLAGS from `--emit-relocs` to '-Wl,--emit-relocs', so that GCC is able to pass `--emit-relocs` to the linker. [1]: https://review.trustedfirmware.org/c/26703 BUG=b:338420310 TEST=emerge-geralt coreboot TEST=./util/abuild/abuild -t google/geralt -b geralt -a TEST=./util/abuild/abuild -t google/oak -b elm -a Change-Id: I65b96aaa052138592a0f57230e1140a1bb2f07ac Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82189 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-09mb/google/brox: Sending End of Post (EOP) asynchronouslyKarthikeyan Ramasubramanian
Currently EOP message is sent to CSE late in the boot flow. Instead send it asynchronously to save ~10 ms in boot time. BUG=b:337330958 TEST=Build Brox BIOS Image and boot to OS. Change-Id: I229d16a5dcd072958db3f59a9c364bf7508b3047 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-09arch/arm64/Makefile.mk: Unset toolchain vars for BL31Yidi Lin
This change is for upcoming arm-trusted uprev commit. TF-A refactors the toolchain detection in [1][2]. After that `AR`, `CC`, `LD` and other toolchain variables have precedence over `CROSS_COMPILE`. Since ChromeOS build system also sets those toolchain variables when building coreboot, it results that TF-A uses CrOS GCC instead of coreboot SDK. It needs to unset those variables in order to make `CROSS_COMPILE` effective. TF-A upstream changes the default linker from BFD to GCC in [3]. Therefore, temporarily overriding LD as $(LD_arm64} to fix the below build error. aarch64-elf-gcc: error: unrecognized command-line option '--emit-relocs' In addition, TF-A wrapped LD with single quotes to solve Windows path issue[4]. On MT8173 platform, `--fix-cortex-a53-843419` is appended to $(LD_arm64} for ERRATA_A53_843419. It results in the below build error. /bin/sh: 1: --fix-cortex-a53-843419: not found Since `--fix-cortex-a53-843419` is never passed to TF-A, simply extract the LD command from $(LD_arm64) by $(word 1, $(LD_arm64)). [1]: https://review.trustedfirmware.org/c/24921 [2]: https://review.trustedfirmware.org/c/25333 [3]: https://review.trustedfirmware.org/c/26703 [4]: https://review.trustedfirmware.org/c/26737 BUG=b:338420310 TEST=emerge-geralt coreboot TEST=./util/abuild/abuild -t google/geralt -b geralt -a -x TEST=./util/abuild/abuild -t google/oak -b elm -a -x TEST=./util/abuild/abuild -t google/cherry -x -a Change-Id: Ieac9f96e81e574b87e20cd2df335c36abcb8bb5c Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-09soc/mediatek/mt8188: devapc: set devapc permission for MFGFei Yan
In order to support SVP Feature, EMI-MPU has to give MFG permissions to allow MFG to access secure buffer by secure read and write. Currently MFG is in domain 0, which include many other masters. Move MFG to domain 6. Set MFG remap, so that MFG can switch to protect mode by MFG register. Change MFG permission from NO_PROTECTION to SEC_RW_ONLY for domain 0, so that only AP in secure mode can access MFG_S_S-2 and MFG_S_S-5. BUG=b:313855815 TEST=emerge-geralt coreboot Change-Id: Ic6fb7d85bf9d4d92946a045a274b274abc440e1d Signed-off-by: Fei Yan <fei.yan@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-08mb/google/brox: Fix the pad reset config for WLAN Wake interruptKarthikeyan Ramasubramanian
Update the pad reset config for WLAN Interrupt from PLTRST to DEEP so that it can still act as a wake source during S3 suspend. BUG=b:336398012 TEST=Build Brox BIOS image and boot to OS. Suspend to S0ix & S3 and wakeup successfully using Wake on WLAN. 268 | 2024-05-07 13:56:44-0700 | S0ix Enter 269 | 2024-05-07 13:57:07-0700 | S0ix Exit 270 | 2024-05-07 13:57:07-0700 | Wake Source | GPE # | 3 271 | 2024-05-07 13:59:01-0700 | ACPI Enter | S3 273 | 2024-05-07 13:59:26-0700 | Wake Source | PME - WIFI | 0 274 | 2024-05-07 13:59:26-0700 | ACPI Wake | S3 275 | 2024-05-07 13:59:26-0700 | Wake Source | GPE # | 3 Change-Id: Ie0d6e6c8fefdd081e252ea99d6e3c559a5330b0e Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82234 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-08mb/google/brox/var/brox: increase PsysPmax from 21.5W to 208WLawrence Chang
According to Brox HW design, the PsysPmax is supposed to be 208W. This patch changes PsysPmax setting from 21.5W to 208W. Change-Id: I43f4b00a54dc0dfe6bd690492f9ef92698c9b903 Signed-off-by: Lawrence Chang <lawrence.chang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Shelley Chen <shchen@google.com>
2024-05-08soc/intel/xeon_sp/spr: Refine return value checksShuo Liu
mp_init_with_smm returns cb_err type, where 0 means success and negative values represent error (see cb_err.h). However, failure checks in form of "ret < 0" is not straightforward. Use "ret != CB_SUCCESS" instead. Change-Id: I7e57f2da0361f3109051e9a35b1cce81d559b261 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-05-08mb/asrock/z97_extreme6: Add new mainboardAngel Pons
That's an ATX mainboard with a LGA1150 socket and four DDR3 DIMM slots. Porting was done using autoport and then doing a bunch of manual edits. This board has two socketed DIP-8 SPI flash chips and a physical switch to choose which one should the system boot from. As long as one of them contains a bootable firmware image, it is possible to reflash the other chip using the internal programmer by flipping the switch after booting to OS. Even if one somehow manages to flash unbootable firmware to both chips, they are socketed: one can carefully remove them from the socket and reflash them externally, which is a relatively safe procedure (when compared to in-circuit flashing, especially if the board isn't designed to safely be flashed in-circuit). In short, the board is hard to brick. Haswell MRC.bin cannot be used because it lacks support for the Z97 PCH found on this mainboard. Broadwell MRC.bin only works with Haswell CPUs so far, as raminit fails on Broadwell CPUs for an unknown reason. Maybe it's something about RcvEn, but it's unlikely it can easily be fixed. Working: - All four DIMM slots - Broadwell MRC.bin for raminit purposes - Serial port to emit spam - POST code display - S3 suspend/resume - All rear USB 3.0 ports - Internal USB 2.0 port - Audio output (green jack) - Integrated graphics (libgfxinit) - HDMI - VBT - Intel GbE (I218-V PHY and PCH MAC) - Realtek RTL8111E GbE - At least one SATA port - M2_1 slot (Gen3 x4, bifurcated from CPU) - Flashing internally with flashrom - SeaBIOS (current version) to boot Arch Linux - NCT6791D Super I/O software-based fan control tested using `sensors` and `pwmconfig`, all 6 fan tachometers and 5 PWM outputs work fine. Untested for now (i.e. should work, will eventually test): - DVI-I, DisplayPort - EHCI debug - Front USB 2.0 and 3.0 ports - The other audio jacks (as well as SPDIF) - The other PCIe and M.2 ports - Non-Linux OSes - PS/2 combo port (can only test with a keyboard) Untestable (i.e. cannot test due to unavailable hardware): - Thunderbolt AIC (Add-In Card) support Not working: - Broadwell CPUs, they require more magic to work (working on it). - Booting from ASM1062 SATA ports with SeaBIOS. Other payloads were not tested. It seems that the problem is with the controllers. - Super I/O automatic fan control: not yet implemented in coreboot. To control fans, use software fan control methods in the meantime. - Acer B247Y board driving a FHD panel of a Samsung S24E650 monitor, connected to the board's HDMI output says "Unsupported resolution" after libgfxinit configured the iGPU outputs in linear framebuffer mode. HDMI output works fine after Linux's i915 driver takes over. Not sure if it's specific to the monitor: the HDMI cable is beaten up, and it is hard to replace (need to relocate the logic board so that the ports are accessible). Change-Id: If1d22547725e59f435de36b973e1bf4f334269a9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Máté Kukri <kukri.mate@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-05-08commonlib/timestamp_serialized: Define VB_AUXFW_SYNC_DONE timestampKarthikeyan Ramasubramanian
Define a new timestamp to identify the completion of Auxiliary Firmware Sync. Without that, it gets accounted into a different timestamp ID in a misleading way. BUG=None TEST=Build Brox BIOS image and boot to OS. Confirm the timestamp is recorded in cbmem. Change-Id: Icd01c68a5848e2aed7bbdcc794987bc780e78dab Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com>
2024-05-08mb/samsung/lumpy: Fix smbus subsystem IDMatt DeVillier
The smbus subsystem ID was inadvertently reversed when added in commit eb2897b113a0 ("mb/samsung/lumpy: override SMBus subsystem ID"), so correct it. TEST=build/boot Win10 on lumpy, verify touchpad driver functional. Change-Id: I7520041ea113dff8f2abebfc71a1de6d0f9fc91f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-08mb/google/parrot: Fix smbus subsystem IDMatt DeVillier
The smbus subsystem ID was inadvertently reversed when added in commit 6974bcd28e74 ("mb/google/parrot: override SMBus subsystem ID"), so correct it. TEST=build/boot Win10 on parrot, verify touchpad driver functional. Change-Id: I93d4812e24a6fc7419887e364974fcfae2465ea3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-08mb/google/butterfly: Fix smbus subsystem IDMatt DeVillier
The smbus subsystem ID was inadvertently reversed when added in commit a6076cfcfdbe ("mb/google/butterfly: override SMBus subsystem ID"), so correct it. TEST=build/boot Win10 on butterfly, verify touchpad driver functional. Change-Id: If4a0eae06bbe4dcba893a42797e371bbf9f899b9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82225 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-07mb/google/corsola: Add new board variant SquirtleYang Wu
Add a new Kingler follower 'Squirtle'. BRANCH=corsola BUG=b:333826091 TEST=emerge-corsola coreboot Change-Id: I393738fc470ffc907f125647a46bf81c243708d7 Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-05-07mb/adlink: Remove leftover directoryAngel Pons
These boards are clones of LiPPERT boards, which are no longer in this branch (they were AMD AGESA boards). So, drop the ADLINK placeholders. Change-Id: Idfd77daf4a5b3d1e120ed22f9a48fa1bf884de9e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-05-07soc/intel/meteorlake: Determine TBT controllers exist by VID/DIDKane Chen
The original code uses TRE0-TRE3 register to determine whether or not the TBT controller exists. However, there is a remap in fsp could confuse the TRPx._STA. Ex: Disable TBT controller 0 on b:0 d:7 f:0 Enable TBT controller 1 on b:0 d:7 f:1 The FSP will do the remap and after the remap: TBT controller 1 is on b:0 d:7 f:0 TBT controller 0 is on b:0 d:7 f:1 This is becuase func 0 must exist per pci spec. However, the TRE0-TRE3 will not be remapped so that the ACPI TRPx._STA method could be confused. In such scenario, TRP0._STA will return 0x0, TRP1._STA will return 0xf which is wrong because TBT controller 1 is now at b:0 d:7 f:0 TEST=tested on rex and _TRPx._STA returns correctly. TBT function OK Change-Id: I54f2ea99cd1ec73dd0b71a6ba738aa927b0ae80f Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-05-07soc/intel/mtl: Fixed TBT PCIe devtree remappingKane Chen
The TBT PCIe devicetree settings are not remapped properly when TBT PCIe port 0 is disabled. This code refer SHA:58bc5d937 to remap the PCIe devtree settings properly in case of TBT PCIe port0 is disabled, TEST=Tested on screebo and found "Remapping PCIe Root Port #2 msg" showed up in coreboot log Change-Id: I7c7549ddf8ccdd67d7af7c69f51a84614cff9a03 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81841 Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-07dram/ddr3: Use the same naming convention as DDR4Elyes Haouas
Change-Id: Ifaff19c0117b5247d3321605ccc2e97bf8226ca8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82216 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-07dram/ddr5: Use the same naming convention as DDR{2,3,4}Elyes Haouas
Change-Id: I2cc38926b56315d4a828311917ff58051b34b777 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-07spd.h: Move enum ddr4_module_type to ddr4.hElyes Haouas
Move specific enum ddr4_module_type to <device/dram/ddr4.h>. Change-Id: Ia538d2c73affa6560fa1533a40c02b3677588f5a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-07device/dram/ddr{3,4}: Rename spd_raw_data for specific DDRElyes Haouas
Rename different spd_raw_data[] for DDR3 and DDR4. This is to solve the conflict when we include both "ddr3.h" and ddr4.h" for example here: src/device/dram/spd.c. Otherwise, it won't compile as DDR3 and DDR4 have different spd_raw_data[] size. Change-Id: I46597fe82790410fbb53d60e04b7fdffb7b0094a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-07device/device_util: Add and use is_pci_bridge()Shuo Liu
TEST=Build and boot on intel/archercity CRB Change-Id: Ied4921f7dc7e144e580d05d4f2262777aa59d895 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81566 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-07soc/intel/xeon_sp/spr: Print return codes for mp_init_with_smmShuo Liu
TEST=Build and boot on intel/archercity CRB Change-Id: Iee2234a3055fe8a94ecbfc820e9ff9e981f8dff2 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-07soc/intel/xeon_sp/spr: Remove duplicated warningShuo Liu
When microcode is not found, intel_microcode_find() will output warning and skip the update. Remove the duplicated warning in CPU codes. TEST=Build and boot on intel/archercity CRB Change-Id: I0264edc01e90186a7b77d57f9c147d3b73747437 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-07soc/intel/xeon_sp/spr: Add comments for get_thread_countShuo Liu
Add comments to clarify the usage of logical core count instead of physical core count. TEST=Build and boot on intel/archercity CRB Change-Id: I2bc94391f060cec9de91183021da03bc5c7438c0 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82097 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-07soc/intel/xeon_sp/spr: Remove unused file includes in cpu.cShuo Liu
TEST=Build and boot on intel/archercity CRB Change-Id: I17b42331fa9b5f59d1fb1d66b9155c57e258357b Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82191 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-07spd.h: Move enum ddr5_module_type to ddr5.hElyes Haouas
Move specific enum ddr5_module_type to <device/dram/ddr5.h>. Change-Id: Ie38d1e99fa46c278e60ced2d3eef29ca823d4b1d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-05-06soc/intel/xeon_sp: Add fill_pd_distancesShuo Liu
Update a simple algorithm to cover some basic case for proximity domain distance handling. In the same time, the local variable usage of fill_pds() is optimized. TEST=Build and boot on intel/archercity CRB ACPI SRAT, SLIT and DMAR (Remapping Hardware Static Affinity) are generated correctly for 2S system. Change-Id: I2b666dc2a140d1bb1fdff9bc7b835d5cf5b4bbc5 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Co-authored-by: Ziang Wang <ziang.wang@intel.com> Co-authored-by: Gang Chen <gang.c.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81442 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06mb/google/brya/var/bujia: Add VBT data fileShon Wang
Add data.vbt files for bujia supported by brask recovery images. Select INTEL_GMA_HAVE_VBT for bujia which currently have a VBT file. changes: 1. "integrated DisplayPort with HDMI/DVI compatible" -> "Integrated HDMI/DVI". 2. turn the AUX off. BUG=b:327549688 TEST=build/boot various brya variants Change-Id: Id56461708250eaedd288ddbf788d686153df0b96 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81553 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06mb/google/brox:Select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATIONKrishna Prasad Bhat
Brox uses PDC<->PMC direct connection for USBC mux configuration. Select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION to enable it. This patch also adds additional dependency on ENABLE_TCSS_USB_DETECTION to be selected only when PDC<->PMC direct connection and CHROMEOS is not used. BUG=b:332383540 TEST=USB3 plugged during G3, is detected after system boots from G3. Cq-Depend: chromium:5484387 Cq-Depend: chrome-internal:7106592 Change-Id: I0f62943f87d8fb6eb494c0aca3ef08c33cd05ffd Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-05-06common/block/tcss: Add config for PDC<->PMC mux configurationKrishna Prasad Bhat
Introduce a new Kconfig to enable PD controller to PMC mux configuration. Selecting this config enables direct communication from PDC to PMC. TCSS_HAS_USBC_OPS enables USB-C operations via the EC. When SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION is selected, disable TCSS_HAS_USBC_OPS to avoid sending PMC commands from AP/EC. BUG=b:332383540 TEST=USB3 plugged during G3, is detected after system boots from G3. Cq-Depend: chromium:5484387 Cq-Depend: chrome-internal:7106592 Change-Id: Ieeb503393418cdad43384be39ac49c93ba91e4db Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82077 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06mb/google/brya: Correct _PLD valuesWon Chung
For Mithrax and Felwinter, port C1 is on the left side and port C2 is on the right side. Correct the values accordingly. The board schematics was mirrored, so had to obtain an actual machine and physically check the correct ports. BUG=b:321051330 TEST=emerge-${BOARD} coreboot then check ACPI table on DUT Change-Id: I977c3b4081987592a1d46529eb848a07a6c4cb47 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81363 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Emilie Roberts <hadrosaur@google.com>
2024-05-06mb/google/brya: Fix mux_conn index used by ec/google/chromeecWon Chung
Within ec_acpi.c, USB-C ports are iterated to be matched with corresponding mux. The iteration happens from 0 to the number of USB-C ports. Given iteration index i, the port with PLD group_token of (i+1) is matched with mux_conn[i]. Mithrax and Felwinter devicetree matches conn1 to mux_conn[1] and conn2 to mux_conn[0]. However, conn1 is for usbX_port2 which has group_token of 1 and conn2 is for usbX_port3 which has group_token of 2. Thus, follow the convention to add conn1 to mux_conn[0] and conn2 to mux_conn[1]. Otherwise, the kernel subsystem linking between Type C connector and USB mux will be swapped. BUG=b:329657774 b:121287022 b:321051330 b:204230406 TEST=emerge-${BOARD} coreboot then check ACPI table on DUT. TEST=Manually check that usb-role-switches are mapped to the correct port. Attach USB 3 A to C cable from development machine to left port of DUT. Attach nothing to right-hand port. usbpd lines are workaround for devices without firmware patch to connect superspeed lines. ectool usbpd 0 none ectool usbpd 0 usb ectool usbpd 1 none ectool usbpd 1 usb echo host > /sys/class/typec/port0/usb-role-switch/role (should succeed) echo host > /sys/class/typec/port1/usb-role-switch/role (should fail as no cable attached) Change-Id: I349682a6fe3fe4848e4e86d9c446530a31b35875 Signed-off-by: Won Chung <wonchung@google.com>, Emilie Roberts <hadrosaur@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81354 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Emilie Roberts <hadrosaur@google.com>
2024-05-06drivers/intel/pmc_mux/conn: Copy ACPI _PLD property from USB port to muxWon Chung
Copy ACPI _PLD values from USB ports to corresponding USB muxes so that the kernel can create symlinks between Type C connectors and corresponding USB muxes. This symlink will be used to let userspace be able to modify the USB role without knowing ACPI topology for the device. BUG=b:121287022 b:329657774 TEST=emerge-${BOARD} coreboot then check ACPI table on DUT Change-Id: If27042cc995ef188f8a3e31444e994318ff98803 Signed-off-by: Won Chung <wonchung@google.com> Tested-by: Emilie Roberts <hadrosaur@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81089 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Emilie Roberts <hadrosaur@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06soc/intel/xeon_sp/acpi: Refactor Xeon-SP ASL file locationShuo Liu
soc/intel/xeon_sp/acpi/*.asl are actually used only by SKX and CPX platforms and not forward compatible to later SoC generations. Move them to soc/intel/xeon_sp/acpi/gen1/ for clean maintenance. TEST=Build and boot on intel/archercity CRB Change-Id: Ib060b123ab0fd761f00d9a0573e9b73d600ea9ef Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82033 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06acpi: Remove acpigen_write_OSC_pci_domainShuo Liu
For PCI domains, static _OSC will be used for better readability and maintenance. This reverts commit f4a12e1d39a097e17007ef11ccf784c2a42f1924. TEST=Build and boot on intel/archercity CRB Change-Id: I2e2b2f0533a3940caf2806ec1ed048c30e4ba801 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82032 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06mb/system76: Exclude ramtop from CMOS checksumTim Crawford
Use the default position for ramtop and exclude it from the checksum. Fixes invalid checksum after caching ramtop causing things like disabling CSME to not work. Fixes: 10d2af04e754 ("mb/system76: Add space for ramtop in CMOS layout") Change-Id: If30df1e6f2735cf767856e42dfede3d17fe494eb Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81641 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06mb/google/nissa/var/sundance: Use default eMMC DLL settingLeo Chou
Configure eMMC DLL tuning values for Sundance board Samsung sku. BUG=b:337741162 TEST=Use the value to boot on Sundance successfully. Change-Id: I5f1e03c06c9f8567e757fed999730dff2551f1e0 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82173 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06mb/google/sarien: Make use of chipset dt reference namesFelix Singer
Replace the PCI numbers with the reference names from the chipset devicetree. Also, remove their comments since they are superfluous now. Change-Id: I49f5fda5628b2ebc76cd8db20c8f7fe85c676c7a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-05-06mb/google/sarien: Remove dt entries equal to chipset dtFelix Singer
Clean up the devicetree by removing entries which are equal to the chipset devicetree. The P2SB device is enabled but it's hidden by the FSP. So just remove that as well since the chipset devicetree configures it correctly. Change-Id: I38f46949d36359826317252e8d3434ad1b24382d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82156 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06mb/google/drallion: Make use of chipset dt reference namesFelix Singer
Replace the PCI numbers with the reference names from the chipset devicetree. Also, remove their comments since they are superfluous now. Change-Id: Ib873854954e44b3ea370c2574da5db9792a446e9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82155 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06mb/google/drallion: Remove dt entries equal to chipset dtFelix Singer
Clean up the devicetree by removing entries which are equal to the chipset devicetree. The P2SB device is enabled but it's hidden by the FSP. So just remove that as well since the chipset devicetree configures it correctly. Change-Id: I6186d295427bcd4a3b696f4df59d94a148ced011 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-05-06mb/google/brya/var/pujjoga: Add GPIO tableleo.chou
Fill GPIO table for pujjoga. BUG=b:336469694 TEST=emerge-nissa coreboot Change-Id: I3f633cf99f56d5f855015de805e16c1205c9bc99 Signed-off-by: leo.chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82044 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-05-06mb/google/brya/var/xol: Override TDP PL1 valueSeunghwan Kim
Update TDP PL1 value for the DTT optimization. The new value 18W is from internal thermal/performance team. - tdp_pl1_override: 15 -> 18 (W) BUG=b:336684032 BRANCH=brya TEST=built and verified MSR PL1 value. Intel doc #614179 introduces how to check current PL values. [Original MSR PL1/PL2/PL4 register values for xol] cd /sys/class/powercap/intel-rapl/intel-rapl\:0/ grep . *power_limit* constraint_0_power_limit_uw:15000000 <= MSR PL1 (15W) constraint_1_power_limit_uw:55000000 <= MSR PL2 (55W) constraint_2_power_limit_uw:114000000 <= MSR PL4 (114W) After this patch: constraint_0_power_limit_uw:18000000 constraint_1_power_limit_uw:55000000 constraint_2_power_limit_uw:114000000 Change-Id: I28c4f099e0169e8389f63083c03023dd8338589f Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82151 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06mb/google/brya/var/xol: Tune I2C5 timing parametersSeunghwan Kim
Update I2C5 timing parameter values to meet I2C bus spec. - fall_time_ns: 400 -> 200 BUG=None BRANCH=brya TEST=built and measure I2C5 timing parameters Before: tLOW : 1.88 us (spec >= 1.30) tHIGH: 0.57 us (spec >= 0.60) fSCL : 399.80 KHz After: tLOW : 1.60 us (spec >= 1.30) tHIGH: 0.97 us (spec >= 0.60) fSCL : 392.1 KHz Change-Id: I386b2765410fd10b8cd711f54478fb52428de5a3 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-06mb/google/nissa: Create a riven variantDavid Wu
Create the riven variant of nissa reference board by copying the template files to a new directory named for the variant. The riven variant is a twinlake platform. BUG=b:337169542 TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_RIVEN Change-Id: I1be2346d87c891cc0e5fbda094e1f6e0dd60df1b Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82132 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06mb/google/corsola: Sort Kconfig board selection in alphabet orderYidi Lin
Change-Id: Iefe61d3ad51d355806716483248df5b1083b69bc Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82149 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06drivers/intel/mipi_camera: Add CSI2 Data Stream Interface GUIDCoolStar
Required in SSDB for Windows drivers. Tested on google/brya (kano) and verified Intel Webcam shows up to Windows as a camera source Change-Id: Id6089f6bd841333882e28de9307fe5e48e368d02 Signed-off-by: CoolStar <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82068 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06mb/google/nissa/var/pujjoga: Generate SPD IDsroger2.wang
Add pujjoga supported memory parts in mem_parts_used.txt, generate SPD id for this part. 1. Samsung K3KL6L60GM-MGCT, K3KL8L80CM-MGCT 2. Hynix H9JCNNNBK3MLYR-N6E, H58G56BK7BX068 3. Micron MT62F1G32D2DS-026 WT:B BUG=b:337990338 TEST=Use part_id_gen to generate related settings Change-Id: I39d44fd278474a7375ad1d2d904d14b9463ba86d Signed-off-by: roger2.wang <roger2.wang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82135 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-05-06mb/google/nissa/variant/pujjoga: Update devicetree settingsroger2.wang
Based on schematic of 500E_GEN4S_ADL_N_MB_0418, generate overridetree.cb settings for Pujjoga. BUG=b:337611700 TEST=FW_NAME= pujjoga emerge-nissa coreboot chromeos-bootimage Change-Id: I279f94044a22f25100a44b1abe2ef5fb6d0dd835 Signed-off-by: roger2.wang <roger2.wang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82109 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-05-06soc/amd/phoenix/include/platform_descriptor: remove TODOFelix Held
There's nothing in this header file that needs to be updated for the Phoenix SoC, so remove the 'Update for Phoenix' TODO. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9d7b5e8d8d6c8c22c2fae8e89d073481d21d8bdc Reviewed-on: https://review.coreboot.org/c/coreboot/+/82150 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06mb/lenovo/*: Set VR12 PSI to fix crashPatrick Rudolph
When in Package C3 or deeper the PSI settings are used to switch the CPU VR into a low power state. It was found that the voltage regulator on the Sandy-Bridge series has non-default PSI settings, compared to Lenovo's Ivy-Bridge series. Apply the same PSI value for PSI2 and PSI3 as the vendor BIOS does to fix a hang when the package is idle. Since neither the vendor BIOS is open-source, nor datasheet exists for the used VR it's unclear why those PSI values must be used and how they influence the regulator. The X220 already has the correct PSI values configured and is now stable for more than 24h in Package C7 state. TEST: Not tested on the affected boards, only checked vendor firmware. Change-Id: Idf8c3719f19f7bcdab30c543215c8abd2669cfd2 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-06block/fast_spi: Use read32p/write32p for SPI RWAshish Kumar Mishra
The current fast_spi code uses memcpy for rw. The SPI flash read/write has 4 byte limit, due to which the current 64 bit memcpy doesn't work. Hence update rw ops to use read32p/write32p. BUG=b:242829490 TEST=Verified MRC cache working on MTL 64-bit, future 64 bit platforms and RPL(brox/skolas) 32-bit platforms. Change-Id: I317c7160bf192dd2aeacebf6029a809bc97f3420 Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-06mb/google/rex/var/deku: Update psys_pmax_watt value to 180WTony Huang
Adjust setting is from power team. Change from 172W to 180W BUG=b:320410462 BRANCH=firmware-rex-15709.B TEST= FSP debug emerge-ovis coreboot intel-mtlfsp check overrides setting Change-Id: Icc8b12adc9fb9f680b05131c8d41212865223ca9 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-05-06mb/google/rex/var/deku: Update FVM itrip for VR domainTony Huang
Adjust setting is from power team. Itrip(GT) FVM 54 Itrip(SA) FVM 27 BUG=b:320410462 BRANCH=firmware-rex-15709.B TEST= FSP debug emerge-ovis coreboot intel-mtlfsp check overrides setting Change-Id: I6d6cf7cecaac650a7b1784833b4afb8dffb3db2c Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82176 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-03soc/intel/xeon_sp/spr: Drop unused symbolElyes Haouas
SOC_INTEL_PCIE_64BIT_ALLOC is not used. Change-Id: I1ef52104ef1d883330b800215cb4d0475092d8fe Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81975 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-03drivers/wifi/generic: Fix a typo on symbolElyes Haouas
WIFI_MTCL_CBFS_FILEPATH is now used. Change-Id: Icdd0332ae9c56a54596a775c0a9aa7b9f8d6738c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-03mb/google/brya/var/xol: Update board type to BOARD_TYPE_ULT_ULXSeunghwan Kim
Correct .UserBd field to BOARD_TYPE_ULT_ULX from BOARD_TYPE_MOBILE. This is from Intel's guidance for MRC to map the memory speed to proper POR number. BUG=b:332980211 BRANCH=brya TEST=Built and compare the results of command 'dmidecode -t 17' [Before] (Same values in all of memory device handle) Speed: 6400 MT/s Configured Memory Speed: 6400 MT/s [After] (Same values in all of memory device handle) Speed: 5200 MT/s Configured Memory Speed: 5200 MT/s Change-Id: Id16bcbc2d0cb4c2cf3008cf2ef1027ed98e93afb Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Chen <jamie.chen@intel.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-03drivers/intel/fsp2_0: Release bmp_logo during OS_PAYLOAD_LOAD stageKarthikeyan Ramasubramanian
bmp_load_logo() loads the custom logo.bmp file into CBMEM. This cbmem buffer is released after FSP-S init is complete. In certain platforms, the logo file is displayed during PCI enumeration. This means the logo buffer is used after it is released. Fix this issue by releasing the logo buffer when the coreboot has finished loading payload. During S3 scenario CBMEM is locked, bmp logo is not loaded and hence the release is a no-op. BUG=b:337144954 TEST=Build Skyrim BIOS Image and boot to OS. Ensure that the chromeOS boot logo is seen without any corruption. Change-Id: Id27cf02de04055075e7c1cb0ae531dee8524f828 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82121 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-05-03soc/intel/xeon_sp: Remove unused xeonsp_acpi_create_madt_lapicsShuo Liu
TEST=Build and boot on intel/archercity CRB Change-Id: I06e5ff635c37253b1c8f151b62f696ff7e5e22ef Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82110 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-03mb/google/corsola: Initialize USB port 0Wentao Qin
The default MT8186 platform is to initialize USB3 port 1. Use option bit 27 in fw_config to enable initialization of USB2 port 0 to support devices mounted on it. BUG=b:335124437 TEST=boot to OS from USB-A boot to OS from SD Card BRANCH=corsola Change-Id: I725b80593f5fc498a204bf47f943c36ccbd78134 Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82089 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-05-02mb/raptor-cs/talos-2: add basic mainboard structureMichał Żygowski
Change-Id: I0c4f74c7b27c8bb5599d68305adf369ddc6fcc70 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-02soc/ibm/power9/*: add file structure for SOCIgor Bagnucki
Boot device is stubbed to be able to build boards without errors. Change-Id: Ie74b1e34f9aebe151d0fdb0e95c003510fd864c3 Signed-off-by: Igor Bagnucki <bagnucki02@gmail.com> Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-02soc/intel/xeon_sp: Use fixed BDF for IBLShuo Liu
Integrated Boot Logic (IBL) codes doesn't support bootloader controlled Primary-to-Sideband Bridge (P2SB) hidden and unhidden. Hence, dynamically read IBL HPET/IOAPIC Bus:Device.Function (BDF) by bootloader is not supported, because when P2SB is hidden the register access is denied. TEST=Build and boot on intel/archercity CRB TEST=Build on intel/avenuecity CRB TEST=Build on intel/beechnutcity CRB Change-Id: I3975cb00e215c4984c63bb8510e8aef7d4cc85a4 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81321 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-02soc/intel/xeon_sp: Move VPD based settings to mainboard codesShuo Liu
Configuration variable implementation (VPD, et al) is regarded to be mainboard specific and should not be bounded to SoC codes. This patch moves the VPD based settings (FSP log level, et al) from SoC codes to mainboard codes. TEST=Build and boot on intel/archercity CRB with no significant log differences Change-Id: Iefea72eec6e52f8d1ae2d10e1edbabdebf4dff91 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82090 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-02soc/intel/xeon_sp: Add get_cxl_modeShuo Liu
Configuration variable implementation (VPD, et al) is regarded to be mainboard specific and should not be bounded to SoC codes. Add get_cxl_mode so that SoC codes do not need to get this configuration from VPD any more. TEST=Build and boot on intel/archercity CRB with no significant log differences Change-Id: I1e08e92ad769112d7e570ee12cf973451a3befc0 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-02soc/intel/mtlrvp: use different names for mtlrvp variantsYH Lin
This patch sets different names for different mtlrvp variants so they can be matched properly at runtime against unique frids (i.e. firmware read-only identifiers). BRANCH=firmware-rex-15709.B TEST=Verified boot functionality on intel/mtlrvp Change-Id: I5292a0ffcd7524c55cd7aef37c2f59432b2af06a Signed-off-by: YH Lin <yueherngl@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-02soc/intel/xeon_sp: Clean up device enablement configurationFelix Singer
Clean up by using is_devfn_enabled(). Change-Id: I9ea3d8b1b18e84a75a81a7e926d2c638766bb493 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82120 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-02soc/intel/cannonlake: Clean up device enablement configurationFelix Singer
Clean up by using is_devfn_enabled(). Change-Id: I9a4984a096e72025e161bf117b70a7c59f2bb094 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82118 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-02soc/intel/xeon_sp: Add device to proximity domain map utilsShuo Liu
In NUMA architecture, all devices (cpu, memory and PCI device) belong to specific proximity domain. Add utils to map device instance to their proximity domain. Proximity domain ID is the index assigned at the creation of proximity domains. There is no hard relationship between proximity domain ID and the device identities (e.g. socket ID). Hence we need the map utils to explicitly link them. For now the Sub-NUMA config isn't taken into account. TEST=Build and boot on intel/archercity CRB Change-Id: Icd14a98823491ccfc38473e44a26dddfbbcaa7c0 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Co-authored-by: Ziang Wang <ziang.wang@intel.com> Co-authored-by: Gang Chen <gang.c.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81440 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-02soc/intel/xeon_sp: Make NUMA support by defaultShuo Liu
TEST=Build and boot on intel/archercity CRB Change-Id: I84f07c16e24e441a885144df8c805f1310acae29 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Co-authored-by: Ziang Wang <ziang.wang@intel.com> Co-authored-by: Gang Chen <gang.c.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81439 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-30soc/intel/alderlake: Default to 512 for DIMM_SPD_SIZEFelix Singer
Alderlake and Raptorlake SoCs support DDR4 and DDR5, which have a total SPD size of 512 bytes. Set this as the default and remove the setting from mainboard Kconfigs. Change-Id: I8703ec25454a0cd55a3de70f73d2117285a833ae Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82115 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-30drivers/intel/fsp2_0: Default to 64-bits for FSP 2.4Jeremy Compostella
Sets`PLATFORM_USES_FSP2_X86_32' to `n' by default if FSP 2.4 is enabled as 64-bits FSP should be norm moving forward. BUG=b:329034258 TEST=verified on Lunar Lake RVP board (lnlrvp) Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec98 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80323 Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-04-30drivers/intel/fsp2_0: Add dedicated caller function for ap procedure callsAppukuttan V K
Add FSP 2 Multi Processor Platform Initialization module a function indirection to ensure that efi_ap_procedure functions are called with the appropriate C calling convention. BUG=b:329034258 TEST=Verified both x86_32 and x86_64 builds on Meteor Lake board (Rex) Change-Id: I64e65b2941207375d5e27c84aa26061e7e72a7f6 Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81663 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-30drivers/intel/fsp2_0: Remove x64-specific assertion from fsp_headerAppukuttan V K
Same fsp_header struture is being used for x64 and x32 modes and hence dropping the x64 assertion. BUG=b:329034258 TEST=Verified on Meteor Lake board (Rex) Change-Id: I6013af342670e6377a3fe7641d7d9b52c9b6f57c Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81662 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Usha P <usha.p@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-30drivers/intel/fsp2_0: Make coreboot FSP stack 16-bytes alignedAppukuttan V K
- Stack alignment: 1. FSP functions must be called with the stack 16-bytes aligned in x86_64 mode.This is already setup properly with the default value of the `mpreferred-stack-boundary' compiler option (4). 2. The FSP heap buffer supplied by coreboot through the `StackBase' UPD must be 16-bytes aligned. This alignment is consistent for both x86_64 and x86_32 modes to simplify the implementation. BUG=b:329034258 TEST=Verified on Meteor Lake board (Rex) Change-Id: I86048c5d3623a29f17a5e492cd67568e4844589c Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81661 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
2024-04-30mb/google/brya/var/xol: Add EC_IN_RW_OD config into early_gpio_tableSeunghwan Kim
Add GPP_F18 configuration in early_gpio_table. Without this, DUT cannot get the proper state of this signal on early phase. It allowed DUT to attempt to enter into dev mode when EC is in RW currently, it causes the failure of autotest/firmware_DevMode. BUG=b:337365524 TEST=built and run autotest firmware_DevMode Change-Id: I2179bb10b431547bc35f332c74915a63495b779d Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82099 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: YH Lin <yueherngl@google.com>
2024-04-30mb/google/brox: Add 20K pulldown to GPP_D14Shelley Chen
GPP_D14 is floating when ISH is not being used and wasting power. Add pulldown to prevent this from happening. BUG=b:336654954 BRANCH=None TEST=emerge-brox coreboot chromeos-bootimage make sure OS boots up HW team validated that power usage is 20 mW lower Change-Id: I4e19e98fa31022ece66a47402a2a4461b430ef70 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-04-29soc/intel/cmn/graphics: Make DDI-A 4 lanes configurableAngel Pons
As described in Intel document 336464 (8th gen S series datasheet volume 1), the CPU's 4 eDP lanes can be bifurcated, so that DDI-A (eDP) ends up with 2 lanes, and DDI-E (DP, typically used for VGA) has the remaining 2 lanes. This lets mainboards provide a VGA output without sacrificing one of the main 4-lane DDIs. Newer platforms seem to be lacking this. However, the way this is structured in coreboot does not allow boards to choose whether bifurcation should be enabled. Most boards in the tree do not use DDI-E (it doesn't exist on mobile platforms), but there are some boards (e.g. hp/280_g2) that use DDI-E and a DP-to-VGA converter chip to provide a VGA output. Replace `SOC_INTEL_CONFIGURE_DDI_A_4_LANES` with two new Kconfig options to allow boards to decide. Use `SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION` to specify whether a platform supports DDI-A bifurcation at all (do nothing otherwise, maintaining the original code's behaviour). If bifurcation is supported, the `SOC_INTEL_GFX_ENABLE_DDI_E_BIFURCATION` is used to clear or set the `DDI_A_4_LANES` bit in the `DDI_BUF_CTL_A` register. Change-Id: I516538db77509209d371f3f49c920476e06b052f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82113 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-29mb/hp/280_g2: Fix comment in `gma-mainboard.ads`Angel Pons
The DVI connector on this board is DVI-D (digital only), not DVI-I. Change-Id: I74c1257efb67cfdff2ae04a42c163dd320c850a4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82112 Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-04-29mb/google/brox: Fix the pad reset config for Touchpad interruptKarthikeyan Ramasubramanian
Update the pad reset config for Touchpad Interrupt from PLTRST to DEEP so that it can still act as a wake source during S3 suspend. BUG=b:336398012 TEST=Build Brox BIOS image and boot to OS. Suspend to S3 and wakeup using Trackpad. 246 | 2024-04-25 16:55:18-0700 | ACPI Enter | S3 247 | 2024-04-25 16:55:34-0700 | ACPI Wake | S3 248 | 2024-04-25 16:55:34-0700 | Wake Source | GPE # | 67 249 | 2024-04-25 17:00:38-0700 | ACPI Enter | S3 250 | 2024-04-25 17:00:47-0700 | ACPI Wake | S3 251 | 2024-04-25 17:00:47-0700 | Wake Source | GPE # | 67 Also suspend to S0ix and wakeup using Trackpad. Change-Id: If1a275e42c6c7ad743eedc9cd3320776008bfd62 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2024-04-29include/device/pci_ids.h, soc/intel/mtl: add new MTL-P iGPU DIDMichał Kopeć
Found in a Clevo V560TU with Intel Core Ultra 155H Change-Id: I0f10808fd0e2d9c122743615fbce656c6d2447cc Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82071 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-29soc/intel/xeon_sp: Support CHIPSET_LOCKDOWN_FSPShuo Liu
In a server platform many silicon specific register lock operations are by default in FSP space. CHIPSET_LOCKDOWN_FSP provides an option to make sure the codes could be used out-of-box to build products. Change-Id: I8efcc1f27446be8e35f51e2568c4af6f8165486b Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82081 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-04-29mb/google/brya/xol: Add Fn key scancodeAseda Aboagye
The Fn key on Xol emits a scancode of 94 (0x5e). BUG=b:327656989 TEST=Flash xol, boot to Linux kernel, and verify that KEY_FN is generated when pressed using `evtest`. Change-Id: I34ed93d9666504bfd4d439e166911e49f58e5ff5 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82069 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-04-28acpi: Fix return value in acpi_device_write_dsd_gpio()Jianeng Ceng
Fix ++ as suffix and * precedence. After modification, the gpio index can be obtained correctly. The error was introduced in the commit making it public: commit 01344bce BUG=None TEST= Can get the correct index test on nissa. Change-Id: I7a3eb89633aaebebc8bd98ac6126c578fda23839 Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82088 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-26mb/framework: Push initial port of azalea (Framework 13 AMD 7040)Martin Roth
This is a minimal framework that allows the build to compile. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ief4b5c75471a2ef5bedaaee9b4737510c2826b6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/81978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-04-26soc/amd/genoa_poc/chip.h: remove empty newline before '}'Felix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7f18f2d754f24bfcc9cbf95a98fa6fe40aaf3b02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-04-26drivers/pc80/tpm: Disable device if TPM not presentMichał Żygowski
If the TPM is not detected in the system it may mean it is inactive due to enabled ME with active PTT. In such case, the chipset will route the TPM traffic to PTT CRB TPM on Intel systems. If TPM is not probed, disable the PC80 TPM device driver, so that coreboot will not generate improper SSDT ACPI table. Change-Id: I05972ad74a36abaafa2f17a16f09710550a3a3f3 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
2024-04-26drivers/crb: Disable device if CRB TPM not presentMichał Żygowski
If CRB TPM is not detected in the system it may mean it is inactive due to disabled or neutered ME. In such case, the chipset will route the TPM traffic to LPC/SPI on Intel systems. If CRB TPM is not probed, disable the CRB TPM device driver, so that coreboot will not generate improper SMBIOS/SSDT ACPI tables. Change-Id: Ie0928536d9042b1f680d585e1ca9ad2cadf0c8ef Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
2024-04-26mb/google/rex: remove duplicate config for karisYH Lin
Remove duplicate config entry CHROMEOS_WIFI_SAR as it is used at the baseboard. BUG=None TEST=emerge-rex coreboot Change-Id: Iabf0e490103c2097f3f033036839b77b5a0bb1b3 Signed-off-by: YH Lin <yueherngl@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81226 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-26arch/arm/armv7/exception.c: fix warnings of macros and functionsIntegral
Use better alignment attribute macro and add missing identifier names for function definition arguments. Change-Id: I1c5c33fc9210f068ff88c8d981f1a1c739890c9c Signed-off-by: Integral <integral@member.fsf.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82050 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-25vc/google/chromeos: Move RAMOOPS region creation to BS_DEV_INIT_CHIPSAnil Kumar
RAMOOPS memory region was being overwritten by coreboot bmp_load_logo() function. The CBMEM_ID_FSP_LOGO region created during bmp_load_logo() was overlapping with RAMOOPS space created earlier. This resulted in memory corruption of RAMOOPS buffer. To prevent this, the RAMOOPS region allocation is moved to BS_DEV_INIT_CHIPS phase from earlier BS_WRITE_TABLES phase of boot. BUG=b:332910298 TEST=build and boot coreboot image on google/rex HW. Check RAMOOPS CBMEM region creation using cbmem -l command Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: Ibae06362cd80eacb16f6cf0eed8c9aa1fbfb2535 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82042 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-04-25mb/google/brox/var/lotso: Add fw_config field for storagetongjian
Add STORAGE_UNKNOWN, STORAGE_UFS, STORAGE_NVME for storage fw_config field to prevent depthcharge build break. BUG=b:333494257 TEST=emerge-brox coreboot depthcharge sys-boot/chromeos-bootimage Change-Id: Idb62e3f37e1480979ae529692455beb533434520 Signed-off-by: tongjian <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82056 Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-25mb/google/nissa/var/glassway: Enable Wi-Fi sar table for Intel moduleDaniel_Peng
1.Enable CHROMEOS_WIFI_SAR flag to load a SAR table for Intel module. 2.Describe the FW_CONFIG probe for the settings on glassway. - WIFI_SAR_0 for Intel Wi-Fi module AX211 BUG=336051631 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I9e43081c93ef17291c5d55cf262a0f4d1497447b Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81781 Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-25mb/google/brya/var/nova: Add initial configurationsKenneth Chan
Upload initial configuration for nova based on proto schematics. Memory: SAMSUNG 2G*4 K4U6E3S4AB-MGCL HYNIX 2G*4 H9HCNNNBKMMLXR-NEE BUG=b:328711879 TEST=FW_NAME=nova emerge-constitution coreboot chromeos-bootimage Change-Id: Ic9ff3ed2fb3a7f0f100385d0a0444d38fcff5c51 Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2024-04-25mb/google/nissa/var/yaviks: Add stop pin for G2 touchscreenWisley Chen
Add stop pin control for G2 touchscreen BUG=b:335803573 TEST=build and verified Touchscreen work normally Change-Id: I7e0bbc7722cdda6bcca0485009fcf8510b1f55e2 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81971 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-25drivers/crb: Check for PTT before attempting to initialize CRB TPMMichał Żygowski
We can assume that platforms, which select HAVE_INTEL_PTT, will not have any other CRB TPM than PTT. Check whether PTT is available before forcefully initializing the TPM and selecting the CRB interface in the TPM configuration registers. Change-Id: If0ec6217b0e321b7d7a9410b70defde3c3195fc3 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80453 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-04-25mb/google/corsola/var/wugtrio: Add STA_ER88577 MIPI panelYang Wu
Add STA_ER88577 MIPI panel for Wugtrio. Datasheet: 2081101BH8028073-50E_Pre Spec_240424.pdf BUG=b:331870701 TEST=emerge-staryu coreboot chromeos-bootimage BRANCH=corsola Change-Id: I279d431d80ca0770540d88e213d4aeafe77038ce Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82055 Reviewed-by: Xuxin Xiong <xuxinxiong@huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-25drivers/mipi: Add support for STA_ER88576 panelYang Wu
Add STA panel STA_ER88577 serializable data to CBFS. Datasheet: 2081101BH8028073-50E_Pre Spec_240424.pdf About the init code, we communicated with the vendor through the datasheet to confirm the writing method of each register value. BUG=b:331870701 TEST=build and check the CBFS includes the panel BRANCH=None Change-Id: I210b23b67fbc102c9926171f1c78f6824820e4b7 Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82054 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-24soc/amd/common/amd_pci_util.h: assign 0 to PIN_A in pcie_swizzle_pinFelix Held
Explicitly assign a value of 0 to the first value of the pcie_swizzle_pin enum. This won't change the behavior, but clarifies that the actual values of the enum elements matter. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I21850e21f859f2079f804d4344a1a11856b27d90 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-04-24soc/amd/common/amd_pci_util.h: rename bridge irq in pci_routing_infoFelix Held
Rename the 'irq' element of the pci_routing_info struct to 'bridge_irq' to better describe what it's doing. This struct element contains the number of the northbridge IOAPIC IRQ input the bridge IRQ is connected to signal power management or error reporting IRQs. Right now, coreboot doesn't put this information into the ACPI bytecode. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6410be673d15d6f9b5eb4c80b51fb705fec5b155 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-27 05:27:47 +0000