mb/asrock/z97_extreme6: Add new mainboard

That's an ATX mainboard with a LGA1150 socket and four DDR3 DIMM slots.
Porting was done using autoport and then doing a bunch of manual edits.

This board has two socketed DIP-8 SPI flash chips and a physical switch
to choose which one should the system boot from. As long as one of them
contains a bootable firmware image, it is possible to reflash the other
chip using the internal programmer by flipping the switch after booting
to OS. Even if one somehow manages to flash unbootable firmware to both
chips, they are socketed: one can carefully remove them from the socket
and reflash them externally, which is a relatively safe procedure (when
compared to in-circuit flashing, especially if the board isn't designed
to safely be flashed in-circuit). In short, the board is hard to brick.

Haswell MRC.bin cannot be used because it lacks support for the Z97 PCH
found on this mainboard. Broadwell MRC.bin only works with Haswell CPUs
so far, as raminit fails on Broadwell CPUs for an unknown reason. Maybe
it's something about RcvEn, but it's unlikely it can easily be fixed.

Working:
 - All four DIMM slots
 - Broadwell MRC.bin for raminit purposes
 - Serial port to emit spam
 - POST code display
 - S3 suspend/resume
 - All rear USB 3.0 ports
 - Internal USB 2.0 port
 - Audio output (green jack)
 - Integrated graphics (libgfxinit)
 - HDMI
 - VBT
 - Intel GbE (I218-V PHY and PCH MAC)
 - Realtek RTL8111E GbE
 - At least one SATA port
 - M2_1 slot (Gen3 x4, bifurcated from CPU)
 - Flashing internally with flashrom
 - SeaBIOS (current version) to boot Arch Linux
 - NCT6791D Super I/O software-based fan control
   tested using `sensors` and `pwmconfig`, all 6
   fan tachometers and 5 PWM outputs work fine.

Untested for now (i.e. should work, will eventually test):
 - DVI-I, DisplayPort
 - EHCI debug
 - Front USB 2.0 and 3.0 ports
 - The other audio jacks (as well as SPDIF)
 - The other PCIe and M.2 ports
 - Non-Linux OSes
 - PS/2 combo port (can only test with a keyboard)

Untestable (i.e. cannot test due to unavailable hardware):
 - Thunderbolt AIC (Add-In Card) support

Not working:
 - Broadwell CPUs, they require more magic to work (working on it).
 - Booting from ASM1062 SATA ports with SeaBIOS. Other payloads were
   not tested. It seems that the problem is with the controllers.
 - Super I/O automatic fan control: not yet implemented in coreboot.
   To control fans, use software fan control methods in the meantime.
 - Acer B247Y board driving a FHD panel of a Samsung S24E650 monitor,
   connected to the board's HDMI output says "Unsupported resolution"
   after libgfxinit configured the iGPU outputs in linear framebuffer
   mode. HDMI output works fine after Linux's i915 driver takes over.
   Not sure if it's specific to the monitor: the HDMI cable is beaten
   up, and it is hard to replace (need to relocate the logic board so
   that the ports are accessible).

Change-Id: If1d22547725e59f435de36b973e1bf4f334269a9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Máté Kukri <kukri.mate@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

15 files changed, 619 insertions, 0 deletions

diff --git a/src/mainboard/asrock/z97_extreme6/Kconfig b/src/mainboard/asrock/z97_extreme6/Kconfig
new file mode 100644
index 0000000000..d47e3a2047
--- /dev/null
+++ b/src/mainboard/asrock/z97_extreme6/Kconfig
@@ -0,0 +1,29 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+if BOARD_ASROCK_Z97_EXTREME6
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_8192
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select INTEL_GMA_HAVE_VBT
+	select MAINBOARD_HAS_LIBGFXINIT
+	select MAINBOARD_USES_IFD_GBE_REGION
+	select MEMORY_MAPPED_TPM
+	select NORTHBRIDGE_INTEL_HASWELL
+	select SERIRQ_CONTINUOUS_MODE
+	select SOUTHBRIDGE_INTEL_LYNXPOINT
+	select SUPERIO_NUVOTON_NCT6791D
+	select USE_BROADWELL_MRC if !USE_NATIVE_RAMINIT
+
+config CBFS_SIZE
+	default 0x200000
+
+config MAINBOARD_DIR
+	default "asrock/z97_extreme6"
+
+config MAINBOARD_PART_NUMBER
+	default "Z97 Extreme6"
+
+endif
diff --git a/src/mainboard/asrock/z97_extreme6/Kconfig.name b/src/mainboard/asrock/z97_extreme6/Kconfig.name
new file mode 100644
index 0000000000..2443587640
--- /dev/null
+++ b/src/mainboard/asrock/z97_extreme6/Kconfig.name
@@ -0,0 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+config BOARD_ASROCK_Z97_EXTREME6
+	bool "Z97 Extreme6"
diff --git a/src/mainboard/asrock/z97_extreme6/Makefile.mk b/src/mainboard/asrock/z97_extreme6/Makefile.mk
new file mode 100644
index 0000000000..513c347cbd
--- /dev/null
+++ b/src/mainboard/asrock/z97_extreme6/Makefile.mk
@@ -0,0 +1,6 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+bootblock-y += bootblock.c
+bootblock-y += gpio.c
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/asrock/z97_extreme6/acpi/ec.asl b/src/mainboard/asrock/z97_extreme6/acpi/ec.asl
new file mode 100644
index 0000000000..16990d45f4
--- /dev/null
+++ b/src/mainboard/asrock/z97_extreme6/acpi/ec.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: CC-PDDC */
+
+/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/asrock/z97_extreme6/acpi/platform.asl b/src/mainboard/asrock/z97_extreme6/acpi/platform.asl
new file mode 100644
index 0000000000..7da03bfddd
--- /dev/null
+++ b/src/mainboard/asrock/z97_extreme6/acpi/platform.asl
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Method(_PTS, 1)
+{
+}
+
+Method(_WAK, 1)
+{
+	Return(Package(){0, 0})
+}
diff --git a/src/mainboard/asrock/z97_extreme6/acpi/superio.asl b/src/mainboard/asrock/z97_extreme6/acpi/superio.asl
new file mode 100644
index 0000000000..ee2eabeb75
--- /dev/null
+++ b/src/mainboard/asrock/z97_extreme6/acpi/superio.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/asrock/z97_extreme6/board_info.txt b/src/mainboard/asrock/z97_extreme6/board_info.txt
new file mode 100644
index 0000000000..bd01474254
--- /dev/null
+++ b/src/mainboard/asrock/z97_extreme6/board_info.txt
@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: https://www.asrock.com/mb/intel/z97%20extreme6/
+ROM package: DIP-8
+ROM protocol: SPI
+ROM socketed: y
+Flashrom support: y
+Release year: 2014
diff --git a/src/mainboard/asrock/z97_extreme6/bootblock.c b/src/mainboard/asrock/z97_extreme6/bootblock.c
new file mode 100644
index 0000000000..318cc034f2
--- /dev/null
+++ b/src/mainboard/asrock/z97_extreme6/bootblock.c
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/pnp_ops.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct6791d/nct6791d.h>
+
+#define GLOBAL_DEV	PNP_DEV(0x2e, 0)
+#define SERIAL_DEV	PNP_DEV(0x2e, NCT6791D_SP1)
+#define ACPI_DEV	PNP_DEV(0x2e, NCT6791D_ACPI)
+#define GPIO_PP_OD_DEV	PNP_DEV(0x2e, NCT6791D_GPIO_PP_OD)
+
+/*
+ * Asrock Z97 Extreme6 Super I/O GPIOs
+ *
+ * +------+-----+---------------------------+
+ * | GPIO | Pin | Description               |
+ * +------+-----+---------------------------+
+ * | GP00 | 121 | N/C                       |
+ * | GP01 | 122 | CHA_FAN2 PWM output       |
+ * | GP02 | 123 | CHA_FAN3 PWM output       |
+ * | GP03 |   2 | N/C                       |
+ * | GP04 |   3 | CHA_FAN3 tach input       |
+ * | GP05 |   4 | CHA_FAN2 tach input       |
+ * | GP06 |   5 | PWR_FAN  tach input       |
+ * | GP07 |   6 | N/C            (SE_IFDET) |
+ * +------+-----+---------------------------+
+ * | GP10 |  14 | HDD Saver power switch    |
+ * | GP11 |  13 | Assert HDA_SDO (SIO_GP11) |
+ * | GP12 |  12 | CPU_FAN2 FON#             |
+ * | GP13 |  11 | SATA_SEL (for eSATA)      |
+ * | GP14 |  10 | N/C                       |
+ * | GP15 |   9 | N/C          (UARTP80_EN) |
+ * | GP16 |   8 | OTP for VCORE (OTE_GATE1) |
+ * | GP17 |   7 | LED_EN#                   |
+ * +------+-----+---------------------------+
+ * | GP20 |  59 | KDAT                      |
+ * | GP21 |  58 | KCLK                      |
+ * | GP22 |  57 | MDAT                      |
+ * | GP23 |  56 | MCLK                      |
+ * | GP24 |  95 | SE_DEVSLP (SATA Express)  |
+ * | GP25 |  96 | N/C            (SIO_GP25) |
+ * | GP26 |  53 | N/C                       |
+ * | GP27 |  98 | M2_2_SE_IFDET             |
+ * +------+-----+---------------------------+
+ * | GP30 |  83 | N/C           (RESETCON#) |
+ * | GP31 |  76 | BIOS_A (or SML1DAT)       |
+ * | GP32 |  75 | BIOS_B (or SML1CLK)       |
+ * | GP33 |  71 | 3VSBSW#                   |
+ * | GP34 |  55 | VCORE_OFFSET#             |
+ * | GP35 |  54 | N/C                       |
+ * | GP36 |  53 | N/C                       |
+ * | GP37 |   7 | LED_EN#                   |
+ * +------+-----+---------------------------+
+ * | GP40 |  62 | N/C             (TEST_EN) |
+ * | GP41 |  52 | N/C                       |
+ * | GP42 |  51 | WLAN1_ON/OFF#             |
+ * | GP43 |  41 | Port 80 display - DGL_0#  |
+ * | GP44 |  40 | PWR_LED gate              |
+ * | GP45 |  39 | HDD_LED gate              |
+ * | GP46 |  38 | CHA_FAN3 FON#             |
+ * | GP47 |  37 | CHA_FAN2 FON#             |
+ * +------+-----+---------------------------+
+ * | GP50 |  93 | N/C            (SUSWARN#) |
+ * | GP51 |  92 | CPU_FAN2 tach input       |
+ * | GP52 |  91 | N/C             (SUSACK#) |
+ * | GP53 |  90 | SUSWARN_5VDUAL            |
+ * | GP54 |  89 | SLP_SUS#                  |
+ * | GP55 |  88 | SLP_SUS_FET               |
+ * | GP56 |  87 | PEG12V_DET (Molex conn)   |
+ * | GP57 |  86 | PCIE4_SEL (PCIE3 / mPCIe) |
+ * +------+-----+---------------------------+
+ * | GP70 |  69 | N/C              (DSW_EN) |
+ * | GP71 |  68 | N/C                       |
+ * | GP72 |  67 | N/C                       |
+ * | GP73 |  66 | M.2 / SATA Express select |
+ * | GP74 |  79 | RESET# of long PCIe ports |
+ * | GP75 |  78 | RESET# for on-board chips |
+ * | GP76 |  77 | RESET# SATA Express / M.2 |
+ * | GP77 |  86 | HDD_LED gate              |
+ * +------+-----+---------------------------+
+ *
+ * HWM voltage inputs
+ *
+ * +------+-----+---------------------------+
+ * | Name | Pin | Voltage (resistor values) |
+ * +------+-----+---------------------------+
+ * | VIN0 | 104 | +12V         (110K / 10K) |
+ * | VIN1 | 105 | +5V           (20K / 10K) |
+ * | VIN2 | 106 | CPU_VRING                 |
+ * | VIN3 | 107 | CPU_VSA                   |
+ * | VIN4 | 111 | CPU_VCORE0                |
+ * | VIN5 | 114 | CPU_VGFX                  |
+ * | VIN6 | 115 | V_VCCIOA_LOAD             |
+ * | VIN7 | 116 | N/C                       |
+ * | VIN8 | 103 | CPU_VIO                   |
+ * +------+-----+---------------------------+
+ */
+
+void mainboard_config_superio(void)
+{
+	nuvoton_pnp_enter_conf_state(GLOBAL_DEV);
+
+	/* Select SIO pin mux states */
+	pnp_write_config(GLOBAL_DEV, 0x1b, 0xe6);
+	pnp_write_config(GLOBAL_DEV, 0x1c, 0x10);
+	pnp_write_config(GLOBAL_DEV, 0x24, 0xfc);
+	pnp_write_config(GLOBAL_DEV, 0x2a, 0x40);
+	pnp_write_config(GLOBAL_DEV, 0x2b, 0x20);
+	pnp_write_config(GLOBAL_DEV, 0x2c, 0x00);
+	pnp_write_config(GLOBAL_DEV, 0x2d, 0x02);
+
+	/* Select push-pull vs. open-drain output */
+	pnp_set_logical_device(GPIO_PP_OD_DEV);
+	pnp_write_config(GPIO_PP_OD_DEV, 0xe0, 0xfe);
+	pnp_write_config(GPIO_PP_OD_DEV, 0xe2, 0x79);
+	pnp_write_config(GPIO_PP_OD_DEV, 0xe6, 0x6f);
+
+	/* Power RAM in S3 */
+	pnp_set_logical_device(ACPI_DEV);
+	pnp_write_config(ACPI_DEV, 0xe4, 0x10);
+
+	nuvoton_pnp_exit_conf_state(GLOBAL_DEV);
+
+	nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
diff --git a/src/mainboard/asrock/z97_extreme6/data.vbt b/src/mainboard/asrock/z97_extreme6/data.vbt
new file mode 100644
index 0000000000..6a73a26626
--- /dev/null
+++ b/src/mainboard/asrock/z97_extreme6/data.vbt
diff --git a/src/mainboard/asrock/z97_extreme6/devicetree.cb b/src/mainboard/asrock/z97_extreme6/devicetree.cb
new file mode 100644
index 0000000000..2258a1bfd1
--- /dev/null
+++ b/src/mainboard/asrock/z97_extreme6/devicetree.cb
@@ -0,0 +1,130 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/haswell
+
+	# This mainboard has DVI-I
+	register "gpu_ddi_e_connected" = "1"
+
+	# This mainboard has a DP output
+	register "gpu_dp_c_hotplug" = "7"
+
+	chip cpu/intel/haswell
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
+	end
+
+	device domain 0 on
+		ops haswell_pci_domain_ops
+		subsystemid 0x1849 0x0c00 inherit
+
+		device pci 00.0 on  end		# Host bridge
+		device pci 01.0 on  end		# Bifurcated PEG: PCIE2 slot
+		device pci 01.1 on  end		# Bifurcated PEG: PCIE4 slot
+		device pci 01.2 on  end		# Bifurcated PEG: M2_1 slot
+		device pci 02.0 on  end		# iGPU
+		device pci 03.0 on  end		# Mini-HD
+
+		chip southbridge/intel/lynxpoint
+			register "gen1_dec"		= "0x000c0291"	# Super I/O HWM
+			register "sata_port_map"	= "0x3f"
+
+			device pci 14.0 on  end		# xHCI controller
+			device pci 16.0 on  end		# MEI #1
+			device pci 16.1 off end		# MEI #2
+			device pci 19.0 on  end		# Intel GbE through I218-V PHY
+			device pci 1a.0 on  end		# EHCI #2
+			device pci 1b.0 on  end		# HD Audio
+			device pci 1c.0 on  end		# RP #1: muxed M2_2 slot, SATA Express
+			device pci 1c.1 off end		# RP #2
+			device pci 1c.2 on		# RP #3: Realtek RTL8111E GbE NIC
+				device pci 00.0 on end
+			end
+			device pci 1c.3 on  end		# RP #4: ASM1184E 4-Port PCIe switch
+			device pci 1c.4 on  end		# RP #5: PCIE5 slot
+			device pci 1c.5 off end		# RP #6
+			device pci 1c.6 on  end		# RP #7: ASM1042A USB 3.0
+			device pci 1c.7 off end		# RP #8
+			device pci 1d.0 on  end		# EHCI #1
+			device pci 1f.0 on		# LPC bridge
+				chip superio/common
+					device pnp 2e.0 on
+						chip superio/nuvoton/nct6791d
+							device pnp 2e.1   off end	# Parallel
+							device pnp 2e.2   on		# UART A
+								io  0x60 = 0x03f8
+								irq 0x70 = 4
+							end
+							device pnp 2e.3   off end	# IR
+							device pnp 2e.5   on		# PS/2 Keyboard/Mouse
+								io  0x60 = 0x0060
+								io  0x62 = 0x0064
+								irq 0x70 = 1		# + Keyboard IRQ
+								irq 0x72 = 12		# + Mouse IRQ
+							end
+							device pnp 2e.6   off end	# CIR
+							device pnp 2e.7   off end	# GPIO6
+							device pnp 2e.107 on		# GPIO7
+								irq 0xe0 = 0x6f
+								irq 0xe1 = 0x10
+							end
+							device pnp 2e.207 off end	# GPIO8
+							device pnp 2e.8   off end	# WDT
+							device pnp 2e.108 off end	# GPIO0
+							device pnp 2e.308 off end	# GPIO base
+							device pnp 2e.408 off end	# WDTMEM
+							device pnp 2e.708 on		# GPIO1
+								irq 0xf0 = 0xbe
+								irq 0xf1 = 0x01
+							end
+							device pnp 2e.9   on		# GPIO2
+								irq 0xe0 = 0xff
+								irq 0xe1 = 0x00
+							end
+							device pnp 2e.109 on		# GPIO3
+								irq 0xe4 = 0x6f
+								irq 0xe5 = 0x72
+							end
+							device pnp 2e.209 on		# GPIO4
+								irq 0xf0 = 0x0f
+								irq 0xf1 = 0x00
+							end
+							device pnp 2e.309 on		# GPIO5
+								irq 0xf4 = 0xdf
+								irq 0xf5 = 0x00
+							end
+							device pnp 2e.a   on		# ACPI
+								# Power RAM in S3
+								irq 0xe4 = 0x10
+								irq 0xe5 = 0x12
+								irq 0xed = 0x01
+								irq 0xf0 = 0x30
+							end
+							device pnp 2e.b   on		# HWM, LED
+								irq 0x30 = 0xe1		# + Fan RPM sense pins
+								io  0x60 = 0x0290	# + HWM base address
+								io  0x62 = 0
+								irq 0x70 = 0
+							end
+							device pnp 2e.d   off end	# BCLK, WDT2, WDT_MEM
+							device pnp 2e.e   off end	# CIR wake-up
+							device pnp 2e.f   off end	# GPIO PP/OD
+							device pnp 2e.14  off end	# SVID, Port 80 UART
+							device pnp 2e.16  off end	# DS5
+							device pnp 2e.116 off end	# DS3
+							device pnp 2e.316 off end	# PCHDSW
+							device pnp 2e.416 off end	# DSWWOPT
+							device pnp 2e.516 on  end	# DS3OPT
+							device pnp 2e.616 off end	# DSDSS
+							device pnp 2e.716 off end	# DSPU
+						end
+					end
+				end
+				chip drivers/pc80/tpm
+					device pnp 0c31.0 on end	# TPM
+				end
+			end
+			device pci 1f.2 on  end		# SATA (AHCI)
+			device pci 1f.3 on  end		# SMBus
+			device pci 1f.5 off end		# SATA (Legacy)
+		end
+	end
+end
diff --git a/src/mainboard/asrock/z97_extreme6/dsdt.asl b/src/mainboard/asrock/z97_extreme6/dsdt.asl
new file mode 100644
index 0000000000..17c44b6523
--- /dev/null
+++ b/src/mainboard/asrock/z97_extreme6/dsdt.asl
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20141018
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include "acpi/platform.asl"
+	#include <cpu/intel/common/acpi/cpu.asl>
+	#include <southbridge/intel/common/acpi/platform.asl>
+	#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <northbridge/intel/haswell/acpi/hostbridge.asl>
+		#include <southbridge/intel/lynxpoint/acpi/pch.asl>
+	}
+}
diff --git a/src/mainboard/asrock/z97_extreme6/gma-mainboard.ads b/src/mainboard/asrock/z97_extreme6/gma-mainboard.ads
new file mode 100644
index 0000000000..cd05ae2fb8
--- /dev/null
+++ b/src/mainboard/asrock/z97_extreme6/gma-mainboard.ads
@@ -0,0 +1,19 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (DP2,     -- DP
+      HDMI1,   -- DVI-I
+      HDMI2,   -- DP
+      HDMI3,   -- HDMI
+      Analog,  -- DVI-I
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/asrock/z97_extreme6/gpio.c b/src/mainboard/asrock/z97_extreme6/gpio.c
new file mode 100644
index 0000000000..1dee18cc7e
--- /dev/null
+++ b/src/mainboard/asrock/z97_extreme6/gpio.c
@@ -0,0 +1,189 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_GPIO,
+	.gpio2 = GPIO_MODE_GPIO,
+	.gpio3 = GPIO_MODE_GPIO,
+	.gpio4 = GPIO_MODE_GPIO,
+	.gpio5 = GPIO_MODE_GPIO,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_NATIVE,
+	.gpio9 = GPIO_MODE_NATIVE,
+	.gpio10 = GPIO_MODE_NATIVE,
+	.gpio11 = GPIO_MODE_GPIO,
+	.gpio12 = GPIO_MODE_NATIVE,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_NATIVE,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_NATIVE,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_GPIO,
+	.gpio19 = GPIO_MODE_NATIVE,
+	.gpio20 = GPIO_MODE_NATIVE,
+	.gpio21 = GPIO_MODE_NATIVE,
+	.gpio22 = GPIO_MODE_NATIVE,
+	.gpio23 = GPIO_MODE_NATIVE,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_GPIO,
+	.gpio26 = GPIO_MODE_NATIVE,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_NATIVE,
+	.gpio30 = GPIO_MODE_NATIVE,
+	.gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_INPUT,
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio2 = GPIO_DIR_INPUT,
+	.gpio3 = GPIO_DIR_INPUT,
+	.gpio4 = GPIO_DIR_INPUT,
+	.gpio5 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio11 = GPIO_DIR_INPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_OUTPUT,
+	.gpio17 = GPIO_DIR_INPUT,
+	.gpio18 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_OUTPUT,
+	.gpio25 = GPIO_DIR_INPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_INPUT,
+	.gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio15 = GPIO_LEVEL_LOW,
+	.gpio24 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+	.gpio8 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio11 = GPIO_INVERT,
+	.gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_GPIO,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_GPIO,
+	.gpio36 = GPIO_MODE_NATIVE,
+	.gpio37 = GPIO_MODE_NATIVE,
+	.gpio38 = GPIO_MODE_NATIVE,
+	.gpio39 = GPIO_MODE_NATIVE,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_NATIVE,
+	.gpio43 = GPIO_MODE_NATIVE,
+	.gpio44 = GPIO_MODE_NATIVE,
+	.gpio45 = GPIO_MODE_GPIO,
+	.gpio46 = GPIO_MODE_NATIVE,
+	.gpio47 = GPIO_MODE_NATIVE,
+	.gpio48 = GPIO_MODE_NATIVE,
+	.gpio49 = GPIO_MODE_NATIVE,
+	.gpio50 = GPIO_MODE_GPIO,
+	.gpio51 = GPIO_MODE_GPIO,
+	.gpio52 = GPIO_MODE_GPIO,
+	.gpio53 = GPIO_MODE_GPIO,
+	.gpio54 = GPIO_MODE_GPIO,
+	.gpio55 = GPIO_MODE_GPIO,
+	.gpio56 = GPIO_MODE_NATIVE,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_NATIVE,
+	.gpio61 = GPIO_MODE_NATIVE,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio32 = GPIO_DIR_OUTPUT,
+	.gpio33 = GPIO_DIR_OUTPUT,
+	.gpio34 = GPIO_DIR_INPUT,
+	.gpio35 = GPIO_DIR_OUTPUT,
+	.gpio45 = GPIO_DIR_INPUT,
+	.gpio50 = GPIO_DIR_INPUT,
+	.gpio51 = GPIO_DIR_OUTPUT,
+	.gpio52 = GPIO_DIR_INPUT,
+	.gpio53 = GPIO_DIR_OUTPUT,
+	.gpio54 = GPIO_DIR_INPUT,
+	.gpio55 = GPIO_DIR_OUTPUT,
+	.gpio57 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio32 = GPIO_LEVEL_HIGH,
+	.gpio33 = GPIO_LEVEL_HIGH,
+	.gpio35 = GPIO_LEVEL_LOW,
+	.gpio51 = GPIO_LEVEL_HIGH,
+	.gpio53 = GPIO_LEVEL_HIGH,
+	.gpio55 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_NATIVE,
+	.gpio65 = GPIO_MODE_NATIVE,
+	.gpio66 = GPIO_MODE_NATIVE,
+	.gpio67 = GPIO_MODE_NATIVE,
+	.gpio68 = GPIO_MODE_GPIO,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_NATIVE,
+	.gpio71 = GPIO_MODE_NATIVE,
+	.gpio72 = GPIO_MODE_GPIO,
+	.gpio73 = GPIO_MODE_GPIO,
+	.gpio74 = GPIO_MODE_NATIVE,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio68 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio72 = GPIO_DIR_INPUT,
+	.gpio73 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+		.reset		= &pch_gpio_set3_reset,
+	},
+};
diff --git a/src/mainboard/asrock/z97_extreme6/hda_verb.c b/src/mainboard/asrock/z97_extreme6/hda_verb.c
new file mode 100644
index 0000000000..7f716965f4
--- /dev/null
+++ b/src/mainboard/asrock/z97_extreme6/hda_verb.c
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x10ec0900,	/* Codec Vendor / Device ID: Realtek ALC1150 */
+	0x18491151,	/* Subsystem ID */
+	11,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(0, 0x18491151),
+	AZALIA_PIN_CFG(0, 0x11, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x01014010),
+	AZALIA_PIN_CFG(0, 0x15, 0x01011012),
+	AZALIA_PIN_CFG(0, 0x16, 0x01016011),
+	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x01a19040),
+	AZALIA_PIN_CFG(0, 0x19, 0x02a19050),
+	AZALIA_PIN_CFG(0, 0x1a, 0x0181304f),
+	AZALIA_PIN_CFG(0, 0x1b, 0x02214020),
+	AZALIA_PIN_CFG(0, 0x1e, 0x01451130),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asrock/z97_extreme6/romstage.c b/src/mainboard/asrock/z97_extreme6/romstage.c
new file mode 100644
index 0000000000..a344dee1a5
--- /dev/null
+++ b/src/mainboard/asrock/z97_extreme6/romstage.c
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <northbridge/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/raminit.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+
+void mainboard_config_rcba(void)
+{
+}
+
+void mb_get_spd_map(struct spd_info *spdi)
+{
+	spdi->addresses[0] = 0x50;
+	spdi->addresses[1] = 0x51;
+	spdi->addresses[2] = 0x52;
+	spdi->addresses[3] = 0x53;
+}
+
+const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
+	{ 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, /* USB3_4_5   */
+	{ 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, /* USB3_4_5   */
+	{ 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, /* USB3_6_7   */
+	{ 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, /* USB3_6_7   */
+	{ 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX        }, /* ASM1074    */
+	{ 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, /* USB2_3     */
+	{ 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, /* USB2_3     */
+	{ 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, /* USB4_5     */
+	{ 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, /* USB4_5     */
+	{ 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL  }, /* USB1       */
+	{ 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE   }, /* MINI_PCIE1 */
+	{ 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP        },
+	{ 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL  }, /* Can be used if ASM1042 */
+	{ 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL  }, /* has not been installed */
+};
+
+const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
+	{ 1, USB_OC_PIN_SKIP }, /* USB3_4_5 */
+	{ 1, USB_OC_PIN_SKIP }, /* USB3_4_5 */
+	{ 1, USB_OC_PIN_SKIP }, /* USB3_6_7 */
+	{ 1, USB_OC_PIN_SKIP }, /* USB3_6_7 */
+	{ 1, USB_OC_PIN_SKIP }, /* ASM1074  */
+	{ 0, USB_OC_PIN_SKIP }, /* N/A, GbE */
+};