diff options
| author | Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> | 2024-04-29 15:14:31 +0900 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-05-06 10:36:18 +0000 |
| commit | 7f0a7f65e6704c3ce050edd79c257f010535a366 (patch) | |
| tree | 02bd95981264b2897fba13de2f7c4049314bd4ed /src | |
| parent | d145a840bf79c208e5e971dc3edae0cffd73f8cb (diff) | |
mb/google/brya/var/xol: Tune I2C5 timing parameters
Update I2C5 timing parameter values to meet I2C bus spec.
- fall_time_ns: 400 -> 200
BUG=None
BRANCH=brya
TEST=built and measure I2C5 timing parameters
Before:
tLOW : 1.88 us (spec >= 1.30)
tHIGH: 0.57 us (spec >= 0.60)
fSCL : 399.80 KHz
After:
tLOW : 1.60 us (spec >= 1.30)
tHIGH: 0.97 us (spec >= 0.60)
fSCL : 392.1 KHz
Change-Id: I386b2765410fd10b8cd711f54478fb52428de5a3
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/brya/variants/xol/overridetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/brya/variants/xol/overridetree.cb b/src/mainboard/google/brya/variants/xol/overridetree.cb index 80d15feb62..6e054c5b0e 100644 --- a/src/mainboard/google/brya/variants/xol/overridetree.cb +++ b/src/mainboard/google/brya/variants/xol/overridetree.cb @@ -132,7 +132,7 @@ chip soc/intel/alderlake .i2c[5] = { .speed = I2C_SPEED_FAST, .rise_time_ns = 650, - .fall_time_ns = 400, + .fall_time_ns = 200, .data_hold_time_ns = 50, }, }" |