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authorElyes Haouas <ehaouas@noos.fr>2024-04-30 22:38:25 +0200
committerElyes Haouas <ehaouas@noos.fr>2024-05-07 08:47:55 +0000
commit305ee06933292d7520292ee0a1910f9062e96298 (patch)
treef446a8ab80fdcc88f85fc933e88b0ae22b03165f /src
parent9580e7fba87f3e933c2fc1a654ecfcde9c8376f1 (diff)
spd.h: Move enum ddr5_module_type to ddr5.h
Move specific enum ddr5_module_type to <device/dram/ddr5.h>. Change-Id: Ie38d1e99fa46c278e60ced2d3eef29ca823d4b1d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/device/dram/spd.c1
-rw-r--r--src/include/device/dram/ddr5.h16
-rw-r--r--src/include/spd.h16
3 files changed, 17 insertions, 16 deletions
diff --git a/src/device/dram/spd.c b/src/device/dram/spd.c
index 4a1e882543..c4ccfee0ba 100644
--- a/src/device/dram/spd.c
+++ b/src/device/dram/spd.c
@@ -2,6 +2,7 @@
#include <device/dram/ddr2.h>
#include <device/dram/ddr3.h>
+#include <device/dram/ddr5.h>
#include <device/dram/spd.h>
#include <spd.h>
#include <stddef.h>
diff --git a/src/include/device/dram/ddr5.h b/src/include/device/dram/ddr5.h
index ff1604a808..37182da365 100644
--- a/src/include/device/dram/ddr5.h
+++ b/src/include/device/dram/ddr5.h
@@ -15,6 +15,22 @@
/** Maximum SPD size supported */
#define SPD_SIZE_MAX_DDR5 1024
+enum ddr5_module_type {
+ DDR5_SPD_RDIMM = 0x01,
+ DDR5_SPD_UDIMM = 0x02,
+ DDR5_SPD_SODIMM = 0x03,
+ DDR5_SPD_LRDIMM = 0x04,
+ DDR5_SPD_MINI_RDIMM = 0x05,
+ DDR5_SPD_MINI_UDIMM = 0x06,
+ DDR5_SPD_72B_SO_UDIMM = 0x08,
+ DDR5_SPD_72B_SO_RDIMM = 0x09,
+ DDR5_SPD_SOLDERED_DOWN = 0x0b,
+ DDR5_SPD_16B_SO_DIMM = 0x0c,
+ DDR5_SPD_32B_SO_RDIMM = 0x0d,
+ DDR5_SPD_1DPC = 0x0e,
+ DDR5_SPD_2DPC = 0x0f,
+};
+
/**
* Converts DDR5 clock speed in MHz to the standard reported speed in MT/s
*/
diff --git a/src/include/spd.h b/src/include/spd.h
index 2fe9f968d4..b456680bc6 100644
--- a/src/include/spd.h
+++ b/src/include/spd.h
@@ -215,22 +215,6 @@ enum ddr4_module_type {
DDR4_SPD_32B_SO_RDIMM = 0x0d,
};
-enum ddr5_module_type {
- DDR5_SPD_RDIMM = 0x01,
- DDR5_SPD_UDIMM = 0x02,
- DDR5_SPD_SODIMM = 0x03,
- DDR5_SPD_LRDIMM = 0x04,
- DDR5_SPD_MINI_RDIMM = 0x05,
- DDR5_SPD_MINI_UDIMM = 0x06,
- DDR5_SPD_72B_SO_UDIMM = 0x08,
- DDR5_SPD_72B_SO_RDIMM = 0x09,
- DDR5_SPD_SOLDERED_DOWN = 0x0b,
- DDR5_SPD_16B_SO_DIMM = 0x0c,
- DDR5_SPD_32B_SO_RDIMM = 0x0d,
- DDR5_SPD_1DPC = 0x0e,
- DDR5_SPD_2DPC = 0x0f,
-};
-
enum lpx_module_type {
LPX_SPD_LPDIMM = 0x07,
LPX_SPD_NONDIMM = 0x0e,