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MT8196 has differenet configurations from other platforms. Make
CAL_TOL_RATE and CAL_MAX_VAL as per SoC configuration in order to reuse
common/pmif_clk.c
BUG=none
TEST=emerge-corsola coreboot; emerge-geralt coreboot
Change-Id: Iefc8180e1719d9796df7457b619a8792ceb762b2
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84771
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This enables SOC_INTEL_DEBUG_CONSENT to set PlatformDebugOption
to Trace Ready to have the safe configurations for Panther Lake
ES SoC.
This safe configuration will be removed once the feature is fully
verified and safe to be set to the default value.
BUG=b:373915085
TEST=Build fatcat and check the platform boots without an issue.
Change-Id: I1eaabcb2e2aaff16ee4e64d1c7709b229de18459
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84823
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
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Fix the following error when including device/pciexp.h
src/include/device/pciexp.h: In function 'pciexp_is_downstream_port':
src/include/device/pciexp.h:42:24: error: 'PCI_EXP_TYPE_ROOT_PORT' undeclared (first use in this function)
42 | return type == PCI_EXP_TYPE_ROOT_PORT ||
by including pci_def.h.
Change-Id: Idfd36301a5e766bbe97c93afef88c97507a4c4dc
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84791
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adjust the DSM to return 0x00 (unsupported) when no reset gpio
is passed to the driver. Leave the _RST method to comply with
the ACPI specification but omit the BTRT method as it won't do
anything.
Change-Id: I9f8e98fb4f5a22b2f7617b131a3d71cf90f5bc80
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
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If project set configure_ext_fivr = 0 will cause
PchFivrVccstIccMaxControl do not set correctly.
BUG=b:361831628
TEST=Verified on Teliks360 that affected DUTs.
Change-Id: I816de9c0c507aad3b73ab29e9f72048704f4662d
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84812
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
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Alder Lake, Meteor Lake and Panther Lake use the effective way size
when setting up the Enhanced No-Eviction Mode (cf.
`INTEL_CAR_ENEM_USE_EFFECTIVE_WAY_SIZE').
BUG=b:360332771
TEST=Verified on PTL Intel reference platform
Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521b
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83947
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
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On Alder Lake, Meteor Lake and Panther Lake platforms the way size to
consider for NEM+ computation is the effective way size.
On Alder Lake, the External Design Specification #627270 "3.5.2
No-Eviction Mode (NEM) Sizes" provides a way to compute the effective
way size by reading the number of CBO. Unfortunately, reading the
number of CBO is not possible on Meteor Lake and Panther
Lake. Therefore, we instead compute the effective way size as the
biggest of power of two of the way size which works across all three
platforms.
The Kconfig `INTEL_CAR_ENEM_USE_EFFECTIVE_WAY_SIZE' is introduced to
control this behavior.
The issue addressed by this commit can be observed with the following
experiment: using a 18 MB LLC SKU, set `DCACHE_RAM_SIZE` to
0x400000 (4 MB).
The number of ways that used to be computed is round(0x400000 /
0x180000) = round(2.66) = 3. 3 ways were mapped to cover the 0x400000
NEM+ region. When the bootblock code accesses memory between 3 MB and
4 MB, the core would raise a page fault exception.
The right computation is: 0x400000 / eff_way_size(0x180000) = 4. 4
ways needs to be mapped to cover the entire 0x400000 NEM+ region.
BUG=b:360332771
TEST=Verified on PTL Intel reference platform
Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521c
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This disables C1 state auto-demotion to run the coreboot with
Panther Lake ES SoC without an issue.
This configuration will be remove later once the related features
are fully verified.
BUG=b:373915085
TEST=Build fatcat and check the platform boots without an issue.
Change-Id: I384dba2918cfd04deb90284513c204fa8c21094b
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84767
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
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There is no ACPI power resource for LTE module Rolling RW101R-GL,
therefore implement the power sequence of power-on, power-off, and
reset timing from GPIO init, bootstate init callbacks, and smihandler
function.
BUG=b:368450447
BRANCH=None
TEST= Build firmware and verify on jubilant with LTE:RW101R-GL.
Measure the power on, power off, and reset timing.
Run warm boot, cold boot and suspend/resume to make sure
WWAN devcie is workable.
Change-Id: I4a205e3db777c7c225d31b6cc802883fd7167089
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Update jubilant CPU PL4 from 9 watt to 14 watt for critical battery
boot. The maximum peak power is set at 14 watt which is 45W multiplied
by 32% efficiency.
Overriding power limits for AC power without battery:
PL1 (15000, 18000)
PL2 (41000, 41000)
PL4 (14)
BUG=b:364441688
BRANCH=None
TEST=Able to successfully boot on jubilant SKU1 and SKU2 with AC only.
Test on AC 65W and 45W w/o battery, and check PL4 values from log.
Change-Id: Id1e58797206a61d241f48b057b304e05c9c323d9
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84784
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add wifi PCIe hosts M.2 E-key WLAN to fulfill
drawman_jsl_schematic_20200528.
BUG=None
BRANCH=firmware-dedede-13606.B
TEST=emerge-dedede coreboot chromeos-bootimage
Change-Id: If414ff1941d2d70c5f0444ac58b228ed5c95303a
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7c5477bbc248a21e21f3a640bdb81304a1bce38c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Add a new Rauru follower 'Navi'.
BUG=b:341210522
TEST=emerge-cherry coreboot
Change-Id: Ia2a6c1c09b3cedc0ef7f51ec93fdabf2c07c8885
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84694
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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NAU8318 supports beep function via GPIO control. Configure the
GPIO pins and pass them to the payload.
BUG=b:343143718
TEST=Verify beep function through CLI in depthcharge successfully.
We can test with:
firmware-shell: badusbbeep
firmware-shell: devbeep
Change-Id: I79277bc1947dab517dea5aba583c5b4e0ac81bc4
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84693
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There is no powering-on control in the fingerprint kernel driver. The
fingerprint team of ChromeOS suggests powering-on FP MCU in the FW.
Follow trogdor to pull down FP_RST_1V8_S3_L, AP_FP_FW_UP_STRAP,
EN_PWR_FP and pull up EN_PWR_FP in ramstage for power rail to be stable.
BUG=b:340401582
TEST=measure waveform and the fingerprint works on ChromeOS
Change-Id: I05600d90fdf922faeb778a36d8a08f68c1bb4125
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84692
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
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Configure GPIO EINT28 (XHCI_INIT_DONE) as output, so that payloads
(for example depthcharge) can assert it to notify EC to enable USB VBUS.
BUG=b:317009620
TEST=emerge-rauru coreboot
Change-Id: I5950974435b56997626886b16d371cd8e6472e3c
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84691
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
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N-1 IBL (Integrated Boot Logic) codes are initially forked from
EBG (Emmitsburg PCH) codes (src/soc/intel/xeon_sp/ebg). N-1 IBL
codes are a set of stub codes to fulfill build sanity check for GNR
SoC and CRB codes before the formal codes are published.
Change-Id: I6bd5a2ed973ff91750c5ed1f9a57d30e41d8b97e
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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FW_CONFIG ids
Based on Gallida360 design, we add two new options for WIFI_SAR_ID:
- WIFI_SAR_ID_INTEL_CONVERTIBLE 2
- WIFI_SAR_ID_INTEL_CLAMSHELL 3
BUG=b:372354703
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I1b58c4f572d4dbcb269d38485664ddc51e378e5e
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84779
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Create the francka variant of the fatcat reference board.
BUG=b:370666276
TEST=util/abuild/abuild -p none -t google/fatcat -x -a
make sure the build includes GOOGLE_FRANCKA
Change-Id: I372f445f7007d0d33020545a8febbce27c260e41
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84769
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add the GPIO pad configuration to be performed before memory is set up
along with the relevant devices definition.
This patch includes:
- FW config for pre-mem GPIO PAD configuration
- Add overridetree changes used by pre-mem FW config
BUG=b:348678529
TEST=Boot on Google Fatcat board. Note this cannot be tested by itself
directly. Test with CL:84408, set the proper CBI fw_config bit(s) and
check that the corresponding GPIO PADs are configured as expected value
accordingly.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Iac1f637c21a9818512b224dc4cbe4a75dbc516ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84718
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
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Create the telith variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0)
BUG=372506691
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_TELITH
Change-Id: I4971b9691d3dd293ca640795967c36472afef9c9
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84759
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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Add support for Arm Neoverse N2 Reference design.
Based on Arm Neoverse N2 reference design
Revision: Release D
TEST=Build Arm Neoverse N2 & make sure there is no error.
Change-Id: I17908d3ce773d4a88924bafb1d0e9e2a043c7fbc
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Add the BMC and all PCIe slots that the board implements.
There are 32 RSSDs and 2 M.2 slots.
Change-Id: Id7d72990d6997d1e8b9ce75477ce3dc571c99839
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add slot types found in SMBIOS spec 3.8.0.
Change-Id: I705529efcbf2add420fb6f4a720ec33444d46efa
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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TEST=Build & boot in IBM SBP1 system. Verified the settings are effective in FSP logs.
Change-Id: I4341ead89a2683f64c834a6981ba316fcfef4f9a
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84741
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The current panel brightness is only 360 nits. Adjust the power and
gamma to optimize the panel brightness. The brightness after adjustment
is 390 nits.
BUG=b:320892589
TEST=boot ciri with IVO_T109NW41 panel and see firmware screen
BRANCH=geralt
Change-Id: I760c37bf915bb40ad2efa7c947034cb168938f2a
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84758
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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The spec tells us to clear the busy bit manually after a timeout. Do
that and wait immediately, to detect further issues early. Also fix
some related comments and prints: Failures shouldn't be debug messa-
ges. And we are talking to the PIO interface of the controller, not
the codec. So this was never about the codec being ready.
Change-Id: I4b737f8259157c01bfcd9e6631cc15d39c653d06
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83592
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1. Add STYLUS fw_config setting.
2. Enable stylus device settings.
3. Disable the stylus GPIO pins based on fw_config.
BUG=b:364798563
BRANCH=firmware-nissa-15217.B
TEST=1. emerge-nissa coreboot
2. Confirm command evtest for stylus PRP0001:00 and workable.
Change-Id: Ifa8555eed1c31e9342a50a735fc618106f26d41a
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84713
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Linux has never supported this feature, and according to our FAE, the
Windows driver dropped support for it in 2022 so remove it.
Change-Id: I4f0b6108bb5db657490a8b9395bb99378fc63c4d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
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Add support for RTD3 for Intel Bluetooth. This is done by
controlling the enable GPIO (GPP_VGPIO_0 for most SOCs) that
exists on all wireless cards since Jefferson Peak.
The exception is GalePeak2, which uses VSEC and this driver doesn't
support that.
Change-Id: Ibea97ab0ae0a9f1eb6aaca43d831bb4ce7bdc02e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
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Print a warning when the FSP UPD for CNVi Audio Offload is enabled
without the corresponding USB ACPI driver being enabled.
Throw an error when the USB ACPI driver is enabled without the
corresponding UPD being enabled.
Change-Id: I449c43998dd379dc68a33db47a2fe51cfe5cda2f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Add AOLD Method, which returns an integer based on
whether Audio Offload is enabled. Leave the existing
control of Audio Offload in `soc/soc_chip.h`. Add
`cnvi_bt_audio_offload` in the USB ACPI `chip.h` to
control the aforementioned return value.
The value in `soc/soc_chip.h` and `chip.h` should
match.
Change-Id: Idb804fb1cf0edef4a98479a6261ca68255dbf075
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84134
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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nullptr was introduced in C11 spec and gcc 4.7.
https://en.cppreference.com/w/cpp/language/nullptr
https://stackoverflow.com/questions/16256586/how-to-enable-c11-on-later-versions-of-gcc
coreboot switched to GCC 4.7.2 on October 25, 2021, prior to coreboot v4.1.
https://review.coreboot.org/c/coreboot/+/1609
GCC-13 implemented nullptr constant: https://www.open-std.org/jtc1/sc22/wg14/www/docs/n3042.htm
So use it insted of NULL macro.
Change-Id: I7d47e692a33d739345a81f589d4329a31beeb8c5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83860
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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After CB:76315, TPM_RDRESP_NEED_DELAY, whose historical mission has
ended, could be removed.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I51e046fb738d2ff7a23225739de62a1a7780bc1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
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TPM_RDRESP_NEED_DELAY was introduced in 2018 in CB:25322 after
observing errors with SLB9635 by Infineon. It has been confirmed
also SLB9670 and SLB9672 require a fix or delay here.
Presumably, prior to CB:4388 SLB9635 did not have this problem,
as this particular TPM shipped with samsung/lumpy Chromebook since
2011. In CB:4388 the code changed from polling the status register
(+burst_count) using a 32bit read to separated 8bit reads.
So far, experiments on samsung/lumpy and SLB9635 indicate that
it would be sufficient to add a single tpm_read_status() call
to see TIS_STS_DATA_AVAILABLE as set at the time of evaluating
the loop exit condition.
Change-Id: If5c3e93c7946ebf8226f7bba47b38253f6920c61
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Co-authored-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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In order to fit the specification, change gpio setting for touch panel
and wwan.
Change items:
1. wwan : Add WWAN_RST_L to 0. And we want WWAN_EN to pull high more
early than WWAN_RST_L, so add WWAN_EN to 1 in romstage stage.
2. touch panel : First we add EN_PP3300_TCHSCR and USI_RST_L to 0 to
init status. And we want EN_PP3300_TCHSCR to pull high more early than
USI_RST_L so delete USI_RST_L pull high in romstage.
BUG=b:357764679
Test=emerge-nissa coreboot
Change-Id: I0a07ea8e2bf3d165dcebd89c4c564f157d9d4846
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84668
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Reduce gspi speed from 10 MHz to 9 MHz, because Raptor
Lake Refresh platform GSPI supports max frequency 9 MHz.
BUG=b:342932183
TEST=emerge-brox coreboot
Change-Id: If5b7885d95cfe21ec71cc37e6d72419935b0844f
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84708
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Setting devices to unprovisioned allows us to perform
functional testing without having to rewrite the fw config
during the SMT phase of factory production.
BUG=None
TEST=Build lotso firmware and boot to OS when fw_config is
unprovisioned and ensure all devices are enable.
Change-Id: I3b8285ce335ee0f3595d184eb0921f697bdbd0c2
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84714
Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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GNR/SRF supports up to 18 logical IIO stacks. Revise IIO domain
ACPI name encoding in below form to support GNR/SRF,
prefix (16 bit) | socket (3-bit) | stack (5-bit)
Change-Id: I6f4c3c22980f2797dd47c8e0d684e0a3175030b7
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Since the Kconfig default for boolean options is already 'n', there's no
need to add that default to the option. Still kept the 'default n' for
the 3 options that result in fuses inside the SoC to be burnt
(PERFORM_RPMC_PROVISIONING, PERFORM_SPL_FUSING and
PSP_PLATFORM_SECURE_BOOT) to point out the fact that that's not selected
by default more clearly.
Change-Id: I55971f1f130d8ec23d4572a215008d9465e1520a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Add the data structures used for the command buffers for the PSP SMI
commands to increment and request the state of the monotonic counters in
the SPI flash. These data structures are specific to the PSP SMI mailbox
interface and not the data structures from the RPMC specification. The
AGESA code was used as a reference.
Change-Id: I8bc8ff4cf9b7ebd0e034f040dde2db8385bb8f79
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
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PEG0 should be set to PCI_INT_D, not PCI_INT_A. This fixes:
pcieport 0000:00:06.0: can't derive routing for PCI INT D
pcieport 0000:00:06.0: PCI INT D: not connected
PEG1 should also be PCI_INT_B.
Tested on `starbook_adl` with Ubuntu 24.04 by running SSD
benchmark with GNOME disks and suspend.
Change-Id: I0f37bb9ac8572d7335084a20fceca6977a491498
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84619
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Rather than hardcoded values, simply change these to -25% of the
defaults for Power Saving, and +25% for Performance.
Change-Id: I16aeb4d5dc25a3f240a775509276c9d3189e9699
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84661
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Windows driver only checks PCI0, so move the window accordingly
so that it can be used.
Tested on `starlite_adl` by booting Windows 11 installation medium.
Prior to this patch, it would flag that the security requirements
were not met - it now happily installs.
Change-Id: I5d0d062502af99104690f9a9affec09f42b5bc71
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84663
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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This pin is used by the DisplayPort connector for Hot Plug.
Change-Id: I3c63e2e3e168a915daee81afd6a9084a3f01b986
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84662
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Override the PL4 to the maximum power the battery can provide
without a charger connected to prevent drawing too much power.
Change-Id: I2945e1ed0f33ab6692631e327c1457980b353c06
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84660
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The wrong definition was used, so the code had no effect.
The ID for the processor used is `b06e0`.
Change-Id: I36e13074a77b93871c1d86664e35a33afe39a402
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84659
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Some boards use hubs for devices, so correct the ACPI configuration
for these ports. Also, add more information to the comments for the
ports.
Change-Id: I8472130aba8e777557cf68280fa0058dbeb77df9
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
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Change-Id: I6fb228bab06b050ac1a51de46ffe5c0d3d80adfb
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
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Make the I2C speed user configurable from CMOS. Both the touchscreen
and accelerometer support running at 100MHz or 400MHz. They perform
better at 400MHz but use more power - this patch lets the user choose.
Change-Id: Ia1b08d7ec6212418bb95d0a52077f01c930f8830
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
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Change-Id: Ibe47f242ce12fc4906baeee89393a34a56eaca76
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83881
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This method is used to provision the CNVi, and ensure
that it is in the correct state.
Intel document #559910 details this.
Change-Id: Id8a36a09c7beaf3ba8b29d3276bd9dc59420dab5
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83713
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This method is used to limit frequencies on CNVi.
Intel document #559910 details this.
Change-Id: Idc4c35e71076fd31786212995472bb8d58c961de
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83712
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
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Only the _PRR method is used here, however, _PS0, _PS3 and _DSW must
exist to avoid a BSOD on Windows.
Change-Id: Ib4a1a8a76ce74b991a3e8686e9594c2c2b145a39
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
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Add a general purpose handle to allow CNVi to be notified
of state changes.
Intel document #559910 details this.
Change-Id: I36c98c525c99fb2b7b5ebd8b0e392e6626e97290
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83710
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a _PRR method that the OS can use to reset the wireless.
This is only used for integrated solutions and depends on the
CNMT Mutex that's created with `drivers/usb/acpi`. Whilst new
ACPI is added, the behavior of existing boards won't be
changed unless they configure the accompanying Bluetooth device.
Intel document #559910 details this.
Change-Id: I25e8462780badcad88b13052a6eb282c83af5def
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
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All CNVi modules, integrated or dedicated only support D3 Hot
so add _S0W to limit the sleep state.
Intel document #559910 details this.
Change-Id: I1541cebc022adc927a9cd883500320e9ef82359f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
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These fields are used to monitor events on CNVi.
Intel document #559910 details this.
Change-Id: I3c1efc039e929ad1eeb8a0dd7c176e370e502e0c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83709
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
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The CNVi driver is relatively basic in coreboot and most
noticeably, recent Linux kernels flag that lack of a _PRR
method, which is used to reset WiFi and Bluetooth.
This patch series adds methods recommended by Intel in
document #559910.
This patch defines an OpRegion for CNVi, for both
integrated and dedicated solutions.
Change-Id: Idd2ff93fb65c40f656804d96966e1881202ccb56
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Hook up CNVi Bluetooth UPDs to the devicetree. Set CnviBtCore to
`true` so the current behaviour is not changed.
Change-Id: Ic5640c23af3ce30498be814a6d7ce56988653b25
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84596
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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None of these boards support or use S0ix so c6dram isn't needed, so
disable it.
Change-Id: I8124899a1f7ce20442f28919f7315ee7e52355e5
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84632
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There is only 1 Type-C port, the rest are Type-A.
Tested on Linux by verified the correct names are shown in dmesg.
Change-Id: Iaf5a29f3d25f299658116fa61ae488775e2b70a2
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84642
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Port 2 is a hub, used for the internal keyboard and the card reader.
Adjust this to a hub.
Change-Id: I3a9b9e6803934291b46fb502ff1b3b088c047703
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
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Change-Id: I8ea01c21ec03c11e9599684dbe51d103c07c172a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84640
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The existing GPIO configuration was IRQ heavy; tweak this to reduce
the number of interrupts.
Change-Id: I6d23bea5ec12e86a3606186edb29636540283fa3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84639
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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A debug configuration was left in the patch when it was uploaded,
remove this.
Change-Id: I3ab8137d3841dfa200750a97969af5dca477d7e2
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
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The wireless GPIOs don't need to be configured in the bootblock,
so set them up in ramstage.
Change-Id: Iab399884edde29891e66ffc097cf6f3dff71c351
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84637
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add options to disable the card reader and fingerprint reader.
Change-Id: Iee985aa2db3da5c2d393b8dc2dc722e990c43272
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84631
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The first table from the chapter 4.1 'OP1/OP2 Command Definition: No
Address Phase' of the JEDEC standard JESD260 (Replay Protected Monotonic
Counter (RPMC) for Serial Flash Devices) in the version from April 2021
was used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0050aea6cdc537122bae63fddb417dd9f6b75a02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84703
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In the case where the x86 owns the SPI controller and the RPMC feature
is used, the PSP will send an SMI to the x86 side for it to send the
RPMC increment monotonic counter and RPMC request monotonic counter
commands to the SPI flash and return the result to the PSP. Add stubs
as handlers for those two PSP SMI commands.
Change-Id: If6091d2b0002f817922cac4cba373f0f981b646e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84702
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ana Cabral
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STMicro first moved their SPI NOR flash business to Numonyx which was a
joint venture with Intel which later got sold to Micron, so add a
comment to the VENDOR_ID_STMICRO JEDEC manufacturer ID define and
mention all 3 companies that have sold SPI NOR flash chips using this
manufacturer ID to the Kconfig help text of SPI_FLASH_STMICRO.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7886396d8f0a9766f568a221c0b5ade02489060b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84018
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Change-Id: I50ee0adc2f70ad593815783078145cc4b494f70c
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77732
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1.Add WFC fw_config setting.
2.Used USB2 Port7 for WFC.
BUG=b:365184481
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: Ie5dcf5ed8f72a4bdf4c2c7fc63bf94dc7b869eef
Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84685
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This change updates the EC event parameters for Ovis, a Chromebox.
As a result, several existing parameters like LID, battery, and AC
connect/disconnect are no longer applicable to the Chromebox design.
TEST=Successfully built and booted google/ovis.
Change-Id: I2b9a6970a07624e16b4483907b8d2b77c04d535c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84671
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Meteor Lake handles a misconfigured devicetree better than Alder Lake
and Tiger Lake; it throws a warning and corrects the FSP config rather
than asserting.
Copy that behavior to Alder Lake and Tiger Lake.
Change-Id: Ifd768fc31a0a6ef2fa0ae7e890cf0b47a9968d30
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84647
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
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Since version 6.6, Linux has warned about the lack of a
_PRR Method being available for Intel Bluetooth. Add one
that follows the recommendations from Intel in their
connectivity integrated guide, that uses the reset
delay set by the DSM.
Change-Id: I9c7fd286e8630d77d79d1d7cd113ce3a3d3d0fe3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84145
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Intel Bluetooth driver can be combined with either CNVi, or
full PCI wireless cards such as the AX210. Move it to the USB
code so it can be used by either or.
Change-Id: Ib456b1870501182b2d8788e5d53bbf4d7981f91b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84627
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The code for Intel Bluetooth is unrelated to all other devices, and
needs to grow in size - move it to another file.
Change-Id: I65ccb9f2fd95b07fa63866485920539adc474873
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84625
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Commit 8cfe1b3302ff (mb/google/brox/jubilant: Modify FP IRQ pin to GPP_D13): CB:84124, changes the fingerprint IRQ pin from GPP_F15 to GPP_D13, but forgot to update the pin in the array fp_disable_pads.
Hence update fp_disable_pads configuration to include that GPIO.
BUG=None
TEST= build firmware
$ emerge-brox coreboot
Change-Id: Iee4c3d3f000f884ca8a77ae8c72ccbeebfeb865f
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84545
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
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Add helper function to allow platform to fill gicc parameters for use in
ACPI table.
Change-Id: Ibd4c52a5482707fae8aa1b8b21fdc6bb5f4b45c2
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79973
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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FSP for Comet Lake S allows one to configure 16 USB2 (PortUsb20Enable
array) ports and 10 USB3 (PortUsb30Enable array) ports [1, 2].
[1] src/soc/intel/cannonlake/chip.h
[2] 3rdparty/fsp/CometLakeFspBinPkg/CometLakeS/Include/FspsUpd.h
Change-Id: Ie69543f335be1a69cf0c068335c2e17eebf4c6a9
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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These aren't used so remove them.
Change-Id: I0e8ef5e3c992f8ff51e4755b80379acfe0361e99
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84630
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All newer Intel SoCs use `s_cfg` as the variable name for a FSP_S_CONFIG
struct pointer, so use that for CNL as well to avoid copy/paste errors
when applying changes across SoCs which touch the FSP_S_CONFIG struct.
Change-Id: I5eadb77f312ad6ad1072bc02adf98d97b1940236
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84653
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change updates SoundWire driver to support ALC721 audio codec
based on config flag.
reference datasheet: Realtek ALC721-VA0-CG Rev. 0.34
BUG=b:368495490
TEST=This driver was tested on Intel RVP with Add-on ALC721 codec card
by testing soundcard binding/devices are detected and check for audio
playback.
Change-Id: I1022ee91b16374d0d4d07e5198226595d61403a6
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Signed-off-by: Naveen M <naveen.m@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This change removes individual conditional blocks for specific ALC
codec models and introduces a common name for the entire ALC 7 Series
configuration.
TEST=Build and test with DRIVERS_SOUNDWIRE_ALC_BASE_7XX.
Change-Id: Ib7c33351207df472cd11243244063b007c24d9bf
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Use the config_of_soc macro, which resolves to a direct pointer to the
chip config, instead of the chip_info member of __pci_0_00_0 to obtain
the same address.
Change-Id: If265819613727853d0f96dc6bb95ba71a2cfeeb1
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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As per commit 865173153760 ("sconfig: Move config_of_soc from device.h
to static.h"), sources that require access to the devicetree should
directly include static.h so that it can be removed from device.h,
eliminating unnecessary dependencies on static.h for files that only
need the types and function declarations in device.h.
Change-Id: Ia793666fda47678764fd33891fddb4aecf207bd4
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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As per commit 865173153760 ("sconfig: Move config_of_soc from device.h
to static.h"), sources that require access to the devicetree should
directly include static.h so that it can be removed from device.h,
eliminating unnecessary dependencies on static.h for files that only
need the types and function declarations in device.h.
Change-Id: I83c3e5db85b98196c465146ba8e3481041d2f7eb
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84589
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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As per commit 865173153760 ("sconfig: Move config_of_soc from device.h
to static.h"), sources that require access to the devicetree should
directly include static.h so that it can be removed from device.h,
eliminating unnecessary dependencies on static.h for files that only
need the types and function declarations in device.h.
Change-Id: I03e42689487c6d63436d9c2945558073aae87cd1
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84586
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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As per commit 865173153760 ("sconfig: Move config_of_soc from device.h
to static.h"), sources that require access to the devicetree should
directly include static.h so that it can be removed from device.h,
eliminating unnecessary dependencies on static.h for files that only
need the types and function declarations in device.h.
Change-Id: Iac8063d2021af83203be8a10b2962c9fb3dd106a
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Hook up PCIEXP_CLK_PM, PCIEXP_ASPM and PCIEXP_L1_SUBSTATE to the
option API.
This provides users an easy way to disable power saving options
that can limit performance.
Change-Id: I2b06a7c734a4fd4073e86c668742ee35e1d79956
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81906
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For more than 2 years the option has been unconfigurable.
Since no one seems to have fixed that, the options seems to be
not needed by anyone. So instead of making it configurable now,
we can just as well remove it.
Change-Id: I4055d497c7c23e148d2a09f216c7b910a9b3ea9b
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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This patch adds "fatcatnuvo" and "fatcatite" boards to the fatcat
Kconfig.
BUG=b:369728249
TEST=Able to build fatcat/fatcatnuvo/fatcatite and verify the correct
configs selected in coreboot.config
Change-Id: Ice3f1d711426cb356c399de6390fef6f0e6bc748
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84648
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1.Add AUDIO fw_config setting.
2.Add audio codec ALC5650 related settings for Gallida360 project.
BUG=b:364798053
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I3761ca6d4cad18c74f5e1a056f0cb465dc4ac3ea
Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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FSP-S UPDs are programmed according to the configuration (Kconfig and
device tree) in ramstage.
BUG=348678529
TEST=Hardware is programmed as desired and Intel Panther Lake
reference board boots to UI.
Change-Id: Iea26d962748116fa84afdb4afcba1098a64b6989
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84552
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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The new names include the `AUDIO_` prefix to clearly indicate that
they are audio-related options.
TEST=Able to build google/fatcat w/o any functional impact.
Change-Id: Ia651c19f02423ee214a31168e2bd809e097ce8c2
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
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use TOUCHSCREEN_THC_I2C instead of TOUCHSCREEN_THC0_I2C
BUG=b:348678529
TEST=Able to build google/fatcat
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I689dd72a925c76ca6c2c9a941f4857daae20c943
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84652
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
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BUG=b:348678529
TEST=Boot google fatcat board till FSP memory training
Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d52
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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BUG=b:348678529
TEST=Able to build google/fatcat.
Change-Id: I4061b9b4c1e515e8c078c67f30f29eee87b84a66
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84645
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
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Remove TODO after checking the addresses are still valid.
source:
PPR 57254 Rev 1.59 Table "Address Space Mapping under APB BUS"
Change-Id: If282ce5687b8a2bdae03ebfc5a37fe5b8b17647a
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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