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2024-05-15cpu/x86/pae/pgtbl.c: remove dead paging_identity_map_addr()Krystian Hebel
This function had roughly the same use (except PAT) as part of memset_pae(), however the latter is able to make use of PAE and map physical memory located above 4 GB. Remove paging_identity_map_addr() to avoid semi-duplicated code. The function has been unused since CB:26745. Change-Id: I7a4ebd84a6f5d222c3b2c6c6e3d26d6464cf01b8 Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82248 Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-15mb/amd/birman: add function to update MPIO config in devicetreeFelix Held
Phoenix 2 has less PCIe lanes than Phoenix, so some of the lane end numbers need to be adjusted to take that into account. When the Kconfig options WLAN01 or WWAN01 are set, either the WLAN or the WWAN card uses both PICe lanes that are available for those two devices, so the MPIO descriptor information the devicetree needs to be updated accordingly and the bridge to the PCIe port that doesn't have any lane left needs to be disabled. Two other PCIe devices will be disabled when the corresponding Kconfig options ENABLE_EVAL_CARD and DISABLE_DT_M2 have the value that results in the device being disabled via some GPIO driven by the EC. Since the code is specific to the openSIL case, only include it in the build in the CONFIG_BOARD_AMD_BIRMAN_PHOENIX_OPENSIL case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I23c14cc03980ea1e39f7e5aec551b975c237e487 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-05-15mb/amd/birman/devicetree_phoenix_opensil: add stub MPIO chipsFelix Held
Add the stub MPIO chips that contain the PCIe engine configuration for the external PCIe interfaces to the devicetree. Birman's port_descriptors_phoenix.c was used as a reference. The static configuration in the devicetree assumes that the default WLAN0_WWAN0 is selected; for the other cases we'll still need to fix up things accordingly in the mutable devicetree. The WLAN01 and WWAN01 cases still need to be handled in a follow-up patch. Since openSIL currently doesn't use the info from the gpio_group struct element, but deasserts both PCIe reset pins GPIO 26 and 27, the gpio_group isn't specified in the chip configuration in the devicetree. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icabe60322d46c1195284dd77ec39f9d143e3d2cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/81101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-05-15mb/google/brya: Create orisa variantEricKY Cheng
Create the orisa variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:337178014 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_ORISA Change-Id: I0cd8d763ffd8864b455a7f8909e95f6aee8bb23e Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-14soc/intel/xeon_sp: Add Granite Rapids initial codesShuo Liu
coreboot GNR (Granite Rapids) is a FSP 2.4 based, no-PCH, single IO-APIC Xeon-SP platform. The same set of codes is also used for SRF (Sierra Forest) SoC. This patch initially sets the code set up as a build target with Granite Rapids N-1 FSP (src/vc/intel/fsp/fsp2_0/graniterapids). 1. All register definitions are forked from SPR (Sapphire Rapids) and EBG (Emmitsburg PCH)'s codes are reused. 2. src/soc/intel/xeon_sp/chip_gen6.c is newly added as chip common codes for 6th Gen Xeon-SP SoC (Granite Rapids) and later. Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Signed-off-by: Shuo Liu <shuo.liu@intel.com> Co-authored-by: Gang Chen <gang.c.chen@intel.com> Co-authored-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-05-14soc/intel/common: Add RPL tracehub supportAshish Kumar Mishra
Add PCI ID for RPL tracehub and update the PCI ID in the pci_device_ids[] in tracehub.c. Reference: Raptor Lake External Design Specification Volume 1 (640555) BUG=None TEST=Verified on brox Change-Id: I5d5c6c8ff44bcb5a7bbbd3e27a1577c169ecd6a9 Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-05-14soc/intel/common: Add Panther Lake DIDsSaurabh Mishra
Reference: Panther Lake External Design Specification Volume 0.51 (815002) BUG=b:329787286 TEST=verified on Panther Lake Simics Platform. Change-Id: I941d6e1c8a697234b8e64a2523e60587897d7f7a Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81848 Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-14soc/intel: Add Panther Lake PCIE device IDsSaurabh Mishra
Add Panther Lake specific CPU and PCIE device IDs Reference: Panther Lake External Design Specification Volume 0.51 (815002) BUG=b:329787286 TEST=verified on Panther Lake Simics Platform. Change-Id: I82f47b6077e28a01f34c59b7e7697323b3d5f990 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81849 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-14soc/intel/common: Add Lunar Lake IAA and TBTRP3 device IDsSaurabh Mishra
Reference: Lunar Lake External Design Specification Volume 1 (734362) BUG=b:329787286 TEST=verified on Lunar Lake RVP board (lnlrvp). Change-Id: I92b65c946682387cbb841d558c6f0a7cb0fcd4ac Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81850 Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-14mb/google/nissa/var/glassway: Set VccIn Aux Imon IccMax to 25 AFrank Chu
Iccmax of VccIn_Aux is 25A with MBVR design. BUG=b:330117043 BRANCH=firmware-nissa-15217.B TEST=Local build successfully and boot to OOBE normally. Change-Id: I105dc9df53c624fd7fc697408a1097e023a3cd68 Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81445 Reviewed-by: Simon Yang <simon1.yang@intel.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-14mb/google/nissa/var/quandiso: Add stop pin for G2 touchscreenRobert Chen
Add stop pin control for G2 touchscreen refer to G7500_Datasheet_Ver.1.2. BUG=b:335803573 TEST=build and verified touchscreen works normally Change-Id: I4f085c67c0cdb8b9ca3ff03993fda69cca6319ef Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82254 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-14mb/google/brox/var/greenbayupoc: Add vbt from broxEren Peng
Copy the data.vbt from brox to greenbayupoc BUG=b:326413034 TEST=emerge-brox coreboot chromeos-bootimage, flash and boot on DUT Change-Id: I1e8101519ab2ecbb4654c20485fbe83c90656e4d Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82108 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-14mb/google/brox/var/greenbayupoc: Update devicetree and gpio settingsEren Peng
Based on latest schematics GREENBAY_0412.SCH update the gpio and devicetree settings. BUG=b:326413034 TEST=emerge-brox coreboot chromeos-bootimage, flash and boot on DUT Cq-Depend:chrome-internal:7218819 Change-Id: I59f25b8abb7dd8a2dff7ff567b231bddc9db8455 Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-05-14arch/x86: Remove unused `protected_mode_jump` APISubrata Banik
This patch removes all instances of the `protected_mode_jump` API and its associated header file. The API is no longer used by any code within the tree. BUG=b:332759882 TEST=Built and booted 64-bit coreboot with 32-bit payload successfully. Change-Id: I3eb31b09c92512338ccc540f60289960bd6bf439 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82372 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-14x86: Switch to protected_mode_call_1arg for correct argument passingSubrata Banik
The payload execution process has been updated to utilize protected_mode_call_1arg in order to guarantee proper handling of function parameters. The previous use of protected_mode_jump with a "jmp" instruction did not allow for proper stack setup for argument passing, as the calling convention was not aligned with the System V ABI calling convention. This patch ensures that calling into the libpayload entry point using protected mode is now aligned with the System V ABI calling convention. This resolves an issue where retrieving the "pointer to coreboot tables" from within the libpayload entry point was failing due to incorrect argument passing. BUG=b:332759882 TEST=Built and booted 64-bit coreboot with 32-bit payload successfully. Change-Id: Ibd522544ad1e9deed6a11015b0c0e95265bda8eb Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82294 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-05-14mb/google/nissa/var/sundance: Update HID offset to 0x01 for Focal touchpadLeo Chou
Currently the Focal touchpad does not work. Based on the Focal touchpad vendor, upadet the HID descriptor address from 0x20 to 0x01. BUG=b:339756281 TEST=Build and check Focal touchpad can work. Change-Id: I383ad907e6a23c34ab1bd0f6594a87564e21181d Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-14mb/google/dedede/var/pirika: Add SPD IDs for two new memory partsDaniel_Peng
Support Memory of Micron MT53E512M32D1NP-046 WT:B and Hynix H54G46CYRBX267 in mem_parts_used list, and generate SPD ID for these parts. DRAM Part Name ID to assign MT53E512M32D1NP-046 WT:B 0 (0000) H54G46CYRBX267 0 (0000) BUG=b:337173071 BRANCH=firmware-dedede-13606.B TEST=Run command "go run \ ./util/spd_tools/src/part_id_gen/part_id_gen.go \ JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ \ src/mainboard/google/dedede/variants/pirika/memory/\ mem_parts_used.txt" Change-Id: I9b1a2a622d0ca1298671b1da58beacc1b4244769 Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82094 Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-13mb/asus/p8z77-m: Support AC97 front audio panelKeith Hui
Add a nvram option for front audio panel type. If it is set to AC97, reprogram front line out and microphone pins to match vendor firmware under same configuration. TEST=On asus/p8z77-m housed in an AOpen H340D case with an AC97 front audio panel, front panel line out port is now available as headphone port in Fedora 39 with this patch applied and option set correctly. And it works. Without the patch (or with this option set to HD Audio), front audio ports are completely inoperable. Change-Id: I39ccf066d87c5744a697599861719182768e0728 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-05-13nb/intel/haswell: Use <device/dram/ddr3.h>Elyes Haouas
Change-Id: I353ceb7ab5ec0c82f5e717c856ad7934fcbd03b6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82355 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-13mb/google/rambi: Use <device/dram/ddr3.h>Elyes Haouas
Change-Id: I3aa669042908b92d7b270df077a352e197071780 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82354 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-13soc/intel/xeon_sp: Use <spd.h>Elyes Haouas
Change-Id: Ib86df42c74474ab6d0bd389073c36ca0761748af Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-05-13mb/intel/{harcuvar,kunimitsu}: Use <spd.h> and <dram/ddr{3,4}.h>Elyes Haouas
Change-Id: I2d73f7815e83e8bf0c6d0a402d32bc99c32c7d90 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82243 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-13mb/google/{eve,glados}: Use <spd.h> and <dram/ddr3.h>Elyes Haouas
Change-Id: I48b833a3727d4b7d7c50371dbe8f090983d80e36 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-13soc/amd/common/block/psp: Comment unused symbolElyes Haouas
This adds a comment for unused AMD_FWM_POSITION_20000_DEFAULT. Change-Id: Id8369f488893e7e5b2e7e7126d1b53199ed1aa77 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-05-13mb/google/brya/var/riven: Copy VBT data file from nivviksDavid Wu
Add data.vbt file for riven recovery image. Select INTEL_GMA_HAVE_VBT for riven as it has a VBT file now. The VBT file is copied from the nivviks reference board. BUG=b:337169542 TEST=build pass Change-Id: I499c1b3e61581483a1640375270f7707ebe8deeb Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82269 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-13cpu/x86/pae/pgtbl.c: remove dead map_2M_page()Krystian Hebel
This function isn't used anywhere. It probably wouldn't work with current coreboot anyway, as it identity mapped lower 2GB of RAM, while ramstage is run from CBMEM, which is usually just below top of memory. It was last used in K8 code that is long gone. Change-Id: I97e2830f381181d7f21ab5f6d4c544066c15b08c Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
2024-05-13mb/google/brox: Disable c1 state auto-demotionAshish Kumar Mishra
Disable c1 state auto-demotion support for brox BUG=None BRANCH=None TEST=Boot brox and verify in fsp debug logs Change-Id: I18d40cd721d46fce4702cf1a943583cd41c03cf4 Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82104 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-12soc/intel/lunarlake: Support stepping A0_2Saurabh Mishra
Details: - Add support for new Lunar Lake MCH ID 0x6410 - Add new CPU id 0xb06d1 Reference: Lunar Lake External Design Specification Volume 1 (734362) TEST=Build, boot the system and verfiy MCH-ID prints in bootblock stage. Below prints verified on Lunar Lake RVP board (lnlrvp). [DEBUG] MCH: device id 6410 (rev 02) is LunarLake M Change-Id: I976d7f269485633d835d204afa224736d71baaa8 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81847 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-12soc/intel/common: Add Lunar Lake CNVI device IDsSaurabh Mishra
Without this patch, ACPI SSDT does not supports and lists CNVW. With this patch, verified "CNVW" in ACPI SSDT listing. Scope (\_SB.PCI0) { Device (CNVW) { Name (_ADR, 0x0000000000140003) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } } } Reference: Lunar Lake External Design Specification Volume 1 (734362) BUG=b:329787286 TEST=verified on Lunar Lake RVP board (lnlrvp). Change-Id: I5a0a3fbc9f43a6a573e33fcf3901055e10faaed1 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81846 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-12mb/google/rex/var/deku: Correct FVM Itrip for GT VR domainTony Huang
Previous CL misspelling VR domain to IA not GT which cause FVM Itrip(GT) not set correctly. This CL corrects it to VR_DOMIAN_GT and confirm FVM Itrip(GT) has set to 54. BUG=b:320410462 BRANCH=firmware-rex-15709.B TEST= FSP debug emerge-ovis coreboot intel-mtlfsp check overrides setting IccLimit[1] = 216 ( 1/4 A) Change-Id: I99df053869aa11b7c82aa0b7f7ec0acf73467a76 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-05-12vc/amd/opensil: introduce common mpio/chip.h header fileFelix Held
The chip drivers in the devicetree use the path where the corresponding chip.h file resides both to include this chip.h file in the static.c generated by util/sconfig from the devicetree and also for the names of the chip config and chip ops struct. To be able to build a SoC using either the MPIO chip driver from the openSIL stub or from the actual openSIL glue code without needing different devicetree files for the different cases, introduce a common MPIO chip.h file that then includes the correct MPIO header file. The chip config and ops structures also need to be renamed to take this change into account. Thanks to Matt for pointing out how to make the path to the actual MPIO chip.h file configurable via a Kconfig setting. This allows overriding this path from site-local without the need to have any reference to site-local in the upstream code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iead97d1727569ec0d23a2b9c4fd96daff4bebcf6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82262 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-12vc/amd/opensil/*/mpio/chip.h: add missing include guardsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idef3b661b1cf3008373e61e0760a7dd3b9e9fede Reviewed-on: https://review.coreboot.org/c/coreboot/+/82261 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-12mb/protectli/vault_cml: use combo v1/v2 FSPMichał Kopeć
Also switch configs to use combo v1/v2 FSP The reason for this change is to simplify configuration - instead of multiple targets for VP4630 and VP4650 or VP4670, it's now possible to have one target covering all VP46x0. Change-Id: I1a6f6e873e4ec35b9777dc17c0495151348d1d88 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81963 Reviewed-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-12mb/google/brox/var/greenbayupoc: Configure board for SODIMM useEren Peng
Configure SODIMM settings for greenbayupoc. The SODIMM settings are copied from mainboard/google/brya/variants/baseboard/brask/memory.c. BUG=b:336955026, b:332230842 TEST=emerge-brox coreboot chromeos-bootimage, flash and boot to OS using Hynix HMAG56EXNSA051N 4G and Micron MTA8AFT1G64HZ-3G2R1 8G SODIMM. Change-Id: I1552cadfa81c48fe561947ded078bcca2e6bc6ad Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82085 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-05-12mb/google/brya/var/riven: Generate SPD ID for supported partsDavid Wu
Add supported memory parts in mem_parts_used.txt, and generate SPD id for these parts. 1. MT62F1G32D4DR-031 WT:B (Mircon) 2. MT62F512M32D2DR-031 WT:B (Mircon) 3. H9JCNNNBK3MLYR-N6E (Hynix) 4. K3LKLKL0EM-MGCN (Samsung) 5. K3LKBKB0BM-MGCP (Samsung) 6. H9JCNNNCP3MLYR-N6E (Hynix) BUG=b:337169542 TEST=build pass Change-Id: I0ff3b1e14fb8bb87d8fc9cbe0e177a5bcedef08c Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82255 Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-05-11include/efi: Override EFIAPI macro for x86_64Subrata Banik
This commit overrides the EFIAPI macro definition when using FSP on x86_64 to ensure the correct calling convention is used. On i386, there is no side-effect since the C calling convention used by coreboot and FSP are the same. However, on x86_64, FSP/UEFI uses the Microsoft x64 calling convention while coreboot uses the System V AMD64 ABI. This change resolves this incompatibility by setting EFIAPI to attribute((ms_abi)) on x86_64 when using FSP. TEST=Able to build google/rex0 in 32-bit and 64-bit mode. Change-Id: Ifae910be66d550af04cce5136d186a7e9dd085b3 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82266 Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-11driver/intel/fsp2_0: Update soc_binding.h for coreboot compatibilitySubrata Banik
Included <efi/efi_datatype.h> to address coreboot style header definitions rather using EDK2 header <Base.h>. TEST=Able to build google/rex0. Change-Id: I66559872c8d137d1baef5860fb98cad2a5214368 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82265 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-10drivers/mipi: Update init code for IVO_T109NW41 panelZhongtian Wu
1. VCOM OTP burning, initial code Settings can be deleted, B6h 2. Fine-tune VGH, VGL, VGHO, VGLO voltage, B1h PA6 3. Boot CLK performance change: add E9h, C7h, E9h 4. Extend TFT life: D5h PA25~PA32,D3h PA1~PA5; 5. Gamma optimization: E0h 6. Improve picture quality, add EQ: D2h to CLK 7. Press mura to improve and modify B1h PA4 and PA5 BUG=b:320892589 TEST=boot ciri with IVO_T109NW41 panel and see firmware screen Change-Id: I13421660faba9ef8e33a51c5ab28aeb1388aff40 Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82240 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
2024-05-09include/spd.h: Add SPD_MEMORY_TYPE_LPDDR3_INTEL into spd_memory_typeElyes Haouas
Change-Id: I694af163fb530be49561e74e74d9c08e04986a44 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82223 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-09include/spd.h: Add new spd_memory_type valuesElyes Haouas
This adds LPDDR4X, DDR5,LPDDR5, DDR5_NVDIMM_P and LPDDR5X, according to revision of JESD400-5A.01, January 2023. Change-Id: I15802da03dc748c0e7f6b035fed25371afe3eed4 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82217 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-09arch/arm64/Makefile.mk: Switch linker to GNU GCCYidi Lin
TF-A migrates the default choice of linker to GCC in order to enable LTO. Change BL31_LDFLAGS from `--emit-relocs` to '-Wl,--emit-relocs', so that GCC is able to pass `--emit-relocs` to the linker. [1]: https://review.trustedfirmware.org/c/26703 BUG=b:338420310 TEST=emerge-geralt coreboot TEST=./util/abuild/abuild -t google/geralt -b geralt -a TEST=./util/abuild/abuild -t google/oak -b elm -a Change-Id: I65b96aaa052138592a0f57230e1140a1bb2f07ac Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82189 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-09mb/google/brox: Sending End of Post (EOP) asynchronouslyKarthikeyan Ramasubramanian
Currently EOP message is sent to CSE late in the boot flow. Instead send it asynchronously to save ~10 ms in boot time. BUG=b:337330958 TEST=Build Brox BIOS Image and boot to OS. Change-Id: I229d16a5dcd072958db3f59a9c364bf7508b3047 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-09arch/arm64/Makefile.mk: Unset toolchain vars for BL31Yidi Lin
This change is for upcoming arm-trusted uprev commit. TF-A refactors the toolchain detection in [1][2]. After that `AR`, `CC`, `LD` and other toolchain variables have precedence over `CROSS_COMPILE`. Since ChromeOS build system also sets those toolchain variables when building coreboot, it results that TF-A uses CrOS GCC instead of coreboot SDK. It needs to unset those variables in order to make `CROSS_COMPILE` effective. TF-A upstream changes the default linker from BFD to GCC in [3]. Therefore, temporarily overriding LD as $(LD_arm64} to fix the below build error. aarch64-elf-gcc: error: unrecognized command-line option '--emit-relocs' In addition, TF-A wrapped LD with single quotes to solve Windows path issue[4]. On MT8173 platform, `--fix-cortex-a53-843419` is appended to $(LD_arm64} for ERRATA_A53_843419. It results in the below build error. /bin/sh: 1: --fix-cortex-a53-843419: not found Since `--fix-cortex-a53-843419` is never passed to TF-A, simply extract the LD command from $(LD_arm64) by $(word 1, $(LD_arm64)). [1]: https://review.trustedfirmware.org/c/24921 [2]: https://review.trustedfirmware.org/c/25333 [3]: https://review.trustedfirmware.org/c/26703 [4]: https://review.trustedfirmware.org/c/26737 BUG=b:338420310 TEST=emerge-geralt coreboot TEST=./util/abuild/abuild -t google/geralt -b geralt -a -x TEST=./util/abuild/abuild -t google/oak -b elm -a -x TEST=./util/abuild/abuild -t google/cherry -x -a Change-Id: Ieac9f96e81e574b87e20cd2df335c36abcb8bb5c Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-09soc/mediatek/mt8188: devapc: set devapc permission for MFGFei Yan
In order to support SVP Feature, EMI-MPU has to give MFG permissions to allow MFG to access secure buffer by secure read and write. Currently MFG is in domain 0, which include many other masters. Move MFG to domain 6. Set MFG remap, so that MFG can switch to protect mode by MFG register. Change MFG permission from NO_PROTECTION to SEC_RW_ONLY for domain 0, so that only AP in secure mode can access MFG_S_S-2 and MFG_S_S-5. BUG=b:313855815 TEST=emerge-geralt coreboot Change-Id: Ic6fb7d85bf9d4d92946a045a274b274abc440e1d Signed-off-by: Fei Yan <fei.yan@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-08mb/google/brox: Fix the pad reset config for WLAN Wake interruptKarthikeyan Ramasubramanian
Update the pad reset config for WLAN Interrupt from PLTRST to DEEP so that it can still act as a wake source during S3 suspend. BUG=b:336398012 TEST=Build Brox BIOS image and boot to OS. Suspend to S0ix & S3 and wakeup successfully using Wake on WLAN. 268 | 2024-05-07 13:56:44-0700 | S0ix Enter 269 | 2024-05-07 13:57:07-0700 | S0ix Exit 270 | 2024-05-07 13:57:07-0700 | Wake Source | GPE # | 3 271 | 2024-05-07 13:59:01-0700 | ACPI Enter | S3 273 | 2024-05-07 13:59:26-0700 | Wake Source | PME - WIFI | 0 274 | 2024-05-07 13:59:26-0700 | ACPI Wake | S3 275 | 2024-05-07 13:59:26-0700 | Wake Source | GPE # | 3 Change-Id: Ie0d6e6c8fefdd081e252ea99d6e3c559a5330b0e Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82234 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-08mb/google/brox/var/brox: increase PsysPmax from 21.5W to 208WLawrence Chang
According to Brox HW design, the PsysPmax is supposed to be 208W. This patch changes PsysPmax setting from 21.5W to 208W. Change-Id: I43f4b00a54dc0dfe6bd690492f9ef92698c9b903 Signed-off-by: Lawrence Chang <lawrence.chang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Shelley Chen <shchen@google.com>
2024-05-08soc/intel/xeon_sp/spr: Refine return value checksShuo Liu
mp_init_with_smm returns cb_err type, where 0 means success and negative values represent error (see cb_err.h). However, failure checks in form of "ret < 0" is not straightforward. Use "ret != CB_SUCCESS" instead. Change-Id: I7e57f2da0361f3109051e9a35b1cce81d559b261 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-05-08mb/asrock/z97_extreme6: Add new mainboardAngel Pons
That's an ATX mainboard with a LGA1150 socket and four DDR3 DIMM slots. Porting was done using autoport and then doing a bunch of manual edits. This board has two socketed DIP-8 SPI flash chips and a physical switch to choose which one should the system boot from. As long as one of them contains a bootable firmware image, it is possible to reflash the other chip using the internal programmer by flipping the switch after booting to OS. Even if one somehow manages to flash unbootable firmware to both chips, they are socketed: one can carefully remove them from the socket and reflash them externally, which is a relatively safe procedure (when compared to in-circuit flashing, especially if the board isn't designed to safely be flashed in-circuit). In short, the board is hard to brick. Haswell MRC.bin cannot be used because it lacks support for the Z97 PCH found on this mainboard. Broadwell MRC.bin only works with Haswell CPUs so far, as raminit fails on Broadwell CPUs for an unknown reason. Maybe it's something about RcvEn, but it's unlikely it can easily be fixed. Working: - All four DIMM slots - Broadwell MRC.bin for raminit purposes - Serial port to emit spam - POST code display - S3 suspend/resume - All rear USB 3.0 ports - Internal USB 2.0 port - Audio output (green jack) - Integrated graphics (libgfxinit) - HDMI - VBT - Intel GbE (I218-V PHY and PCH MAC) - Realtek RTL8111E GbE - At least one SATA port - M2_1 slot (Gen3 x4, bifurcated from CPU) - Flashing internally with flashrom - SeaBIOS (current version) to boot Arch Linux - NCT6791D Super I/O software-based fan control tested using `sensors` and `pwmconfig`, all 6 fan tachometers and 5 PWM outputs work fine. Untested for now (i.e. should work, will eventually test): - DVI-I, DisplayPort - EHCI debug - Front USB 2.0 and 3.0 ports - The other audio jacks (as well as SPDIF) - The other PCIe and M.2 ports - Non-Linux OSes - PS/2 combo port (can only test with a keyboard) Untestable (i.e. cannot test due to unavailable hardware): - Thunderbolt AIC (Add-In Card) support Not working: - Broadwell CPUs, they require more magic to work (working on it). - Booting from ASM1062 SATA ports with SeaBIOS. Other payloads were not tested. It seems that the problem is with the controllers. - Super I/O automatic fan control: not yet implemented in coreboot. To control fans, use software fan control methods in the meantime. - Acer B247Y board driving a FHD panel of a Samsung S24E650 monitor, connected to the board's HDMI output says "Unsupported resolution" after libgfxinit configured the iGPU outputs in linear framebuffer mode. HDMI output works fine after Linux's i915 driver takes over. Not sure if it's specific to the monitor: the HDMI cable is beaten up, and it is hard to replace (need to relocate the logic board so that the ports are accessible). Change-Id: If1d22547725e59f435de36b973e1bf4f334269a9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Máté Kukri <kukri.mate@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-05-08commonlib/timestamp_serialized: Define VB_AUXFW_SYNC_DONE timestampKarthikeyan Ramasubramanian
Define a new timestamp to identify the completion of Auxiliary Firmware Sync. Without that, it gets accounted into a different timestamp ID in a misleading way. BUG=None TEST=Build Brox BIOS image and boot to OS. Confirm the timestamp is recorded in cbmem. Change-Id: Icd01c68a5848e2aed7bbdcc794987bc780e78dab Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com>
2024-05-08mb/samsung/lumpy: Fix smbus subsystem IDMatt DeVillier
The smbus subsystem ID was inadvertently reversed when added in commit eb2897b113a0 ("mb/samsung/lumpy: override SMBus subsystem ID"), so correct it. TEST=build/boot Win10 on lumpy, verify touchpad driver functional. Change-Id: I7520041ea113dff8f2abebfc71a1de6d0f9fc91f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-08mb/google/parrot: Fix smbus subsystem IDMatt DeVillier
The smbus subsystem ID was inadvertently reversed when added in commit 6974bcd28e74 ("mb/google/parrot: override SMBus subsystem ID"), so correct it. TEST=build/boot Win10 on parrot, verify touchpad driver functional. Change-Id: I93d4812e24a6fc7419887e364974fcfae2465ea3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-08mb/google/butterfly: Fix smbus subsystem IDMatt DeVillier
The smbus subsystem ID was inadvertently reversed when added in commit a6076cfcfdbe ("mb/google/butterfly: override SMBus subsystem ID"), so correct it. TEST=build/boot Win10 on butterfly, verify touchpad driver functional. Change-Id: If4a0eae06bbe4dcba893a42797e371bbf9f899b9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82225 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-07mb/google/corsola: Add new board variant SquirtleYang Wu
Add a new Kingler follower 'Squirtle'. BRANCH=corsola BUG=b:333826091 TEST=emerge-corsola coreboot Change-Id: I393738fc470ffc907f125647a46bf81c243708d7 Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-05-07mb/adlink: Remove leftover directoryAngel Pons
These boards are clones of LiPPERT boards, which are no longer in this branch (they were AMD AGESA boards). So, drop the ADLINK placeholders. Change-Id: Idfd77daf4a5b3d1e120ed22f9a48fa1bf884de9e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-05-07soc/intel/meteorlake: Determine TBT controllers exist by VID/DIDKane Chen
The original code uses TRE0-TRE3 register to determine whether or not the TBT controller exists. However, there is a remap in fsp could confuse the TRPx._STA. Ex: Disable TBT controller 0 on b:0 d:7 f:0 Enable TBT controller 1 on b:0 d:7 f:1 The FSP will do the remap and after the remap: TBT controller 1 is on b:0 d:7 f:0 TBT controller 0 is on b:0 d:7 f:1 This is becuase func 0 must exist per pci spec. However, the TRE0-TRE3 will not be remapped so that the ACPI TRPx._STA method could be confused. In such scenario, TRP0._STA will return 0x0, TRP1._STA will return 0xf which is wrong because TBT controller 1 is now at b:0 d:7 f:0 TEST=tested on rex and _TRPx._STA returns correctly. TBT function OK Change-Id: I54f2ea99cd1ec73dd0b71a6ba738aa927b0ae80f Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-05-07soc/intel/mtl: Fixed TBT PCIe devtree remappingKane Chen
The TBT PCIe devicetree settings are not remapped properly when TBT PCIe port 0 is disabled. This code refer SHA:58bc5d937 to remap the PCIe devtree settings properly in case of TBT PCIe port0 is disabled, TEST=Tested on screebo and found "Remapping PCIe Root Port #2 msg" showed up in coreboot log Change-Id: I7c7549ddf8ccdd67d7af7c69f51a84614cff9a03 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81841 Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-07dram/ddr3: Use the same naming convention as DDR4Elyes Haouas
Change-Id: Ifaff19c0117b5247d3321605ccc2e97bf8226ca8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82216 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-07dram/ddr5: Use the same naming convention as DDR{2,3,4}Elyes Haouas
Change-Id: I2cc38926b56315d4a828311917ff58051b34b777 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-07spd.h: Move enum ddr4_module_type to ddr4.hElyes Haouas
Move specific enum ddr4_module_type to <device/dram/ddr4.h>. Change-Id: Ia538d2c73affa6560fa1533a40c02b3677588f5a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-07device/dram/ddr{3,4}: Rename spd_raw_data for specific DDRElyes Haouas
Rename different spd_raw_data[] for DDR3 and DDR4. This is to solve the conflict when we include both "ddr3.h" and ddr4.h" for example here: src/device/dram/spd.c. Otherwise, it won't compile as DDR3 and DDR4 have different spd_raw_data[] size. Change-Id: I46597fe82790410fbb53d60e04b7fdffb7b0094a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-07device/device_util: Add and use is_pci_bridge()Shuo Liu
TEST=Build and boot on intel/archercity CRB Change-Id: Ied4921f7dc7e144e580d05d4f2262777aa59d895 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81566 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-07soc/intel/xeon_sp/spr: Print return codes for mp_init_with_smmShuo Liu
TEST=Build and boot on intel/archercity CRB Change-Id: Iee2234a3055fe8a94ecbfc820e9ff9e981f8dff2 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-07soc/intel/xeon_sp/spr: Remove duplicated warningShuo Liu
When microcode is not found, intel_microcode_find() will output warning and skip the update. Remove the duplicated warning in CPU codes. TEST=Build and boot on intel/archercity CRB Change-Id: I0264edc01e90186a7b77d57f9c147d3b73747437 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-07soc/intel/xeon_sp/spr: Add comments for get_thread_countShuo Liu
Add comments to clarify the usage of logical core count instead of physical core count. TEST=Build and boot on intel/archercity CRB Change-Id: I2bc94391f060cec9de91183021da03bc5c7438c0 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82097 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-07soc/intel/xeon_sp/spr: Remove unused file includes in cpu.cShuo Liu
TEST=Build and boot on intel/archercity CRB Change-Id: I17b42331fa9b5f59d1fb1d66b9155c57e258357b Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82191 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-07spd.h: Move enum ddr5_module_type to ddr5.hElyes Haouas
Move specific enum ddr5_module_type to <device/dram/ddr5.h>. Change-Id: Ie38d1e99fa46c278e60ced2d3eef29ca823d4b1d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-05-06soc/intel/xeon_sp: Add fill_pd_distancesShuo Liu
Update a simple algorithm to cover some basic case for proximity domain distance handling. In the same time, the local variable usage of fill_pds() is optimized. TEST=Build and boot on intel/archercity CRB ACPI SRAT, SLIT and DMAR (Remapping Hardware Static Affinity) are generated correctly for 2S system. Change-Id: I2b666dc2a140d1bb1fdff9bc7b835d5cf5b4bbc5 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Co-authored-by: Ziang Wang <ziang.wang@intel.com> Co-authored-by: Gang Chen <gang.c.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81442 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06mb/google/brya/var/bujia: Add VBT data fileShon Wang
Add data.vbt files for bujia supported by brask recovery images. Select INTEL_GMA_HAVE_VBT for bujia which currently have a VBT file. changes: 1. "integrated DisplayPort with HDMI/DVI compatible" -> "Integrated HDMI/DVI". 2. turn the AUX off. BUG=b:327549688 TEST=build/boot various brya variants Change-Id: Id56461708250eaedd288ddbf788d686153df0b96 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81553 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06mb/google/brox:Select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATIONKrishna Prasad Bhat
Brox uses PDC<->PMC direct connection for USBC mux configuration. Select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION to enable it. This patch also adds additional dependency on ENABLE_TCSS_USB_DETECTION to be selected only when PDC<->PMC direct connection and CHROMEOS is not used. BUG=b:332383540 TEST=USB3 plugged during G3, is detected after system boots from G3. Cq-Depend: chromium:5484387 Cq-Depend: chrome-internal:7106592 Change-Id: I0f62943f87d8fb6eb494c0aca3ef08c33cd05ffd Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-05-06common/block/tcss: Add config for PDC<->PMC mux configurationKrishna Prasad Bhat
Introduce a new Kconfig to enable PD controller to PMC mux configuration. Selecting this config enables direct communication from PDC to PMC. TCSS_HAS_USBC_OPS enables USB-C operations via the EC. When SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION is selected, disable TCSS_HAS_USBC_OPS to avoid sending PMC commands from AP/EC. BUG=b:332383540 TEST=USB3 plugged during G3, is detected after system boots from G3. Cq-Depend: chromium:5484387 Cq-Depend: chrome-internal:7106592 Change-Id: Ieeb503393418cdad43384be39ac49c93ba91e4db Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82077 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06mb/google/brya: Correct _PLD valuesWon Chung
For Mithrax and Felwinter, port C1 is on the left side and port C2 is on the right side. Correct the values accordingly. The board schematics was mirrored, so had to obtain an actual machine and physically check the correct ports. BUG=b:321051330 TEST=emerge-${BOARD} coreboot then check ACPI table on DUT Change-Id: I977c3b4081987592a1d46529eb848a07a6c4cb47 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81363 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Emilie Roberts <hadrosaur@google.com>
2024-05-06mb/google/brya: Fix mux_conn index used by ec/google/chromeecWon Chung
Within ec_acpi.c, USB-C ports are iterated to be matched with corresponding mux. The iteration happens from 0 to the number of USB-C ports. Given iteration index i, the port with PLD group_token of (i+1) is matched with mux_conn[i]. Mithrax and Felwinter devicetree matches conn1 to mux_conn[1] and conn2 to mux_conn[0]. However, conn1 is for usbX_port2 which has group_token of 1 and conn2 is for usbX_port3 which has group_token of 2. Thus, follow the convention to add conn1 to mux_conn[0] and conn2 to mux_conn[1]. Otherwise, the kernel subsystem linking between Type C connector and USB mux will be swapped. BUG=b:329657774 b:121287022 b:321051330 b:204230406 TEST=emerge-${BOARD} coreboot then check ACPI table on DUT. TEST=Manually check that usb-role-switches are mapped to the correct port. Attach USB 3 A to C cable from development machine to left port of DUT. Attach nothing to right-hand port. usbpd lines are workaround for devices without firmware patch to connect superspeed lines. ectool usbpd 0 none ectool usbpd 0 usb ectool usbpd 1 none ectool usbpd 1 usb echo host > /sys/class/typec/port0/usb-role-switch/role (should succeed) echo host > /sys/class/typec/port1/usb-role-switch/role (should fail as no cable attached) Change-Id: I349682a6fe3fe4848e4e86d9c446530a31b35875 Signed-off-by: Won Chung <wonchung@google.com>, Emilie Roberts <hadrosaur@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81354 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Emilie Roberts <hadrosaur@google.com>
2024-05-06drivers/intel/pmc_mux/conn: Copy ACPI _PLD property from USB port to muxWon Chung
Copy ACPI _PLD values from USB ports to corresponding USB muxes so that the kernel can create symlinks between Type C connectors and corresponding USB muxes. This symlink will be used to let userspace be able to modify the USB role without knowing ACPI topology for the device. BUG=b:121287022 b:329657774 TEST=emerge-${BOARD} coreboot then check ACPI table on DUT Change-Id: If27042cc995ef188f8a3e31444e994318ff98803 Signed-off-by: Won Chung <wonchung@google.com> Tested-by: Emilie Roberts <hadrosaur@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81089 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Emilie Roberts <hadrosaur@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06soc/intel/xeon_sp/acpi: Refactor Xeon-SP ASL file locationShuo Liu
soc/intel/xeon_sp/acpi/*.asl are actually used only by SKX and CPX platforms and not forward compatible to later SoC generations. Move them to soc/intel/xeon_sp/acpi/gen1/ for clean maintenance. TEST=Build and boot on intel/archercity CRB Change-Id: Ib060b123ab0fd761f00d9a0573e9b73d600ea9ef Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82033 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06acpi: Remove acpigen_write_OSC_pci_domainShuo Liu
For PCI domains, static _OSC will be used for better readability and maintenance. This reverts commit f4a12e1d39a097e17007ef11ccf784c2a42f1924. TEST=Build and boot on intel/archercity CRB Change-Id: I2e2b2f0533a3940caf2806ec1ed048c30e4ba801 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82032 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06mb/system76: Exclude ramtop from CMOS checksumTim Crawford
Use the default position for ramtop and exclude it from the checksum. Fixes invalid checksum after caching ramtop causing things like disabling CSME to not work. Fixes: 10d2af04e754 ("mb/system76: Add space for ramtop in CMOS layout") Change-Id: If30df1e6f2735cf767856e42dfede3d17fe494eb Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81641 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06mb/google/nissa/var/sundance: Use default eMMC DLL settingLeo Chou
Configure eMMC DLL tuning values for Sundance board Samsung sku. BUG=b:337741162 TEST=Use the value to boot on Sundance successfully. Change-Id: I5f1e03c06c9f8567e757fed999730dff2551f1e0 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82173 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06mb/google/sarien: Make use of chipset dt reference namesFelix Singer
Replace the PCI numbers with the reference names from the chipset devicetree. Also, remove their comments since they are superfluous now. Change-Id: I49f5fda5628b2ebc76cd8db20c8f7fe85c676c7a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-05-06mb/google/sarien: Remove dt entries equal to chipset dtFelix Singer
Clean up the devicetree by removing entries which are equal to the chipset devicetree. The P2SB device is enabled but it's hidden by the FSP. So just remove that as well since the chipset devicetree configures it correctly. Change-Id: I38f46949d36359826317252e8d3434ad1b24382d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82156 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06mb/google/drallion: Make use of chipset dt reference namesFelix Singer
Replace the PCI numbers with the reference names from the chipset devicetree. Also, remove their comments since they are superfluous now. Change-Id: Ib873854954e44b3ea370c2574da5db9792a446e9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82155 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06mb/google/drallion: Remove dt entries equal to chipset dtFelix Singer
Clean up the devicetree by removing entries which are equal to the chipset devicetree. The P2SB device is enabled but it's hidden by the FSP. So just remove that as well since the chipset devicetree configures it correctly. Change-Id: I6186d295427bcd4a3b696f4df59d94a148ced011 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-05-06mb/google/brya/var/pujjoga: Add GPIO tableleo.chou
Fill GPIO table for pujjoga. BUG=b:336469694 TEST=emerge-nissa coreboot Change-Id: I3f633cf99f56d5f855015de805e16c1205c9bc99 Signed-off-by: leo.chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82044 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-05-06mb/google/brya/var/xol: Override TDP PL1 valueSeunghwan Kim
Update TDP PL1 value for the DTT optimization. The new value 18W is from internal thermal/performance team. - tdp_pl1_override: 15 -> 18 (W) BUG=b:336684032 BRANCH=brya TEST=built and verified MSR PL1 value. Intel doc #614179 introduces how to check current PL values. [Original MSR PL1/PL2/PL4 register values for xol] cd /sys/class/powercap/intel-rapl/intel-rapl\:0/ grep . *power_limit* constraint_0_power_limit_uw:15000000 <= MSR PL1 (15W) constraint_1_power_limit_uw:55000000 <= MSR PL2 (55W) constraint_2_power_limit_uw:114000000 <= MSR PL4 (114W) After this patch: constraint_0_power_limit_uw:18000000 constraint_1_power_limit_uw:55000000 constraint_2_power_limit_uw:114000000 Change-Id: I28c4f099e0169e8389f63083c03023dd8338589f Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82151 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06mb/google/brya/var/xol: Tune I2C5 timing parametersSeunghwan Kim
Update I2C5 timing parameter values to meet I2C bus spec. - fall_time_ns: 400 -> 200 BUG=None BRANCH=brya TEST=built and measure I2C5 timing parameters Before: tLOW : 1.88 us (spec >= 1.30) tHIGH: 0.57 us (spec >= 0.60) fSCL : 399.80 KHz After: tLOW : 1.60 us (spec >= 1.30) tHIGH: 0.97 us (spec >= 0.60) fSCL : 392.1 KHz Change-Id: I386b2765410fd10b8cd711f54478fb52428de5a3 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-06mb/google/nissa: Create a riven variantDavid Wu
Create the riven variant of nissa reference board by copying the template files to a new directory named for the variant. The riven variant is a twinlake platform. BUG=b:337169542 TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_RIVEN Change-Id: I1be2346d87c891cc0e5fbda094e1f6e0dd60df1b Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82132 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06mb/google/corsola: Sort Kconfig board selection in alphabet orderYidi Lin
Change-Id: Iefe61d3ad51d355806716483248df5b1083b69bc Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82149 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06drivers/intel/mipi_camera: Add CSI2 Data Stream Interface GUIDCoolStar
Required in SSDB for Windows drivers. Tested on google/brya (kano) and verified Intel Webcam shows up to Windows as a camera source Change-Id: Id6089f6bd841333882e28de9307fe5e48e368d02 Signed-off-by: CoolStar <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82068 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06mb/google/nissa/var/pujjoga: Generate SPD IDsroger2.wang
Add pujjoga supported memory parts in mem_parts_used.txt, generate SPD id for this part. 1. Samsung K3KL6L60GM-MGCT, K3KL8L80CM-MGCT 2. Hynix H9JCNNNBK3MLYR-N6E, H58G56BK7BX068 3. Micron MT62F1G32D2DS-026 WT:B BUG=b:337990338 TEST=Use part_id_gen to generate related settings Change-Id: I39d44fd278474a7375ad1d2d904d14b9463ba86d Signed-off-by: roger2.wang <roger2.wang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82135 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-05-06mb/google/nissa/variant/pujjoga: Update devicetree settingsroger2.wang
Based on schematic of 500E_GEN4S_ADL_N_MB_0418, generate overridetree.cb settings for Pujjoga. BUG=b:337611700 TEST=FW_NAME= pujjoga emerge-nissa coreboot chromeos-bootimage Change-Id: I279f94044a22f25100a44b1abe2ef5fb6d0dd835 Signed-off-by: roger2.wang <roger2.wang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82109 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-05-06soc/amd/phoenix/include/platform_descriptor: remove TODOFelix Held
There's nothing in this header file that needs to be updated for the Phoenix SoC, so remove the 'Update for Phoenix' TODO. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9d7b5e8d8d6c8c22c2fae8e89d073481d21d8bdc Reviewed-on: https://review.coreboot.org/c/coreboot/+/82150 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06mb/lenovo/*: Set VR12 PSI to fix crashPatrick Rudolph
When in Package C3 or deeper the PSI settings are used to switch the CPU VR into a low power state. It was found that the voltage regulator on the Sandy-Bridge series has non-default PSI settings, compared to Lenovo's Ivy-Bridge series. Apply the same PSI value for PSI2 and PSI3 as the vendor BIOS does to fix a hang when the package is idle. Since neither the vendor BIOS is open-source, nor datasheet exists for the used VR it's unclear why those PSI values must be used and how they influence the regulator. The X220 already has the correct PSI values configured and is now stable for more than 24h in Package C7 state. TEST: Not tested on the affected boards, only checked vendor firmware. Change-Id: Idf8c3719f19f7bcdab30c543215c8abd2669cfd2 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-06block/fast_spi: Use read32p/write32p for SPI RWAshish Kumar Mishra
The current fast_spi code uses memcpy for rw. The SPI flash read/write has 4 byte limit, due to which the current 64 bit memcpy doesn't work. Hence update rw ops to use read32p/write32p. BUG=b:242829490 TEST=Verified MRC cache working on MTL 64-bit, future 64 bit platforms and RPL(brox/skolas) 32-bit platforms. Change-Id: I317c7160bf192dd2aeacebf6029a809bc97f3420 Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-06mb/google/rex/var/deku: Update psys_pmax_watt value to 180WTony Huang
Adjust setting is from power team. Change from 172W to 180W BUG=b:320410462 BRANCH=firmware-rex-15709.B TEST= FSP debug emerge-ovis coreboot intel-mtlfsp check overrides setting Change-Id: Icc8b12adc9fb9f680b05131c8d41212865223ca9 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-05-06mb/google/rex/var/deku: Update FVM itrip for VR domainTony Huang
Adjust setting is from power team. Itrip(GT) FVM 54 Itrip(SA) FVM 27 BUG=b:320410462 BRANCH=firmware-rex-15709.B TEST= FSP debug emerge-ovis coreboot intel-mtlfsp check overrides setting Change-Id: I6d6cf7cecaac650a7b1784833b4afb8dffb3db2c Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82176 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-03soc/intel/xeon_sp/spr: Drop unused symbolElyes Haouas
SOC_INTEL_PCIE_64BIT_ALLOC is not used. Change-Id: I1ef52104ef1d883330b800215cb4d0475092d8fe Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81975 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-03drivers/wifi/generic: Fix a typo on symbolElyes Haouas
WIFI_MTCL_CBFS_FILEPATH is now used. Change-Id: Icdd0332ae9c56a54596a775c0a9aa7b9f8d6738c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-03mb/google/brya/var/xol: Update board type to BOARD_TYPE_ULT_ULXSeunghwan Kim
Correct .UserBd field to BOARD_TYPE_ULT_ULX from BOARD_TYPE_MOBILE. This is from Intel's guidance for MRC to map the memory speed to proper POR number. BUG=b:332980211 BRANCH=brya TEST=Built and compare the results of command 'dmidecode -t 17' [Before] (Same values in all of memory device handle) Speed: 6400 MT/s Configured Memory Speed: 6400 MT/s [After] (Same values in all of memory device handle) Speed: 5200 MT/s Configured Memory Speed: 5200 MT/s Change-Id: Id16bcbc2d0cb4c2cf3008cf2ef1027ed98e93afb Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Chen <jamie.chen@intel.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-03drivers/intel/fsp2_0: Release bmp_logo during OS_PAYLOAD_LOAD stageKarthikeyan Ramasubramanian
bmp_load_logo() loads the custom logo.bmp file into CBMEM. This cbmem buffer is released after FSP-S init is complete. In certain platforms, the logo file is displayed during PCI enumeration. This means the logo buffer is used after it is released. Fix this issue by releasing the logo buffer when the coreboot has finished loading payload. During S3 scenario CBMEM is locked, bmp logo is not loaded and hence the release is a no-op. BUG=b:337144954 TEST=Build Skyrim BIOS Image and boot to OS. Ensure that the chromeOS boot logo is seen without any corruption. Change-Id: Id27cf02de04055075e7c1cb0ae531dee8524f828 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82121 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-05-03soc/intel/xeon_sp: Remove unused xeonsp_acpi_create_madt_lapicsShuo Liu
TEST=Build and boot on intel/archercity CRB Change-Id: I06e5ff635c37253b1c8f151b62f696ff7e5e22ef Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82110 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-03mb/google/corsola: Initialize USB port 0Wentao Qin
The default MT8186 platform is to initialize USB3 port 1. Use option bit 27 in fw_config to enable initialization of USB2 port 0 to support devices mounted on it. BUG=b:335124437 TEST=boot to OS from USB-A boot to OS from SD Card BRANCH=corsola Change-Id: I725b80593f5fc498a204bf47f943c36ccbd78134 Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82089 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 12:45:43 +0000