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2023-12-04mb/google/rex/variants/deku: Add basic DTTEran Mitrani
Add default Intel DPTF. BUG=b:305793886 TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: Id681754fc8e7b418de35f66df097cadd4aad7448 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-04mb/google/rex/var/deku: Enable LAN0, LAN1Eran Mitrani
google/deku is a Chromebox featuring two LAN ports. Add overridetree.cb entry to configure the LAN0 LAN1 devices. BUG=b:305793886 TEST=Built FW image correctly. Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I8980dabc7f9fc731a2b60c599e1e48c9b11dabb4 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79292 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-04mb/google/rex/var/ovis: Add power limit support for MCH ID 0x7d14Subrata Banik
This patch adds the power limit configuration for MCH ID index 3 aka 0x7d14 DID which is identical to MCH ID 0x7d01 (index 1). TEST=Able to perform power limit configuration for google/ovis. [DEBUG] WEAK: src/mainboard/google/rex/variants/baseboard/ovis/ ramstage.c/variant_devtree_update called [INFO ] Overriding power limits PL1 (mW) (19000, 28000) PL2 (mW) (64000, 64000) PL4 (W) (120) Change-Id: Iff71adb4e26d18970b5947927c258419f751de32 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79332 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-12-04mb/google/rex: Simplify power limit configuration usageSubrata Banik
This patch removes the deprecated PL_PERFORMANCE and PL_BASELINE configurations, relying instead on the refactored power limit flow. This flow allows for seamless overrides by the baseboard and/or by the variant board, if necessary. Specifically, this patch: - Removes PL_PERFORMANCE and PL_BASELINE configuration options from mainboard.c in the google/rex directory. - Relies on the baseboard_devtree_update() function, which is implemented by the respective baseboard, to handle power limit configuration. - Leverages the variant_devtree_update() function, which is a __weak implementation, to allow overrides by the variant directory. This simplification improves code readability and maintainability while maintaining the flexibility to handle power limit configurations as needed. Change-Id: I872e5cb59d7b2789ef517d4a090189785db46b85 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79331 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-04soc/intel/alderlake: Update LidStatus UPD dynamicallySubrata Banik
This patch ensures that the LidStatus UPD is passed a dynamic value, rather than always passing 1 (CONFIG_RUN_FSP_GOP enabled) for FSP 2.0 devices. Problem statement: * FSP-S GFX PEIM initializes the on-board display (eDP) even when the LID is physically closed, because LidStatus is always set to 1. * FSP-S skips external display initialization even when the LID is closed. Solution: * FSP-S GFX PEIM module understands the presence of an external display if LidStatus is not set, and tries to probe the other display endpoint. * Statically passing LidStatus as always enabled (aka 1) does not illustrate the exact device scenarios, so this patch updates LidStatus dynamically by reading the EC memory map offset. BUG=b:313886118 TEST=Able to build and boot google/marasov to redirect the display using external HDMI monitor while LID is closed. Change-Id: Idb1d71bd54837630f36d43a45effc53d35f9cb70 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79352 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-02acpi: Add PPTT supportDavid Milosevic
This patch adds code to generate Processor Properties Topology Tables (PPTT) compliant to the ACPI 6.4 specification. - The 'acpi_get_pptt_topology' hook is mandatory once ACPI_PPTT is selected. Its purpose is to return a pointer to a topology tree, which describes the relationship between CPUs and caches. The hook can be provided by, for example, mainboard code. Background: We are currently working on mainboard code for qemu-sbsa and Neoverse N2. Both require a valid PPTT table. Patch was tested against the qemu-sbsa board. Change-Id: Ia119e1ba15756704668116bdbc655190ec94ff10 Signed-off-by: David Milosevic <David.Milosevic@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-12-02mb/google/rex: Enhance power limit override mechanismSubrata Banik
This patch expands the power limit override capability to include variants directories, enabling them to modify power limit settings configured by the baseboard. Previously, only the baseboard could override power limit settings. For instance, while the google/rex baseboard sets the PL1 max power limit to 15W, the google/screebo variant couldn't override this value. This enhancement empowers variants directories to override baseboard- configured power limit settings, allowing for greater flexibility and control over power limits. BUG=b:313667378 TEST=Able to call into _weak implementation of `variant_devtree_update` unless there is one override. [DEBUG] WEAK: src/mainboard/google/rex/variants/baseboard/rex/ ramstage.c/variant_devtree_update called [INFO ] Overriding power limits PL1 (mW) (10000, 15000) PL2 (mW) (40000, 40000) PL4 (W) (84) Change-Id: Ib07691625e075b0fbab42271512322ffc60ba13b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-12-02soc/amd: Add DBG2 ACPI tableZheng Bao
Dump the DBG2 table on Linux console. $> acpidump -s ACPI: DBG2 0x0000000000000000 000054 (v00 COREv4 COREBOOT 00000000 **) $> acpidump > acpidump.bin $> acpixtract -a acpidump.bin $> iasl -d dbg2.dat $> cat dbg2.dsl /* * ACPI Data Table [DBG2] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */ [000h 0000 4] Signature : "DBG2" [Debug Port table type 2] [004h 0004 4] Table Length : 00000054 [008h 0008 1] Revision : 00 [009h 0009 1] Checksum : FA [00Ah 0010 6] Oem ID : "COREv4" [010h 0016 8] Oem Table ID : "COREBOOT" [018h 0024 4] Oem Revision : 00000000 [01Ch 0028 4] Asl Compiler ID : "CORE" [020h 0032 4] Asl Compiler Revision : 20220331 [024h 0036 4] Info Offset : 0000002C [028h 0040 4] Info Count : 00000001 [02Ch 0044 1] Revision : 00 [02Dh 0045 2] Length : 0028 [02Fh 0047 1] Register Count : 01 [030h 0048 2] Namepath Length : 0002 [032h 0050 2] Namepath Offset : 0026 [034h 0052 2] OEM Data Length : 0000 [Optional field not present] [036h 0054 2] OEM Data Offset : 0000 [Optional field not present] [038h 0056 2] Port Type : 8000 [03Ah 0058 2] Port Subtype : 0012 [03Ch 0060 2] Reserved : 0000 [03Eh 0062 2] Base Address Offset : 0016 [040h 0064 2] Address Size Offset : 0022 [042h 006612] Base Address Register : [Generic Address Structure] [042h 0066 1] Space ID : 00 [SystemMemory] [043h 0067 1] Bit Width : 00 [044h 0068 1] Bit Offset : 00 [045h 0069 1] Encoded Access Width : 03 [DWord Access:32] [046h 0070 8] Address : 00000000FEDC9000 [04Eh 0078 4] Address Size : 00000100 [052h 0082 2] Namepath : "." Raw Table Data: Length 84 (0x54) 00: 44 42 47 32 54 00 00 00 00 FA 43 4F 52 45 76 34 // DBG2T.....COREv4 10: 43 4F 52 45 42 4F 4F 54 00 00 00 00 43 4F 52 45 // COREBOOT....CORE 20: 31 03 22 20 2C 00 00 00 01 00 00 00 00 28 00 01 // 1." ,........(.. 30: 02 00 26 00 00 00 00 00 00 80 12 00 00 00 16 00 // ..&............. 40: 22 00 00 00 00 03 00 90 DC FE 00 00 00 00 00 01 // "............... 50: 00 00 2E 00 // .... BUG=b:303689867 Change-Id: I3c97a78d1889549421baf0bc1a2e8f959a0f47e2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79174 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-02acpi/acpi: update ACPI_DBG2_PORT_SERIAL_16550 subtypeFelix Held
The Microsoft Debug Port Table 2 (DBG2) specification says that the serial port subtype 0x00 should only be used for I/O-mapped 16550 compatible UARTs. The subtype 0x12 is a superset of that, and supports specifying MMIO vs IO and the register access size via the generic address structure. Rename the subtype 0x00 definition to ACPI_DBG2_PORT_SERIAL_16550_IO_ONLY and add the subtype 0x12 definition as new ACPI_DBG2_PORT_SERIAL_16550, so that the acpi_write_dbg2_uart function will write the correct subtype for the generic 16550 UART. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I816bb22e6f76e661c8b8e39a2a4cb83b0085acb5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79219 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-01superio/smsc: Add support for the SCH555x seriesMate Kukri
Used by the OptiPlex 3020/7020/9020: - EMI and Runtime registers work - UART1 works (including IRQs) - PS/2 keyboard and mouse untested Signed-off-by: Mate Kukri <kukri.mate@gmail.com> Change-Id: I9323198f1139cd0c3dd37f977ae7693b721654f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-01mb/google/nissa/var/anraggar: Trim GPIO commentsWeimin Wu
Trim all GPIO comments like "origin ==> current". BUG=b:304920262 TEST=pass building Change-Id: I05daa4df16b6da3d3f971b75c7c467032e3f854d Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79321 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-01mb/google/nissa/var/anraggar: Fix the GPP_D6 for LTE power.Weimin Wu
Fix GPP_D6 configuration for LTE power enable. BUG=b:304920262 TEST=mmcli -m any Change-Id: I2996fd35c2897269997bc0290e0ce93bbbaa1bf8 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79166 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com>
2023-12-01mb/google/nissa/var/anraggar: Fix Type-C & DP functionsWeimin Wu
Due to TCPC0 & TCPC1 exchanged compare to Neried design, but related USB2 Ports not exchanged. BUG=b:304920262 TEST=Tpye-C & DP functions workable Change-Id: I9dacf06b1e672575a684856acdb10b6c88360b18 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79165 Reviewed-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-01mb/google/nissa/var/anraggar: Enable ILITEK touchscreenWeimin Wu
For proto PCB: GPP_C0 for enable power supply which also for sensor subsystem. GPP_C0 must allways turn power on, so GPP_C6 is not only used for enable function but also for stop report. BUG=b:304920262 TEST=1. touchscreen function workable 2. INT pin no active during suspend Change-Id: I7dabf205dba616f57ef9717f950eba96282d8e3d Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com>
2023-12-01mb/google/brya/var/dochi: Update overridetree for type c1Morris Hsu
Update overridetree to correct AUX pin to USB-C port 3 BUG=b:299570339 TEST=emerge-brya coreboot chromeos-bootimage Change-Id: I3a5a89c6008fbf28c927f83060e6e508d60845ba Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79343 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-01soc/mediatek/mt8188: Support loading OP-TEE via an SMCkiwi liu
This patch adds compilation flags to BL31 to support loading OP-TEE via an SMC from rootfs. This patch also reserves 80MB memory space for running the OP-TEE image. BUG=b:246837563 TEST=emerge-geralt coreboot Change-Id: Ic38c8beb59c090ae56c5be6821dd8625435609e9 Signed-off-by: Kiwi Liu <kiwi.liu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78801 Reviewed-by: Kiwi Liu <kiwi.liu@mediatek.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-01mb/google/brox: Update storage settings for SSD and UFSIvy Jian
Brox has SSD and UFS storage per different SKU. 1. Set SSD on CPU PCIe port (PCIEX4_A) and configure related gpio settings according to the schematic. 2. Enable UFS, also enable ISH since it is PCI function 0, required for UFS function 7 to be enabled. 3. Set unused SRCCLKREQ signals to NC. 4. Remove unused gpio settings in variant gpio table to prevent unexpected overrides. BUG=b:311450057 BRANCH=None TEST=emerge-brox coreboot Change-Id: I88922bcfa13652006aa10078c3c444624fd4575e Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79295 Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-01nb/amd/pi/00730F01: drop leftover family10_northbridge PCI driverFelix Held
This is likely a copy-paste leftover, since this SoC neither has a PCI device with the device ID 0x1200 nor is family 10h. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7095f208a7503545ea012241d058692a510109f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79094 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-30mb/google/rex/variants/deku: Add GPIO configurationEran Mitrani
Based on Platform Mapping Document for Deku (go/cros-deku-mapping) from Nov 8, 2023 (Rev 0.4) BUG=b:305793886 TEST=WIP, not tested yet Change-Id: Ib37a7ebf0aca788d14fafea0f97e364beafb4c4d Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78960 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-11-30soc/amd/genoa: Implement romstageArthur Heymans
The only thing romstage needs to do is find cbmem_top. TESTED: reaches ramstage. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ic2837c4a2b0ec8dcd9dd99602f9c073999c36139 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76514 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-11-30vendorcode/amd/opensil: Implement cbmem_top_chipsetArthur Heymans
Use an xPRF call to get the top of lower DRAM. Organize Makefile to keep romstage/ramstage components separate. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Martin Roth <gaumless@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I269663414f4d8e39eb218cd6348bfce7989a79f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76513 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-11-30mb/google/corsola: Use fw_config to differentiate audio ampsYidi Lin
Use fw_config to differentiate audio amps instead of the kconfig option. BRANCH=corsola BUG=b:305828247 TEST=Verify devbeep in depthcharge console Change-Id: I5f887f5e0d16dc14039fb12b636257d01339b2de Signed-off-by: Yidi Lin <yidilin@chromium.org> Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79309 Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-30mb/google/nissa/var/quandiso: Add LTE only daughterboard supportRobert Chen
Quandiso does not use DB_1C, replace the fw_config with LTE only daughterboard. BUG=b:312094048 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Id7129e52d3733f62405f9d766f08563f05016c69 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79297 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Shawn Ku <shawnku@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-30mb/google/galdos/var/lars: Implement touchscreen power sequencingMatt DeVillier
Since lars has two touchscreen options, we need to determine which (if any) are present on a given device at runtime so that there are not multiple ACPI touchscreen devices (as it makes Windows unhappy). Implement power sequencing and runtime detection for both touchscreen options. TEST=build/boot Win11/Linux on google/lars, verify touchscreen detected and functional under both OSes. Change-Id: I49ccb29ec4589315a4abe3c0ea8fa76f97080bcd Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-30mb/google/glados/var/lars: Add Melfas touchscreenMatt DeVillier
LARS has a Melfas touchscreen option, so add an entry for it. Adapted from Chromium branch firmware-glados-7820.315.B, commit a26fe552569f ("Chell: Update DPTF parameters for CPU"). TEST=build/boot Linux on google/lars with Melfas touchscreen, verify functional. Change-Id: Idecd572335d7d5d52e4f89e85ebf7f0c90f23751 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79310 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-30mb/siemens/mc_ehl: Enable write access for SPD EEPROM on mc_ehl1Werner Zeh
The address space of possible SPD-EEPROMs 0x50..0x53 on the SMBus interface is per default write-protected in FSP. This avoids that an SPD-EEPROM on a DRAM module gets overwritten by the host. On mc_ehl1, memory-down configuration is used and there is no SPD EEPROM available. Nevertheless, there is a general purpose EEPROM on the same address available which needs to stay writeable. This patch disables the default-enabled write protect feature for the SPD-EEPROM addresses just for mc_ehl1. Test=Boot into Linux and make sure a write access into the EEPROM is possible. Change-Id: I6b0fcdbeb0dbf971cfdceb70d6f4845765a3bdb6 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com>
2023-11-30mb/google/nissa/var/anraggar: Add OV13B10 MIPI camera deviceWeimin Wu
Enable MIPI camera for anraggar project. Sensor: OV13B10-GA5A Driver: DW9714V EEPROM: GT24P64E Ref to SCH, use MIPI 4-lane serial output interface. BUG=b:309518095 TEST=Google Camera app working Checking log with: coreboot log: \_SB.PCI0.I2C2.CAM0: Intel MIPI Camera Device I2C address 036h \_SB.PCI0.I2C2.VCM0: Intel MIPI Camera Device I2C address 0ch \_SB.PCI0.I2C2.NVM0: Intel MIPI Camera Device I2C address 050h kernel log: kernel: [ 6.140429] intel-ipu6-isys intel-ipu6-isys0: bind ov13b10 11-0036 nlanes is 4 port is 1 cros_camera_service[4755]: Read camera eeprom from /sys/bus/i2c/devices/i2c-PRP0001:02/eeprom cros_camera_service[4755]: Probing media device '/dev/media0' cros_camera_service[4755]: Probing sensor 'ov13b10 11-0036' (v4l-subdev17) cros_camera_service[4755]: Found V4L2 sensor subdev on /sys/devices/pci0000:00/0000:00:15.2/i2c_designware.2/i2c-11/i2c-OVTIDB10:00/video4linux/v4l-subdev17 Change-Id: I6a82557c94203f24449588a6005abc53cc29ca76 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79163 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arec Kao <arec.kao@intel.corp-partner.google.com>
2023-11-30mb/google/nissa/var/anraggar: Enable CNVi BluetoothWeimin Wu
Intel CNVi WLAN's BT uses USB2 Port 10 inside the SOC, and the relevant configuration needs to be modified in overridtre.cb. BUG=b:304920262 TEST=lsusb ID 8087:0033 Intel Corp. rfkill list hci0:Bluetooth Change-Id: Ibcae800836c17307bc133de5a91658f6dda5985c Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79055 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-30mb/google/nissa/var/anraggar: Tune eMMC DLL valuesSimon Yang
Anraggar cannot boot into OS and kernel loading failure. Update eMMC DLL values to improve initialization reliability - Sending different speed TX/RX command/data signal to eMMC and check the response is success or not. - Collecting every eMMC that use for the project - Based on above result to provide a fine tune DLL values BUG=b:308366637 TEST=Cold reboot stress test over 2500 cycles Change-Id: I9ec3cc23000301aa72aed96e74b63114623c4fc2 Signed-off-by: Simon Yang <simon1.yang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78851 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-30vendorcode/amd/opensil/genoa: Implement console callbackArthur Heymans
OpenSIL has an API to call back into the host firmware to print to the console. These could be moved to a common directory when there are more openSIL implementations to see if it is actually common. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Martin Roth <gaumless@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I208eea37ffde64a2311cb9f51e2bcd1ac3dbad4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/76512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-11-30mb/google/brya/var/marasov: Update MSR Package Power Limit-1 valuesDaniel Peng
As customer demand, it is necessary to set MSR Package Power Limit-1 to 17W for the DTT setting to optimize performance. The PL1 value (17W) suggested by the thermal team which is different from the reference code(PL1=15W). BUG=b:312321601 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Built and booted into OS, and confirm MSR PL1=17W correctly. Change-Id: If7874d26038118c5605cf0721c30e681b45123fe Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79335 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-30mb/google/brya: Centralize SOC_INTEL_STORE_ISH_FW_VERSION configSubrata Banik
This patch moves the SOC_INTEL_STORE_ISH_FW_VERSION config from the Nissa baseboard to BOARD_GOOGLE_BRYA_COMMON. This allows all baseboards to retrieve the ISH version and store it into memory. Ensure SOC_INTEL_STORE_ISH_FW_VERSION is enabled only for platforms with ISH support (DRIVERS_INTEL_ISH). Additionally, the dedicated SOC_INTEL_STORE_ISH_FW_VERSION config selection for the Nissa baseboard is no longer needed. BUG=b:280722061 TEST=Able to build and boot google/marasov. Change-Id: I99dab43ae4e13869b7f8797a9c4014f60e38a595 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79338 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-11-29mb/google/rex/var/screebo: Change GPP_B14 from NC to NFKun Liu
Change GPP_B14 from NC to NF BUG=b:272447747 TEST=enable usb OC2 function to ensure USBA work normal Change-Id: Ie0f112bcf183870869d0c1b9a223d4231600a300 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-11-29mb/google/brox: Fix configuration for TPMShelley Chen
On Brox, TPM is using i2c4 and GPP_E2, so modifying the Kconfig to reflect this. Also, fixing up the TPM entry in the device tree. Making sure that the GPIO for GSC_PCH_INT_ODL is set correctly. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I0ecaa6fcfc05c3c2e55f857d7a4e59fe46096bb5 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79102 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-11-29arch/x86/Makefile.inc: Do not pass CPPFLAGS to linkerSrinivas Hegde
We seem to be passing CPPFLAGS to linker in x86 arch ramstage. This is superflous as these are only meant to be compiler flags and should not be passed to the linker. Change-Id: Ia3cd51be6be252aa796191cf0d2cd91d393c8878 Signed-off-by: Srinivas Hegde <srinivashegde@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-11-28soc/amd/cezanne: Move PSP_VERSTAGE_MAP_ENTIRE_SPIROM configKarthikeyan Ramasubramanian
Select PSP_VERSTAGE_MAP_ENTIRE_SPIROM in Cezanne Kconfig instead of common Kconfig. BUG=None TEST=Build BIOS image and boot to OS in dewatt. Change-Id: I476971700824fed06d17000001afc075105fa1ee Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79306 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-28soc/amd/common/psp_verstage: Make SPI ROM mapping configurableKarthikeyan Ramasubramanian
Earlier entire SPI ROM was mapped to memory. With limited TLB resources in PSP, this approach hit the limit on systems using 32 MiB SPI ROM. Therefore regions in SPI ROM were mapped on need basis. This works well on Picasso, Mendocino and Phoenix SoCs. But unfortunately this causes boot hangs in Cezanne SoC. Add a configuration to map the entire SPI ROM and enable it in Cezanne SoC. For other SoCs, keep the configuration disabled so that only the required SPI ROM region is mapped. BUG=b:309690716 TEST=Build and boot to OS in both Dewatt and Skyrim. Change-Id: I166ac7b50b367c067e1a743fc94686e69dd07844 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-11-28soc/amd/genoa: Add openSIL to Genoa KconfigMartin Roth
Select opensil & opensil_genoa. This enables openSIL for Genoa, allowing the build to be tested. Change-Id: I18379f311a56ff3f8b68d3c9a07a4f59de2d90b2 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-11-28vendorcode/amd: Hook up opensilArthur Heymans
OpenSIL has a native buildsystem using meson and configuration mechanism using kconfiglib. To be able to use the coreboot toolchain with opensil, meson crossfiles are used, which get generated by coreboot makefiles. Configuration of opensil is done in a similar fashion with a template defconfig after which kconfiglib is called to generate headers. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Martin Roth <gaumless@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ide2d181914116119dfd37b1511d89ea965729141 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76511 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-11-27acpi: Enable 64bit ECAM resourceNaresh Solanki
Adjust ACPI DSDT to support ECAM resource above 4GB by modifying the PCI ECAM Resource Consumption settings. The changes include specifying a QWordMemory resource template, accommodating non-cacheable, read-write attributes, and adjusting the address range. Change-Id: Idb049d848f2311e27df5279a10c33f9fab259c08 Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-11-27mb/google/brya/var/taeko: Generate SPD IDs for 2 new memory partsLeo Chou
Add taeko new supported memory parts in mem_parts_used.txt, generate spd-3.hex for these parts. 1. Samsung K4UBE3D4AB-MGCL 2. Micron MT53E1G32D2NP-046 WT:B BUG=b:312363368 TEST=Use part_id_gen to generate related settings Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I221ad3f490f24b43fe1ccd211014787eab5d1038 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: YH Lin <yueherngl@google.com>
2023-11-27mb/asus/p8z77-m_pro: Drop useless early init codeKeith Hui
Drop code that puts Super I/O into config mode, select serial device, then leave config mode right away having done nothing. I'll also take this chance to revise its #includes based on include-what-you-use results. Change-Id: I304fc1610740375b59121b6b8784122440795838 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73693 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-27mb/asus/p8z77-m: Properly configure early serialKeith Hui
Board was not producing serial output until well into ramstage. To fix, select SUPERIO_NUVOTON_COMMON_COM_A Kconfig to tell nuvoton_enable_serial() to route serial port A signals to the outside, not GPIO8x. TEST=Full native raminit debug log received over serial by minicom. Change-Id: I376a79dd76ffa5f4d47e7c0cb53680e173e1ad78 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79222 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-11-27mb/google/rex/var/screebo: Enable BT audio offload configKapil Porwal
Enable BT audio offload of ALC1019_ALC5682I_I2S based on fw_config. BUG=b:299510759 TEST=Build and boot to Screebo. Verify the config from serial logs. w/o this CL - ``` [SPEW ] ------------------ CNVi Config ------------------ [SPEW ] CNVi Mode = 1 [SPEW ] Wi-Fi Core = 1 [SPEW ] BT Core = 1 [SPEW ] BT Audio Offload = 0 [SPEW ] BT Interface = 1 ``` w/ this CL - ``` [SPEW ] ------------------ CNVi Config ------------------ [SPEW ] CNVi Mode = 1 [SPEW ] Wi-Fi Core = 1 [SPEW ] BT Core = 1 [SPEW ] BT Audio Offload = 1 [SPEW ] BT Interface = 1 ``` Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I6c713752f3f0bf58b5ebd78b904e773fdbf16e06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77755 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-11-27mb/google/nissa/var/craask: Enable PIXA touchpadTyler Wang
Add PIXA touchpad for variants of craask. BUG=b:310489697 TEST=build craask firmware and test with PIXA touchpad Change-Id: I7e68a44eb3d639eaadb5b7b9cb5a6955fd059eeb Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-11-25tree wide: Rename VBOOT_MEASURED_BOOT* to TPM_MEASURED_BOOTPatrick Georgi
This follows commit c79e96b4eb3 which did the rename across the tree except in these places. Remove the flag from CHROMEOS abuild builds because it never really belonged there. Change-Id: If98fa27f64d6b676d3edf68ba6fbaacf7ac422e4 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79258 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-11-24soc/amd/genoa: Hook up microcode updatingArthur Heymans
Also update the regular expression to find the genoa blobs. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Iba0109c049019a22cba1e0358cedbd9c198c6569 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-24mb/google/nissa: make GPP_F17 edge triggered to avoid spamming ECScott Chao
In nissa platform, we configured GPP_F17 as SCI+APIC to wake the system and also generate IRQ to the IOAPIC. Currently, we set GPP_F17 to level triggered and it causes AP (Application Processor) to keep sending GET_NEXT_EVENT to EC during resume from suspend by connecting AC. So we change GPP_F17 to edge triggered to avoid this condition. BUG=b:308716748 TEST=Original failure rate was 7 out of 10 times and it reduced to 0 out of 60 times on six joxer systems. Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I3ceb1dfce46376a6a9a8c6cb6d691d818a0a42ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/79244 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-11-23arch/riscv/romstage: Start from assemblyArthur Heymans
Without this it would use the exception handler from the previous stage. Change-Id: I79d875aca6cd0cffe482e4ebb5f388af0adf6aed Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68840 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-23acpigen.c: Add resource consumer functions for mmioArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Id9e4adcd976e1f56ef7f502d9df16dbefce95c3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79217 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-23mb/google/nissa/var/quandiso: Disable un-used C1 port by daughterboardRobert Chen
Probe usb ports by FW_CONFIG setting to disable C1 port on quandiso new daughterboard without C1 port. BUG=b:312094048 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I6f702f60c772176e80b3452bf957d10625564102 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79173 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-22mb/asus/p8z77-m: Ensure RAM stays powered in ACPI S3 suspendKeith Hui
Enable 3VSBSW# in NCT6779D super I/O like other variants in the family, needed to maintain power to memory during S3 suspend. Without it resuming totally fails. (Enabling it in devicetree is OK; it needs not be done in early board init.) TEST=Resuming from S3 works. Change-Id: Ia8059b2a263ab5c459e54685f046eeb913776473 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78205 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kevin Keijzer <kevin@quietlife.nl> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-22mb/google/nissa/var/craaskov: Add 6W and 15W DPTF parametersVan Chen
The DPTF parameters were defined by the thermal team. Based on thermal table in 290705146#comment17. BUG=b:290705146 BRUNCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I02b4187000eec9990bf10a57875b23007f7bdd12 Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79183 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-22mb/google/rex: Enable FSP logo rendering for all Rex variantsSubrata Banik
This patch enables the FSP (Firmware Splash Screen) rendering feature for all Rex variants, including chromeboxes like Ovis. This will allow users to see the FSP logo during the boot process. BUG=b:284799726 TEST=Verify that the FSP logo is displayed during the boot process on an google/ovis chromebox. Change-Id: I73d82e16f70ffdc8cb168506c86d9c4e9a92c38d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-22mb/google/rex/var/karis: Set pen detect pin to NC for non-stylus skuTyler Wang
Set pen detect pin to NC base on fw_config. BUG=b:304680060 TEST=emerge-rex coreboot pass Change-Id: Icf9171fca49cfed1a05a67ae7fc8d62b7e9630c9 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79213 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-22soc/amd/genoa: add I2C supportFelix Held
The Genoa SoC has 6 I2C controllers. In order to support those, select SOC_AMD_COMMON_BLOCK_I2C and implement the SoC-specific functions and data structures needed by the common AMD I2C code. Since the common AMD I2C code also reports if the controller is enabled or not in the SSDT, change the corresponding DSDT code to use this information. In this patch the I2C pad control registers don't get configured by coreboot yet and we rely on ABL already having those set up correctly which seems to be an assumption that the reference firmware is making too. PPR #55901 Rev 0.26 was used as a reference for the I2C controllers and the GPIO pins being used. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iebc10de6ea5c6d441cff04e016dcec62405078c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-11-22vboot: Add catchall recovery reason for unspecified phase 4 errorsJulius Werner
The code for "phase 4" of firmware verification currently only sets a recovery reason when there's an actual hash mismatch detected in vb2api_check_hash_get_digest(). This is the most likely way how this section of code can fail but not the only one. If any other unexpected issue occurs, we should still set a recovery reason rather than just reboot and risk an infinite boot loop. This patch adds a catchall recovery reason for any error code that falls out of this block of code. If a more specific recovery reason had already been set beforehand, we'll continue to use that -- if not, we'll set VB2_RECOVERY_FW_GET_FW_BODY. Change-Id: If00f00f00f00aa113e0325aad58d367f244aca49 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78866 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-22google/*: Clean up Kconfg board selection for Google MTK boardsJulius Werner
This patch tries to standardize and simplify the Kconfig option layout for Google boards with MediaTek SoCs and align them to the scheme used with other Arm-based Google boards. Change-Id: I40880e7609ba703d0053ad01da742871e54d4e7a Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79063 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-11-22google/*: Clean up Kconfig board selection for non-MTK Google Arm boardsJulius Werner
This patch unifies and simplifies the Kconfig selection model for the Gru, Herobrine, Trogdor and Veyron boards according to the model discussed in CB:78972. Also add missing license headers to two Kconfig files while I'm here. Change-Id: If679a05afd10869afba9c2a33b54862e102b5f40 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79022 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-21mb/hp/280_g2: Restore comments documenting root port devicesFelix Singer
While transitioning the devicetree to make use of the chipset devicetree, commit 3b5b9f4c543c ("mb/hp/280_g2: Make use of the chipset devicetree") removed useful comments documenting the endpoints of the root ports. Restore them. Change-Id: I178cb472a8f40baaccc30514689bda2730dfa9dc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-11-21soc/intel/mtl: Keep SOC_INTEL_COMMON_BASECODE_RAMTOP for non-ChromeOSSubrata Banik
This patch guarantees that non-ChromeOS platforms continue to enable early caching. ChromeOS devices, on the other hand, control this configuration through the motherboard configuration based on the underlying SoC. BUG=b:306677879 TEST=Enable SOC_INTEL_COMMON_BASECODE_RAMTOP for google/rex. Change-Id: I412b2b6a807dc0f5f2632f0fbd56bd37689dead3 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-11-21mb/{google,intel}/{rex,mtlrvp}: Enable SOC_INTEL_COMMON_BASECODE_RAMTOPSubrata Banik
This patch enables the `SOC_INTEL_COMMON_BASECODE_RAMTOP` config option for select mainboards, as not all board variants may want to enable this config due to underlying SoC dependencies. Mainboards that attempt to enable early caching have exhibited soft hangs while switching between pre-RAM and post-RAM phases. This patch allows mainboards to choose to enable this option without enabling it by default (which could cause boot hangs). Furthermore, it reorganizes the configuration options under BOARD_GOOGLE_BASEBOARD_REX in alphabetical order for better readability. BUG=b:306677879 TEST=Enable SOC_INTEL_COMMON_BASECODE_RAMTOP for google/rex and intel/mtlrvp. Change-Id: If380c2ecbee4f6437c3d58bfb55be076a4902997 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-11-21mb/google/nissa/var/joxer: Add speaker ldo configTerry Chen
Follow thermal validation, add ldo output select for speaker. BUG=b:297298847 TEST=emerge-nissa and deploy to DUT to verify audio functionality. Change-Id: Ie68f2b35f024b4dd066d831ae8fd5a662d407753 Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-21mb/google/byra/var/*: Set LAN device type back to pciMatt DeVillier
This partially reverts commit f493857c9bc1 ("mb/google/brya/var/*: Set dGPU/LAN/WLAN device type to generic"). Setting the LAN device type to generic broke programming the LAN MAC address, so set it back to pci. TEST=build/boot google/brya (osiris), verify LAN MAC address programmed correctly. Change-Id: I4fb43b7212e67b5c38724baad572860bc45b558e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79150 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-21mb/google/puff/var/*: Set LAN device type back to pciMatt DeVillier
This mostly reverts commit 6c705e766f7f ("mb/google/puff/var/*: Set LAN/WLAN device type to generic"). Setting the LAN device type to generic broke programming the LAN MAC address, so set it back to pci. TEST=build/boot google/puff (wyvern), verify LAN MAC address programmed correctly. Change-Id: I558ae6dc1366d5a8a22e0383d7d597d15159df03 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-20acpi: Optimize enum acpi_tables layoutNaresh Solanki
Arrange ACPI table enum in a vertical and alphabetized format. This change aims to reduce conflicts between patches. Change-Id: I192339df771d6a3ae67358fe46334fe2b216b974 Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79099 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-20nb/intel/sandybridge: Use SA devid to identify PC typePatrick Rudolph
Instead of using MSR IA32_PLATFORM_ID read the SystemAgent device id to figure out the PC type. This follows the BWG which suggest to not use MSR IA32_PLATFORM_ID for system identification. Tested: Lenovo X220 still boots. Change-Id: Ibddf6c75d15ca7a99758c377ed956d483abe7ec1 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78826 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-11-20cpu/intel/model_206ax: Lock MSR_PP_CURRENT_CONFIGPatrick Rudolph
Now that those registers are only written once set the lock bit to protect it from runtime changes. TEST: Lenovo X220 still boots. Change-Id: I4c56a3cb322a0e75eb3dd366808068093928e10c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-11-20cpu/intel/model_206ax: Write MSRs in scope package only oncePatrick Rudolph
Write MSRs that are in scope package only once by checking for the BSP bit. While this improves performance a bit it also has the benefit that registers can be safely locked down without the need for semaphores. TEST: Lenovo X220 still boots. Change-Id: I43f5d62d782466d2796c1df6015d43c0fbf9d031 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-11-20nb/intel/sandybridge: Fix unitialized variable issueJeremy Compostella
commit 1e9601c5ef80 ("nb/intel/sandybridge: Standardize MRC vs. native SPD mapping API") introduced an uninitialized variable issue. Change-Id: I41b081dc4c961acc04423067e29e0eabe5f17539 Found-by: Coverity CID 1524317 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79093 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2023-11-20mb/goog/brya/var/brya0/skolas: Disable HPS GPIOs if HPS_ABSENTNick Vaccaro
Check FW_CONFIG and disable gpios for HPS if HPS_ABSENT for skolas and brya0 variants. BUG=b:311740746 BRANCH=firmware-brya-14505.B TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot skolas to kernel and verify via "cbmem -c | grep HPS". Change-Id: I8cbe4f40c41f1d06e8f511c3e88c05984566d441 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-20mb/goog/brya/var/brya0/skolas: Disable LTE GPIOs if LTE_ABSENTNick Vaccaro
Check FW_CONFIG and disable gpios for LTE if LTE_ABSENT for skolas and brya0 variants. BUG=b:311459627 BRANCH=firmware-brya-14505.B TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot skolas to kernel and verify LTE gpios are disabled via "cbmem -c | grep LTE". Change-Id: I3f3bc2b536babf71cc484cce02f96f47707f729c Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79122 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-20mb/goog/brya/var/skolas: sync slolas overridetree with brya0Nick Vaccaro
Skolas uses brya0 schematic, so override tree should be almost the same for brya0 and skolas. This change sync's the skolas overridetree.cb with brya0's overridetree.cb. BUG=b:311722825 BRANCH=firmware-brya-14505.B TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot skolas to kernel. Change-Id: I14a2ed803a8ffb8614018af587c66034fb724b38 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-20sbom/Makefile.inc: Change GOPATHMaximilian Brune
This changes the path where go installs its packages. Now the packages are not installed in the users home directory anymore. This solution is not perfect though, since offline build are still not possible, because go will fetch the packages at build time. -modcacherw will create the go files with rw permissions, otherwise coreboot is not able to delete the files afterwards (make distclean). Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I2a35369628454057ea4758cd1225e57f07cb71c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-20mb/google/geralt: Remove unnecessary delay for MIPI panelYidi Lin
According to eDP panel datasheet[1], the eDP panel needs 0 <= x <=200ms delay after VDD powering on. The MIPI panel[2] does not need this delay. Move this delay to eDP path. [1] NE135FBM-N41 V8.0 Product Spec_P2 20191025.pdf [2] B5 TV110C9M-LL0 Product Specification Rev.P0 BRANCH=none BUG=none TEST=check FW screen TEST=check timestamp Before: 60:device initialization 696,422 (1) 15:starting LZMA decompress (ignore for x86) 696,587 (165) 16:finished LZMA decompress (ignore for x86) 696,675 (88) 17:starting LZ4 decompress (ignore for x86) 1,340,226 (643,551) After: 60:device initialization 724,259 (1) 15:starting LZMA decompress (ignore for x86) 724,425 (166) 16:finished LZMA decompress (ignore for x86) 724,512 (87) 17:starting LZ4 decompress (ignore for x86) 1,168,176 (443,664) Change-Id: I92bca5ec8269f4bad4dfab4ee193cdb5665de233 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79109 Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-11-18sb/intel/bd82x6x: assign PCH HDA controller ops in chipset devicetreeFelix Held
Since the HD audio controller in the PCH are always on the same device functions, the device operations can be statically assigned in the devicetree and there's no need to bind the host bridge device operations to the PCI device during runtime via a list of PCI IDs. TEST=Lenovo X220 still boots to Linux and audio still works Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com> Change-Id: I9bbbe9f4490dc6fb21174d63d1c8906d69ea3ee0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79118 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-18sb/intel/bd82x6x: assign PCIe root port ops in chipset devicetreeFelix Held
Since the PCIe root ports in the PCH are always on the same device functions, the device operations can be statically assigned in the devicetree and there's no need to bind the host bridge device operations to the PCI device during runtime via a list of PCI IDs. TEST=Lenovo X220 still boots to Linux and all PCIe devices on PCH are visible and working. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com> Change-Id: I05bfe8db88fd54415f320f32ea147636ca4e0df8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2023-11-18nb/intel/sandybridge: assign gma ops in chipset devicetreeFelix Held
Since the integrated GPU is always function 0 of device 2 on bus 0, the device operations can be statically assigned in the devicetree and there's no need to bind the host bridge device operations to the PCI device during runtime via a list of PCI IDs. TEST=Lenovo X220 still boots to Linux and graphics works in UEFI Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com> Change-Id: I20e387e626e19dc441aceda18451186d1e86cd5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/79114 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-18nb/intel/sandybridge: assign host bridge ops in chipset devicetreeFelix Held
Since the host bridge is always function 0 of device 0 on bus 0, the device operations can be statically assigned in the devicetree and there's no need to bind the host bridge device operations to the PCI device during runtime via a list of PCI IDs. TEST=Lenovo X220 still boots to Linux Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com> Change-Id: Icf3d9f8cd2be2f8ef71fd9fdb5f005f3b683332e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79113 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2023-11-18mb/google/brox: Use Ti50 configShelley Chen
Brox is using Ti50, so make sure that we set the right config for that. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: If4a16448eebc028b2989c1de150b9e0f9067ee92 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-11-18mb/google/brox: Fix GPIO assignments in gpio.hShelley Chen
Assigning the macros in gpio.h to the correct GPIOs. Also, fixing GPE configurations so that they are mapped to the proper wake sources (GPP_B, D, E groups). BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I6320cd98e560e514e63c52e173cb7923cfd1cdee Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-11-18qualcomm/sc7180: Move QCSDI and increase romstage size by 4KBJulius Werner
We need to increase romstage size a little to make a compiler upgrade fit (CB:70771). Unfortunately the end of the romstage directly touches the QCSDI region in the current memlayout, and there is no other way to reshuffle things to make more space... so we need to move QCSDI out of the way. This means that anyone who is actually building this platform with CONFIG_QC_SDI_ENABLE (which requires a proprietary blob that's not publicly available) will need to recompile their QCSDI binary to match the new start address. Change-Id: Iaf13e4001b3c763e3ec59009779931ec75603d5d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79074 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-11-17mb/google/herobrine: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I25b7adccf60abe515d129f8d00383165eccf6431 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79028 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-17mb/google/trogdor: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I30a15277527a1e423691ff55ff11cc2136cefc90 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-17soc/qualcomm/{sc7180,sc7280}: Allow building without QC blobs repoFelix Singer
Building coreboot for the Qualcomm SoCs SC7180 and SC7280 requires to include the Qualcomm blobs, which requires to accept their license. However, for various reasons it makes sense to build without blobs, e.g. static analysis or just build-testing. So in order to do that, run the steps integrating the Qualcomm blobs into the coreboot binary only if USE_QC_BLOBS is enabled and also remove guards which prevent building related mainboards when USE_QC_BLOBS is not enabled. Change-Id: I249ac477b8f10e7fa0848e967c23a3b3b9bbd27d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79026 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-17nb/amd/pi/00730F01: add CPU and domain ops in devicetreeFelix Held
Add the CPU and PCI domain operation bindings statically in the chipset devicetree instead of adding them during runtime. TEST=PC Engines APU2 still boots and doesn't show any new problems Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I44fa57458c408e74a6341643620c5e9ac1817557 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-11-17nb/amd/pi/00730F01: restructure chip opsFelix Held
Since this chip is a SoC and also to bring the chipset devicetree more in line with the chipset devicetree of Sandy Bridge, merge the chip operations of the northbridge's root complex and the northbridge itself into one chip operations structure and use it at the top level of the devicetree. TEST=PC Engines APU2 still boots and doesn't show any new problems Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8b42bac07b1409bbc797bc4428cf9f84a40e94c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-11-17nb/amd/pi/00730F01: introduce and use chipset devicetreeFelix Held
BKDG #52740 Rev 3.05 was used as a reference for the SoC's various PCI devices. The HDA controller in the FCH at function 2 of device 0x14 on bus 0 was missing in the mainboard's devicetrees. TEST=PC Engines APU2 still boots and doesn't show any new problems Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6970c2f6e6d661d40406586f4e6eeb05bcd07979 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79083 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-11-17include/device/device: drop HAVE_ACPI_TABLES guardsFelix Held
There's no need to remove the corresponding fields from the device_operations struct when HAVE_ACPI_TABLES isn't selected. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iac20b6cdc44a5280566ee7003a5ef6fbe913b099 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78990 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-17include/device/device: drop GENERATE_SMBIOS_TABLES guardsFelix Held
There's no need to remove the corresponding fields from the device_operations struct when GENERATE_SMBIOS_TABLES isn't selected. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifa24d1fd211c263b788046e63de3dd5c54cba801 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-11-17mb/google/corsola: Configure I2C and I2S interface for ALC5650wuyang5
Configure I2S1 and I2C5 for ALC5650 to support beep sound in depthcharge. BRANCH=corsola BUG=b:305828247 TEST=Verify devbeep in depthcharge console Change-Id: Ibd098adb8d5568ad338bbfece0edfd0c38cbf854 Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79064 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-11-17mb/google/zork/morphius: Drop touchscreen detectionMatt DeVillier
Morphius boards using pre-v3.6 schematics don't have a dedicated GPIO for touchscreen power/enable, and so fail with runtime detection enabled. Since it only has one touchscreen option, and no SKUs lack a touchscreen, we can safely assume it is present in all cases. TEST=build/boot morphius w/4k screen, verify touchscreen enabled in cbmem and functional in Linux and Windows. Change-Id: I13e07e14b5a18fa1dd3b18950cf46e9d7821eedc Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-16ec/google/chromeec: Update ec_cmd_api.h and ec_commands.hSimon Glass
Generated using update_ec_headers.sh [EC-DIR]. The original include/ec_commands.h version in the EC repo is: ab9b64ac4c Add a host command to print info about AP-firmware state The original include/ec_cmd_api.h version in the EC repo is: ab9b64ac4c Add a host command to print info about AP-firmware state BUG=b:300525571 BRANCH=none TEST=none Change-Id: I3570e073a91621cb1d28a24aa35c1f4beedceaab Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79066 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-16acpi/device: Only return dev->ops->acpi_name if non-NULLCoolStar
Returning a NULL device name can cause issues if something else does handle it. E.g. UART and GNA devices on Intel Alder Lake-N cause INTERNAL_POWER_ERROR BSOD's in Windows when enabled due to invalid packages being created from a NULL name Test: build/boot google/nissa (craaskvin) to Win11 Change-Id: I0679147ad3e330d706bbf97c30bc11b2432e2e8a Signed-off-by: CoolStar <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-11-16mb/google/skyrim/frostflow: Drop GPIO override for camera shutterMatt DeVillier
Appears to not be used under Windows, Linux, or ChromeOS, and causes high CPU usage at idle under Windows. BUG=none TEST=build/boot Win11, Linux on google/frostflow, verify camera shutter function unchanged, CPU usage under Windows idles where expected. Change-Id: I8a6ea3b886766bdb055b40949c75bec0264eecc5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-16mb/system76/rpl: Allow 5600 MT/s memory for RPL-HXMatt Parnell
System76 only sells units with memory speeds up to 5200 MT/s, but the i9-13900HX supports up to 5600 MT/s memory. Tested by running memtest and checking dmidecode reports 5600 MT/s when using 2x16 GB 5600 MT/s Crucial SODIMMs (CT2K16G56C46S5) on addw3, bonw15, serw13. Change-Id: I9bb0435769c70c1db06d2c5cca2dd28eb5331f49 Signed-off-by: Matt Parnell <mparnell@gmail.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Tested-by: Levi Portenier <levi@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78912 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-16mb/supermicro/x11: Make use of chipset devicetreeFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: I5176aa56ecaa52d0f42455bc7176b0415a6199ec Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78594 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-16mb/google/geralt: Disable SD card support for CiriRuihai Zhou
According to proto schematics, the SD card is removed. BUG=b:308968270 TEST=emerge-geralt coreboot BRANCH=None Change-Id: Id4e021e7896d093560f39c40573ac616d76438c2 Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-11-16mb/google/geralt: Move backlight-related functions to common panel.cRuihai Zhou
These backlight related functions can be reused in other variants, move them out to the panel.c. Also the panel_geralt.c should be used for Geralt, enable it on Geralt board only. BUG=b:308968270 TEST=emerge-geralt coreboot BRANCH=None Change-Id: I5d4035d5f480551c428c450826e23bf77f2fe08a Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78955 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
2023-11-16lib/device_tree.c: Fix print_propertyMaximilian Brune
This uses the size attribute to traverse the possible string. This patch traverses the entire property for non printable characters and not just until the first 0 is hit. Now numbers that start with a zero (memory wise) are not falsely recognized as strings: before the patch: clock-frequency = ""; after the patch: clock-frequency = < 0x1c2000 >; Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I229c07b76468fe54f90fa9df12f103d7c7c2859d Reviewed-on: https://review.coreboot.org/c/coreboot/+/78025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 00:26:11 +0000