diff options
| author | Robert Chen <robert.chen@quanta.corp-partner.google.com> | 2023-11-20 01:39:00 -0500 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-11-23 13:11:29 +0000 |
| commit | 39b19f270c717dbf4b3c947341cb3f2f239eabe6 (patch) | |
| tree | 2e0982c471bbd6d33423716121f7b6def1ecdc21 /src | |
| parent | e94d7d8264fa77c69e113865e668107143128ccf (diff) | |
mb/google/nissa/var/quandiso: Disable un-used C1 port by daughterboard
Probe usb ports by FW_CONFIG setting to disable C1 port on quandiso new daughterboard without C1 port.
BUG=b:312094048
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I6f702f60c772176e80b3452bf957d10625564102
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79173
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/brya/variants/quandiso/overridetree.cb | 18 |
1 files changed, 15 insertions, 3 deletions
diff --git a/src/mainboard/google/brya/variants/quandiso/overridetree.cb b/src/mainboard/google/brya/variants/quandiso/overridetree.cb index 64cd862d31..29a4cee08c 100644 --- a/src/mainboard/google/brya/variants/quandiso/overridetree.cb +++ b/src/mainboard/google/brya/variants/quandiso/overridetree.cb @@ -442,7 +442,11 @@ chip soc/intel/alderlake chip drivers/intel/pmc_mux/conn use usb2_port2 as usb2_port use tcss_usb3_port2 as usb3_port - device generic 1 alias conn1 on end + device generic 1 alias conn1 on + probe DB_USB DB_1C_1A + probe DB_USB DB_1C + probe DB_USB DB_1C_LTE + end end end end @@ -462,7 +466,11 @@ chip soc/intel/alderlake register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" - device ref tcss_usb3_port2 on end + device ref tcss_usb3_port2 on + probe DB_USB DB_1C_1A + probe DB_USB DB_1C + probe DB_USB DB_1C_LTE + end end end end @@ -482,7 +490,11 @@ chip soc/intel/alderlake register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" - device ref usb2_port2 on end + device ref usb2_port2 on + probe DB_USB DB_1C_1A + probe DB_USB DB_1C + probe DB_USB DB_1C_LTE + end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port A0 (MLB)"" |