diff options
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2023-10-20 14:37:07 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-11-20 14:55:58 +0000 |
| commit | 8685205ad15a0890dfb731a91551256ee41775ec (patch) | |
| tree | bb8b8cc19e57e19295e368c016c8b3403ba5a26a /src | |
| parent | ea04a53e69d25556ac0c290100071d18d1d80cb9 (diff) | |
cpu/intel/model_206ax: Lock MSR_PP_CURRENT_CONFIG
Now that those registers are only written once set the lock bit to
protect it from runtime changes.
TEST: Lenovo X220 still boots.
Change-Id: I4c56a3cb322a0e75eb3dd366808068093928e10c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/intel/model_206ax/model_206ax.h | 2 | ||||
| -rw-r--r-- | src/cpu/intel/model_206ax/model_206ax_init.c | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index ecbf3237d9..9379c29323 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -73,8 +73,10 @@ #define PKG_POWER_LIMIT_TIME_MASK 0x7f #define MSR_PP0_CURRENT_CONFIG 0x601 +#define PP0_CURRENT_LIMIT_LOCK (1U << 31) #define PP0_CURRENT_LIMIT (112 << 3) /* 112 A */ #define MSR_PP1_CURRENT_CONFIG 0x602 +#define PP1_CURRENT_LIMIT_LOCK (1U << 31) #define PP1_CURRENT_LIMIT_SNB (35 << 3) /* 35 A */ #define PP1_CURRENT_LIMIT_IVB (50 << 3) /* 50 A */ #define MSR_PKG_POWER_SKU_UNIT 0x606 diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 14a7965f42..dfe7ae5e4a 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -206,6 +206,7 @@ static void configure_c_states(void) msr = rdmsr(MSR_PP0_CURRENT_CONFIG); msr.lo &= ~0x1fff; msr.lo |= PP0_CURRENT_LIMIT; + msr.lo |= PP0_CURRENT_LIMIT_LOCK; wrmsr(MSR_PP0_CURRENT_CONFIG, msr); /* Secondary Plane Current Limit */ @@ -215,6 +216,7 @@ static void configure_c_states(void) msr.lo |= PP1_CURRENT_LIMIT_IVB; else msr.lo |= PP1_CURRENT_LIMIT_SNB; + msr.lo |= PP1_CURRENT_LIMIT_LOCK; wrmsr(MSR_PP1_CURRENT_CONFIG, msr); } } |