mb/google/brox: Update storage settings for SSD and UFS

Brox has SSD and UFS storage per different SKU.
1. Set SSD on CPU PCIe port (PCIEX4_A) and configure related gpio
settings according to the schematic.
2. Enable UFS, also enable ISH since it is PCI function 0, required
for UFS function 7 to be enabled.
3. Set unused SRCCLKREQ signals to NC.
4. Remove unused gpio settings in variant gpio table to prevent
unexpected overrides.

BUG=b:311450057
BRANCH=None
TEST=emerge-brox coreboot

Change-Id: I88922bcfa13652006aa10078c3c444624fd4575e
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79295
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

4 files changed, 38 insertions, 220 deletions

diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig
index f6f33b6773..74bea817e3 100644
--- a/src/mainboard/google/brox/Kconfig
+++ b/src/mainboard/google/brox/Kconfig
@@ -47,6 +47,7 @@ config BOARD_GOOGLE_BASEBOARD_BROX
 	select SOC_INTEL_CRASHLOG
 	select SOC_INTEL_RAPTORLAKE
 	select SOC_INTEL_ALDERLAKE_PCH_P
+	select DRIVERS_INTEL_ISH
 	select SYSTEM_TYPE_LAPTOP
 	select TPM_GOOGLE_TI50
 
diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb
index c8b4c5aeaa..42bf467b9a 100644
--- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb
+++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb
@@ -168,22 +168,21 @@ chip soc/intel/alderlake
 		end
 		device ref heci1 on end
 		device ref sata on end
-		device ref pcie_rp8 on
-			# Enable SD Card PCIE 8 using clk 3
-			register "pch_pcie_rp[PCH_RP(8)]" = "{
-				.clk_src = 3,
+		device ref pcie4_0 on
+			# Enable CPU PCIE RP 1 using CLK 3
+			register "cpu_pcie_rp[CPU_RP(1)]" = "{
 				.clk_req = 3,
-				.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
-			}"
-		end	#PCIE8 SD card
-		device ref pcie_rp9 on
-			# Enable NVMe PCIE 9 using clk 1
-			register "pch_pcie_rp[PCH_RP(9)]" = "{
-				.clk_src = 1,
-				.clk_req = 1,
+				.clk_src = 3,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
-		end	#PCIE9-12 SSD
+		end
+		device ref ish on
+			chip drivers/intel/ish
+				register "add_acpi_dma_property" = "true"
+				device generic 0 on end
+			end
+		end
+		device ref ufs on end
 		device ref uart0 on end
 		device ref gspi1 on end
 		device ref pch_espi on
diff --git a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c
index daf1b96a00..a9095330a3 100644
--- a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c
+++ b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c
@@ -145,12 +145,12 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI_INT(GPP_D3, NONE, PLTRST, LEVEL),
 	/* GPP_D4 : [NF1: IMGCLKOUT0 NF2: BK4 NF5: SBK4 NF6: USB_C_GPP_D4] ==> SOC_GPP_D4 */
 	PAD_NC(GPP_D4, NONE),
-	/* GPP_D5 : SRCCLKREQ0_L ==> PCIE_CLKREQ0_ODL */
-	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+	/* GPP_D5 : SRCCLKREQ0_L ==> NC */
+	PAD_NC(GPP_D5, NONE),
 	/* GPP_D6 : [NF1: SRCCLKREQ1# NF6: USB_C_GPP_D6] ==> WLAN_CLKREQ_ODL */
 	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
-	/* GPP_D7 : SRCCLKREQ2_L ==> PCIE_CLKREQ2_ODL */
-	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
+	/* GPP_D7 : SRCCLKREQ2_L ==> NC */
+	PAD_NC(GPP_D7, NONE),
 	/* GPP_D8 : [NF1: SRCCLKREQ3# NF6: USB_C_GPP_D8] ==> SSD_CLKREQ_ODL */
 	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
 	/* GPP_D9 : [NF1: ISH_SPI_CS# NF2: DDP3_CTRLCLK NF4: TBT_LSX2_TXD NF5: BSSB_LS2_RX NF6: USB_C_GPP_D9 NF7: GSPI2_CS0#] ==> USB_C2_LSX_TX */
@@ -158,7 +158,7 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_D10 : [NF1: ISH_SPI_CLK NF2: DDP3_CTRLDATA NF4: TBT_LSX2_RXD NF5: BSSB_LS2_TX NF6: USB_C_GPP_D10 NF7: GSPI2_CLK] ==> USB_C2_LSX_RX_STRAP */
 	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF4),
 	/* GPP_D11 : [] ==> EN_PP3300_SSD */
-	PAD_CFG_GPO(GPP_D11, 0, DEEP),
+	PAD_CFG_GPO(GPP_D11, 1, DEEP),
 	/* GPP_D12 : [NF1: ISH_SPI_MOSI NF2: DDP4_CTRLDATA NF4: TBT_LSX3_RXD NF5: BSSB_LS3_TX NF6: USB_C_GPP_D12 NF7: GSPI2_MOSI] ==> SOC_GPP_D12 */
 	PAD_NC(GPP_D12, DN_20K),
 	/* GPP_D13 : [NF1: ISH_UART0_RXD NF3: I2C6_SDA NF6: USB_C_GPP_D13] ==> UART0_ISH_RX_DBG_TX */
@@ -261,8 +261,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_F17, NONE, DEEP, NF3),
 	/* GPP_F18 : [NF3: THC1_SPI2_INT# NF6: USB_C_GPP_F18] ==> TCHSCR_INT_ODL */
 	PAD_CFG_NF(GPP_F18, NONE, DEEP, NF3),
-	/* GPP_F19 : SRCCLKREQ6 ==> PCIE_CLKREQ5_ODL */
-	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+	/* GPP_F19 : SRCCLKREQ6 ==> NC */
+	PAD_NC(GPP_F19, NONE),
 	/* GPP_F20 : [NF1: Reserved NF6: USB_C_GPP_F20] ==> SOC_GPP_F20 */
 	PAD_NC(GPP_F20, NONE),
 	/* GPP_F21 : [NF1: Reserved NF6: USB_C_GPP_F21] ==> SOC_GPP_F21 */
@@ -306,16 +306,16 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
 	/* GPP_H18 : [NF1: PROC_C10_GATE# NF6: USB_C_GPP_H18] ==> CPU_C10_GATE_L */
 	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
-	/* GPP_H19 : SRCCLKREQ4_L ==> PCIE_CLKREQ4_ODL */
-	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
+	/* GPP_H19 : SRCCLKREQ4_L ==> NC */
+	PAD_NC(GPP_H19, NONE),
 	/* GPP_H20 : IMGCLKOUT1 ==> BOARD_ID7 */
 	PAD_CFG_GPI(GPP_H20, NONE, DEEP),
 	/* GPP_H21 : [NF1: IMGCLKOUT2 NF6: USB_C_GPP_H21] ==> SOC_GPP_H21 */
 	PAD_NC(GPP_H21, NONE),
 	/* GPP_H22 : IMGCLKOUT3 ==> BOARD_ID8 */
 	PAD_CFG_GPI(GPP_H22, NONE, DEEP),
-	/* GPP_H23 : SRCCLKREQ5_L ==> PCIE_CLKREQ5_ODL */
-	PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1),
+	/* GPP_H23 : SRCCLKREQ5_L ==> NC */
+	PAD_NC(GPP_H23, NONE),
 
 	/* GPP_R0 : [NF1: HDA_BCLK NF2: I2S0_SCLK NF3: DMIC_CLK_B0 NF4: HDAPROC_BCLK] ==> HDA_HP_BCLK_R */
 	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
@@ -371,14 +371,26 @@ const struct pad_config *__weak variant_gpio_override_table(size_t *num)
 
 /* Early pad configuration in bootblock */
 static const struct pad_config early_gpio_table[] = {
+	/* GPP_D11 : [] ==> EN_PP3300_SSD */
+	PAD_CFG_GPO(GPP_D11, 1, DEEP),
 	/* GPP_E2  : THC0_SPI1_IO3 ==> GSC_PCH_INT_ODL */
 	PAD_CFG_GPI_APIC_LOCK(GPP_E2, NONE, LEVEL, INVERT, LOCK_CONFIG),
 	/* GPP_E8 : GPP_E8 ==> PCH_WP_OD */
 	PAD_CFG_GPI_LOCK(GPP_E8, NONE, LOCK_CONFIG),
+	/* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_F9, 0, DEEP),
+	/* F21 : EXT_PWR_GATE2# ==> NC */
+	PAD_NC(GPP_F21, NONE),
 	/* GPP_H8 : [NF1: I2C4_SDA NF2: CNV_MFUART2_RXD NF6: USB_C_GPP_H8] ==> PCH_I2C_GSC_SDA */
 	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
 	/* GPP_H9 : [NF1: I2C4_SCL NF2: CNV_MFUART2_TXD] ==> PCH_I2C_GSC_SCL */
 	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
+	/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> MEM_CH_SEL */
+	PAD_CFG_GPI(GPP_S0, NONE, DEEP),
 };
 
 const struct pad_config *__weak variant_early_gpio_table(size_t *num)
diff --git a/src/mainboard/google/brox/variants/brox/gpio.c b/src/mainboard/google/brox/variants/brox/gpio.c
index 444adc4fa9..5805beeb62 100644
--- a/src/mainboard/google/brox/variants/brox/gpio.c
+++ b/src/mainboard/google/brox/variants/brox/gpio.c
@@ -4,213 +4,19 @@
 #include <boardid.h>
 #include <soc/gpio.h>
 
-static const struct pad_config board_id0_1_overrides[] = {
-	/* B2  : VRALERT# ==> NC */
-	PAD_NC(GPP_B2, NONE),
-	/* B7  : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
-	PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG),
-	/* B8  : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
-	PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG),
-	/* B15 : TIME_SYNC0 ==> NC */
-	PAD_NC(GPP_B15, NONE),
-	/* C3  : SML0CLK ==> NC */
-	PAD_NC(GPP_C3, NONE),
-	/* C4  : SML0DATA ==> NC */
-	PAD_NC(GPP_C4, NONE),
-	/* D13 : ISH_UART0_RXD ==> PCH_I2C_CAM_SDA */
-	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF3),
-	/* D14 : ISH_UART0_TXD ==> PCH_I2C_CAM_SCL */
-	PAD_CFG_NF(GPP_D14, NONE, DEEP, NF3),
-	/* F19 : SRCCLKREQ6# ==> WWAN_SIM1_DET_OD */
-	PAD_CFG_GPI(GPP_F19, UP_20K, DEEP),
-	/* F20 : EXT_PWR_GATE# ==> HPS_RST_R */
-	PAD_CFG_GPO(GPP_F20, 0, DEEP),
-	/* F21 : EXT_PWR_GATE2# ==> WAKE_ON_WWAN_ODL */
-	PAD_NC(GPP_F21, NONE),
-	/* H13 : I2C7_SCL ==> EN_PP3300_SD */
-	PAD_CFG_GPO(GPP_H13, 1, DEEP),
-	/* H21 : IMGCLKOUT2 ==> WLAN_INT_L */
-	PAD_CFG_GPI_APIC(GPP_H21, NONE, DEEP, EDGE_SINGLE, NONE),
-	/* GPD2: LAN_WAKE# ==> NC */
-	PAD_NC(GPD2, NONE),
-};
-
-/* Early pad configuration in bootblock for board id < 2 */
-static const struct pad_config early_gpio_table[] = {
-	/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
-	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
-	/* B7  : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
-	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
-	/* B8  : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
-	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
-	/*
-	 * D1  : ISH_GP1 ==> FP_RST_ODL
-	 * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
-	 * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
-	 * early on in bootblock, followed by enabling of power. Reset signal is deasserted
-	 * later on in ramstage. Since reset signal is asserted in bootblock, it results in
-	 * FPMCU not working after a S3 resume. This is a known issue.
-	 */
-	PAD_CFG_GPO(GPP_D1, 0, DEEP),
-	/* D2  : ISH_GP2 ==> EN_FP_PWR */
-	PAD_CFG_GPO(GPP_D2, 1, DEEP),
-	/* E0  : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */
-	PAD_CFG_GPO(GPP_E0, 0, DEEP),
-	/* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
-	PAD_CFG_GPI(GPP_E13, NONE, DEEP),
-	/* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage) */
-	PAD_CFG_GPO(GPP_E16, 0, DEEP),
-	/* E15 : RSVD_TP ==> PCH_WP_OD */
-	PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
-	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
-	PAD_CFG_GPI(GPP_F18, NONE, DEEP),
-	/* F21 : EXT_PWR_GATE2# ==> NC */
-	PAD_NC(GPP_F21, NONE),
-	/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
-	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
-	/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
-	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
-	/* H13 : I2C7_SCL ==> EN_PP3300_SD */
-	PAD_CFG_GPO(GPP_H13, 1, DEEP),
-};
-
-/* Early pad configuration in bootblock for board id 2 */
-static const struct pad_config early_gpio_table_id2[] = {
-	/* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */
-	PAD_CFG_GPO(GPP_A12, 1, DEEP),
-	/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
-	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
-	/* B4  : PROC_GP3 ==> SSD_PERST_L */
-	PAD_CFG_GPO(GPP_B4, 0, DEEP),
-	/* B7  : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
-	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
-	/* B8  : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
-	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
-	/*
-	 * D1  : ISH_GP1 ==> FP_RST_ODL
-	 * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
-	 * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
-	 * early on in bootblock, followed by enabling of power. Reset signal is deasserted
-	 * later on in ramstage. Since reset signal is asserted in bootblock, it results in
-	 * FPMCU not working after a S3 resume. This is a known issue.
-	 */
-	PAD_CFG_GPO(GPP_D1, 0, DEEP),
-	/* D2  : ISH_GP2 ==> EN_FP_PWR */
-	PAD_CFG_GPO(GPP_D2, 1, DEEP),
-	/* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
-	PAD_CFG_GPO(GPP_D11, 1, DEEP),
-	/* E0  : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */
-	PAD_CFG_GPO(GPP_E0, 0, DEEP),
-	/* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
-	PAD_CFG_GPI(GPP_E13, NONE, DEEP),
-	/* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage) */
-	PAD_CFG_GPO(GPP_E16, 0, DEEP),
-	/* E15 : RSVD_TP ==> PCH_WP_OD */
-	PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
-	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
-	PAD_CFG_GPI(GPP_F18, NONE, DEEP),
-	/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */
-	PAD_CFG_GPO(GPP_F21, 0, DEEP),
-	/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
-	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
-	/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
-	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
-	/* H13 : I2C7_SCL ==> EN_PP3300_SD */
-	PAD_NC(GPP_H13, UP_20K),
-};
-
-/* Early pad configuration in bootblock for board id 4 */
-static const struct pad_config early_gpio_table_id4[] = {
-	/* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */
-	PAD_CFG_GPO(GPP_A12, 1, DEEP),
-	/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
-	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
-	/* B4  : PROC_GP3 ==> SSD_PERST_L */
-	PAD_CFG_GPO(GPP_B4, 0, DEEP),
-	/* H6  : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
-	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
-	/* H7  : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
-	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
-	/*
-	 * D1  : ISH_GP1 ==> FP_RST_ODL
-	 * FP_RST_ODL comes out of reset as hi-z and does not have an external
-	 * pull-down. To ensure proper power sequencing for the FPMCU device,
-	 * reset signal is driven low early on in bootblock, followed by
-	 * enabling of power. Reset signal is deasserted later on in ramstage.
-	 * Since reset signal is asserted in bootblock, it results in FPMCU not
-	 * working after a S3 resume. This is a known issue.
-	 */
-	PAD_CFG_GPO(GPP_D1, 0, DEEP),
-	/* D2  : ISH_GP2 ==> EN_FP_PWR */
-	PAD_CFG_GPO(GPP_D2, 1, DEEP),
-	/* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
-	PAD_CFG_GPO(GPP_D11, 1, DEEP),
-	/* E0  : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */
-	PAD_CFG_GPO(GPP_E0, 0, DEEP),
-	/* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
-	PAD_CFG_GPI(GPP_E13, NONE, DEEP),
-	/* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage) */
-	PAD_CFG_GPO(GPP_E16, 0, DEEP),
-	/* E15 : RSVD_TP ==> PCH_WP_OD */
-	PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
-	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
-	PAD_CFG_GPI(GPP_F18, NONE, DEEP),
-	/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */
-	PAD_CFG_GPO(GPP_F21, 0, DEEP),
-	/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
-	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
-	/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
-	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
-	/* H13 : I2C7_SCL ==> EN_PP3300_SD */
-	PAD_NC(GPP_H13, UP_20K),
-};
 
 static const struct pad_config romstage_gpio_table[] = {
-	/* B4  : PROC_GP3 ==> SSD_PERST_L */
-	PAD_CFG_GPO(GPP_B4, 1, DEEP),
 
-	/* Enable touchscreen, hold in reset */
-	/* C0  : SMBCLK ==> EN_PP3300_TCHSCR */
-	PAD_CFG_GPO(GPP_C0, 1, DEEP),
-	/* C1  : SMBDATA ==> USI_RST_L */
-	PAD_CFG_GPO(GPP_C1, 0, DEEP),
-
-	/* D1  : ISH_GP1 ==> FP_RST_ODL */
-	PAD_CFG_GPO(GPP_D1, 0, DEEP),
-	/* D2  : ISH_GP2 ==> EN_FP_PWR */
-	PAD_CFG_GPO(GPP_D2, 0, DEEP),
-
-	/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */
-	PAD_CFG_GPO(GPP_F21, 1, DEEP),
+	/* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_F9, 1, DEEP),
 };
 
 const struct pad_config *variant_gpio_override_table(size_t *num)
 {
-	const uint32_t id = board_id();
-	if (id == BOARD_ID_UNKNOWN || id < 2) {
-		*num = ARRAY_SIZE(board_id0_1_overrides);
-		return board_id0_1_overrides;
-	}
-
 	*num = 0;
 	return NULL;
 }
 
-const struct pad_config *variant_early_gpio_table(size_t *num)
-{
-	const uint32_t id = board_id();
-	if (id == BOARD_ID_UNKNOWN || id < 2) {
-		*num = ARRAY_SIZE(early_gpio_table);
-		return early_gpio_table;
-	} else if (id >= 4) {
-		*num = ARRAY_SIZE(early_gpio_table_id4);
-		return early_gpio_table_id4;
-	}
-
-	*num = ARRAY_SIZE(early_gpio_table_id2);
-	return early_gpio_table_id2;
-}
-
 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 {
 	*num = ARRAY_SIZE(romstage_gpio_table);