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2022-06-22mb/google/brya/var/kinox: Refactoring update_power_limits functionDtrain Hsu
Based on 'commit 0b917bde36a7 ("mb/google/brya/var/kinox: Set power limit based on charger type")' to refactoring update_power_limits function for kinox. BUG=b:231911918 TEST=Build and boot to Chrome OS Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I1fcb593090f95bf23808e577dd11b8a836f47494 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-06-22security/vboot: Deprecate VBOOT_VBNV_ECYu-Ping Wu
Boards using VBOOT_VBNV_EC (nyan, daisy, veyron, peach_pit) are all ChromeOS devices and they've reached the end of life since Feb 2022. Therefore, remove VBOOT_VBNV_EC for them, each with different replacement. - nyan (nyan, nyan_big, nyan_blaze): Add RW_NVRAM to their FMAP (by reducing the size of RW_VPD), and replace VBOOT_VBNV_EC with VBOOT_VBNV_FLASH. - veyron: Add RW_NVRAM to their FMAP (by reducing the size of SHARED_DATA), and replace VBOOT_VBNV_EC with VBOOT_VBNV_FLASH. Also enlarge the OVERLAP_VERSTAGE_ROMSTAGE section for rk3288 (by reducing the size of PRERAM_CBMEM_CONSOLE), so that verstage won't exceed its allotted size. - daisy: Because BOOT_DEVICE_SPI_FLASH is not set, which is required for VBOOT_VBNV_FLASH, disable MAINBOARD_HAS_CHROMEOS and VBOOT configs. - peach_pit: As VBOOT is not set, simply remove the unused VBOOT_VBNV_EC option. Remove the VBOOT_VBNV_EC Kconfig option as well as related code, leaving VBOOT_VBNV_FLASH and VBOOT_VBNV_CMOS as the only two backend options for vboot nvdata (VBNV). Also add a check in read_vbnv() and save_vbnv() for VBNV options. BUG=b:178689388 TEST=util/abuild/abuild -t GOOGLE_NYAN -x -a TEST=util/abuild/abuild -t GOOGLE_VEYRON_JAQ -x -a TEST=util/abuild/abuild -t GOOGLE_DAISY -a TEST=util/abuild/abuild -t GOOGLE_PEACH_PIT -a BRANCH=none Change-Id: Ic67d69e694cff3176dbee12d4c6311bc85295863 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-06-22mb/google/brya/var/taeko: Modify DPTF setting for tarloJoey Peng
Adjust sensor trigger point and fan duty according to thermal team tuning results. BRANCH=brya BUG=b:215033683 TEST=Built and tested on tarlo board Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Ib543cee82f6940ab35a1a40af1d41bb2b8bf8521 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-22soc/intel/alderlake: add GPIO definitions for PCH-SMichał Kopeć
Add GPIO definitions for ADL-S, similarly to how TGL/TGL-H handles the split. Based on: - Intel PCH-S EDS Vol2 (#621483) - Alderlake-S FSP - slimbootloader sources - Linux alderlake-pinctrl driver Change-Id: I0fd1dc645c19c33bf14424703f966271e884ed3d Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-22soc/amd/picasso/acpi: Add missing UART resourcesMatt DeVillier
Both UART and DMA MMIO regions for each UART are mapped by the UEFI reference code, so do the same here. Without these defined, UART-attached devices fail to correctly initialize under Windows. Change-Id: I0e1af9028c7c1746407e923cebe824a15aeb565e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65233 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-22soc/intel/alderlake: Remove menu option for MAX_PCIE_CLOCK_SRCCliff Huang
MAX_PCIE_CLOCK_SRC is not an user-configurable option. Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: Ia49f6e236e8853c377e9096500d96f21dbdc9b8d Reviewed-on: https://review.coreboot.org/c/coreboot/+/65298 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22soc/intel: Add Meteor Lake SA device IDSubrata Banik
Add Meteor Lake SA device ID 0x7d14 (4+8, 15W). BUG=b:224325352 TEST=Able to build MTL SoC and verified SA DID is now shown proper. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I051a40136ed89e837945bf4569c77d2a80375ed6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65111 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22mb/starlabs/lite/{glk/glkr}: Disable UFS deviceSean Rhodes
Disable 1d.0 UFS as it is not used. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib392bc64db440ea3d98ee62536d5395587a3f6aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/65046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-06-22mb/google/skyrim/variants/baseboard: enable iommuJason Glenesk
With IOMMU disabled, kernel complains that 'IOMMUv2 functionality not available on this system'. Enable iommu in devicetree for skyrim proto board in order to allow kernel to load and initialize IOMMUv2. BUG=b:232750390 TEST=Boot to Chrome OS on skyrim board, and grep dmesg for "AMD IOMMUv2 loaded and initialized" Change-Id: I2f10f5eda8083335619a34c44df253b8e5a8572c Signed-off-by: Jason Glenesk <Jason.Glenesk@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-06-22soc/cannonlake: Hook up Comet Lake U 06-a6-01 microcodeMichał Żygowski
The file is already present in the microcode submodule repository. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ib284908db165dc95a5895979174512818f2aceff Reviewed-on: https://review.coreboot.org/c/coreboot/+/65292 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22mb/intel/adlrvp: Enable early EC sync for ADL-NUsha P
Enable VBOOT_EARLY_EC_SYNC in coreboot. EC Sync was failing on ADL-N RVP since the ec image was not getting stitched into coreboot during emerge build. This is now fixed with https://crrev.com/c/3705002 and hence enabling the EC sync for ADL-N RVP BUG=b:232875824 TEST=Build and boot adlrvp-n. Ensure EC Software sync is complete. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: Ibea37825abd0f13a5184cbbe96c38d44474782f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
2022-06-22soc/intel/mp_init: Skip before_post_cpus_init if !USE_COREBOOT_MP_INITSubrata Banik
This patch ensures all APs finish the task and continue before_post_cpus_init() if coreboot decides to perform multiprocessor initialization using native coreboot drivers instead of using FSP MP PPI implementation. BUG=b:233199592 TEST=Build and boot google/kano to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3b76974ab19323201bf1dca9af423481a40f65c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65173 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22soc/intel/alderlake: Allow possible options for MP InitSubrata Banik
This patch creates choice that lists all possible options to perform MP Init as below: 1. USE_FSP_MP_INIT: Allow coreboot to bring APs from reset and FSP runs feature programming based and selects MP_SERVICES_PPI_V2 config. 2. USE_COREBOOT_MP_INIT: Allow coreboot to perform MP Init (both AP init and feature programming) using native implementation. Additionally, selects required RELOAD_MICROCODE_PATCH when coreboot is expected to run MP Init. Refactor SoC code to allow required FSP UPD override based on selected MP Init option. BUG=b:233199592 TEST=Build and boot google/taeko to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I20adc1935890c4c6bcd11fd086838f15d0723932 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64977 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22microcode: Add error msg in case `intel_microcode_find()` return NULLSubrata Banik
This patch adds an error msg if intel_microcode_find() is unable to find a microcode for the CPU SKU. TEST=Able to see the error msg in coreboot serial log in case packed with wrong microcode binary. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib4865575a44d2c8c6c3a20c2823a546d8f261e52 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65285 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22cpu/intel/microcode: Create helper function to load microcode patchSubrata Banik
This patch refactors the microcode loading and reloading API with a helper function that perform the actual MSR write operation after taking the microcode pointer from the caller function. Also, convert the microcode loading failure msg type from `BIOS_INFO` to `BIOS_ERR` to catch the error in proper. TEST=Able to perform microcode loading on google/kano. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9a7cdc2d2c9211f1e0c7921015126f7a1be87761 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65249 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22soc/intel/cmn/block/cpu: Perform PRMRR sync on all coresSubrata Banik
This patch ensures to perform core PRMRR sync if SoC decides to perform MP Init using coreboot native implementation. Also, implement a function to allow calling `init_core_prmrr()` for all CPUs from `before_post_cpus_init()`. BUG=b:233199592 TEST=Build and boot google/kano to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9b6222c98ff278419fa8411054c0954689e1271e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64978 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22intel/mp_init: Call `intel_reload_microcode()` before post_cpus_init()Subrata Banik
This patch calls into `intel_reload_microcode() function to load second microcode patch after BIOS Done bit is set and before setting the BIOS Reset CPL bit. Also, remove redundant microcode reloading debug print. BUG=b:233199592 TEST=Build and boot google/kano to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Icb3fcfd7ef5478be0a40f8f1358f55c0247b4914 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65157 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22cpu/intel/microcode: Have API to re-load microcode patchSubrata Banik
This patch introduces a newer API to reload the microcode patch when SoC selects RELOAD_MICROCODE_PATCH config. Expected to call this API being independent of CPU MP Init regular flow hence, doesn't regress the boot time. BUG=b:233199592 TEST=Build and boot google/kano to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: If480e44b88d04e5cb25d7104961b70f7be041a23 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-22mb/google/brya/var/kinox: Enable PCIe WLANIan Feng
Enable PCIe WLAN for Kinox 1. Enable PCI port 5 for PCIe WLAN 2. Enable CLKREQ, CLK SRC 2 for PCI port 5 BUG=b:236175551 TEST=Build and boot to OS in Kinox. Ensure that the WLAN module is enumerated in the output of lspci. localhost ~ # lspci 02:00.0 Network controller: Realtek Semiconductor Co., Ltd.Device c852 (rev 01) Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I3fbeadc85c9c88f5d178326dbbc83762083fe59a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65168 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-06-22device/resource: Add _kb postfix for resource allocatorsKyösti Mälkki
There is a lot of going back-and-forth with the KiB arguments, start the work to migrate away from this. Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22intel/broadwell,lynxpoint: Change formula around 4 GiBKyösti Mälkki
Let's not rely on the type to get the correct result, casting 0 to 0ull made the result wrong. Change-Id: I6dfba3800170fdd4267e3bb74c55b05533c101fc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-22ec/lenovo/pmh7: Add IORESOURCE_ASSIGNED flagKyösti Mälkki
This makes coccinelle script happy, everyone else sets flags last. Change-Id: I80f421aeacb6e72fea2265c69cafb2a0d89e5616 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-22ec/kontron/kempld: Fix IORESOURCE_IRQKyösti Mälkki
The IRQ was incorrecly allocated as IO resource. It's not possible for new_resource() to return NULL. Change-Id: I66811b36b44f06cb39df8e9cdab87be0e2ef8eb9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-06-21mb/google/nissa/var/joxer: add generic LPDDR5 SPDs for JoxerMark Hsieh
Add Makefile.inc to include five generic LPDDR5 SPDs for the following parts for Joxer: DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) MT62F1G32D4DR-031 WT:B 1 (0001) H9JCNNNBK3MLYR-N6E 0 (0000) H58G56AK6BX069 2 (0010) K3LKBKB0BM-MGCP 2 (0010) BUG=b:236576115 TEST=USE="project_joxer emerge-nissa coreboot" Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I90acb436bccd5dae8585436316246c50fc256842 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-21mb/intel/adlrvp: Select the right Kconfig for raptorlakeUsha P
CL 64619 adds the required initial code for raptorlake. Select BOARD_INTEL_ADLRVP_RPL_EXT_EC for VBOOT_MOCK_SECDATA which is mistakenly not selected. BUG=None BRANCH=firmware-brya-14505.B Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I5da561cb31b0cb0d574a8091cc346d6b321ac6fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/65165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-21soc/amd/*/Kconfig: drop unused SOC_AMD_COMMON_BLOCK_UCODE_SIZE optionFelix Held
Commit 96f7b96866b0bce7a1323c4da478f838f884383f (soc/amd/common/block/ cpu/: Make ucode update more generic) removed the code that used the SOC_AMD_COMMON_BLOCK_UCODE_SIZE Kconfig value. Drop the now unused Kconfig option. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I079f229678452ff20d8bb282804cd2e49555a6fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/65255 Reviewed-by: ritul guru <ritul.bits@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-06-21security/vboot: Add support for GSCVD (Google "RO verification")Julius Werner
This patch adds a new CONFIG_VBOOT_GSCVD option that will be enabled by default for TPM_GOOGLE_TI50 devices. It makes the build system run the `futility gscvd` command to create a GSCVD (GSC verification data) which signs the CBFS trust anchor (bootblock and GBB). In order for this to work, boards will need to have an RO_GSCVD section in their FMAP, and production boards should override the CONFIG_VBOOT_GSC_BOARD_ID option with the correct ID for each variant. BUG=b:229015103 Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I1cf86e90b2687e81edadcefa5a8826b02fbc8b24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-06-21mb/starlabs/lite/{glk/glkr}: Disable Sata Port 1Sean Rhodes
Disable Sata Port 1 as it is not used. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I93ecdaba5d1ce96ddcf3695edd7fb109054743e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-06-21mb/starlabs/lite/glkr: Don't configure GPIO's 147 through 156Sean Rhodes
These are configured by the TXE, so they do not need to be configured. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I13957992d637a53203b4328e39c0e6607e017891 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-21mb/starlabs/lite/glkr: Simplify GPIO macro'sSean Rhodes
Use shorter macro's to conifgure GPIO's. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I926aac8679f847cd963be07786e9fe2e4c63bda6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-21mb/starlabs/lite/glkr: Disconnect unused GPIO'sSean Rhodes
Disconnect GPIO's that are unused, or not connected. Also update comments that are vague or have errors. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I1b071ec1d194f76ee78066396bac8dfff5ec851b Reviewed-on: https://review.coreboot.org/c/coreboot/+/64651 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-21soc/amd/common/i2c: Add i2c bus ops handlerMatt DeVillier
Without this, calls to i2c_link() and runtime i2c detection fails on AMD common platform boards. Test: Runtime i2c detection of correct touchpad model succeeds on google/zork. Change-Id: I238b680b2afb4b9d3e5ac75fe9e630b2adc74860 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-06-21soc/amd/*: Move selection of DRIVERS_I2C_DESIGNWARE to common blockMatt DeVillier
All AMD SoCs which select SOC_AMD_COMMON_BLOCK_I2C also select DRIVERS_I2C_DESIGNWARE, so make the pairing explicit by moving the selection into SOC_AMD_COMMON_BLOCK_I2C. This will facilitating adding the Designware I2C bus ops handler in a subsequent commit. Change-Id: Ice30c8806766deb9a6ba617c3e633ab069af3b46 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-06-21device/i2c_bus: Add missing trailing newline to console outputMatt DeVillier
Improves readability in console log. Change-Id: Ied0cbb746ff3ca6250ed9322dfb2726da0949e16 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-06-21device/i2c_bus: Check for self loop in bus linkMatt DeVillier
When trying to find the parent i2c bus of a given device, ensure that the bus link doesn't point to itself, else we'll get stuck in an infinite loop. Change-Id: I56cb6b2a3e4f98d2ce3ef2d8298e74d52661331c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-06-21mb/google/brya: Add `ext_pm_support` for taeko eMMC SKUSubrata Banik
This patch ensures google/taeko eMMC SKU has advanced PM support enabled. BUG=b:235915257 TEST=Able to boot to eMMC SKU to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6b14130e47c3e3ec9b066456f3195841c83623a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65243 Reviewed-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-21mb/google/brya: Add `ext_pm_support` for taniks eMMC SKUSubrata Banik
This patch ensures google/taniks eMMC SKU has advanced PM support enabled. BUG=b:235915257 TEST=Able to boot to eMMC SKU to ChromeOS. Change-Id: I20c98006b6a45e2c8286480c560c8dbc0752327c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65213 Reviewed-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-21mb/google/nissa: Create pujjo variantStanley Wu
Create the pujjo variant of the nissa reference board by copying the template files to a new directory named for the variant. (Follow other ADLN variant to generate by manual) BUG=b:235182560 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_PUJJO Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I73ec985bc19320260d0c3132c1ca23a3648df9e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-06-20mb/purism/librem_cnl: convert to using overridetreesMatt DeVillier
Convert the librem_14 and librem_mini from using separate devicetrees to using a baseboard devicetree and overridetrees. This reduces code duplication, and facilitates adding any new variants with minimal additional code. Test: build/boot Librem 14 and Librem Mini v2 boards Change-Id: Ide65ffc750495c9ba2074757ce467efa2f384c56 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20soc/intel/apollolake: Hook Up SataPortEnable to devicetreeSean Rhodes
Hook Up SataPortsEnable to the devicetree. As the default value is 0, set both [0] and [1] in all mainboards so they aren't affected. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ica8cf9484a6e6fe4362eabb8a9a59fcaf97c1bd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64524 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-20soc/intel/alderlake/chip.c: Add missing ADL-S USB ports ACPI namesMichał Żygowski
ADL-S has more USB ports than mobile chipsets. Add missing ACPI names. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ice5f7784f9de0364681be00fc5cc445caf9d1b3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/63655 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-20soc/amd/stoneyridge: Align get_cpu_count to other targetsArthur Heymans
The CPUID function to get the number of cores on a package is common across multiple generations of AMD cpus. Change-Id: I28bff875ea2df7837e4495787cf8a4c2d522d43d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64869 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-06-20soc/amd/*: Make mtrr decision based on syscfgArthur Heymans
The syscfg has to option to automatically mark the range between 4G and TOM2, which contains DRAM, as WB. Making it generally not necessary to allocate MTRRs for memory above 4G if no PCI BARs are placed up there. Change-Id: Ifbacae28e272ab2f39f268ad034354a9c590d035 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-06-20mb/starlabs/labtop: Configure tcc_offset based on power_profile settingsSean Rhodes
Set tcc_offset value based on the power_profile value, ranging from 10 to 20 degrees. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I66fb266c1730833ff6e2dbf8ea39f23ee0878590 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20mb/google/brya/variants/nereid: enable CNVi bluetooth in overridetreeJesper Lin
When using CNVi WLAN on ADL-N, the internal USB2 port 10 is used for bluetooth. So update the nereid overridetree to enable port 10. BUG=b:236162084 TEST=USE="project_nereid emerge-nissa coreboot" and verify it builds without error. Signed-off-by: Jesper Lin <jesper_lin@wistron.corp-partner.google.com> Change-Id: Ic45301b863383e447b2dd3e06811b469cc247229 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65188 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-20drivers/usb/gadget.c: Use 'printk()' instead of 'dprintk()'Elyes HAOUAS
dprintk(BIOS_,...) was probably useed for debug print, so use printk(BIOS_, ...) instead. Change-Id: Ia4171c8b4b42f6b0c1c9c0438bab2eef73f8c416 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-06-20mb/starlabs/lite/glk: Organise USB ports by hardware portSean Rhodes
Group the USB ports by hardware ports, rather than separate USB 2.0 and 3.0 interfaces. This change also corrects the daughterboard USB 3.0 port number. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib6a934a1e5e65fe387c63b78cbe80e45e97e0a8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/64796 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-20mb/starlabs/lite/glkr: Correct the daughterboard USB 3.0 port numberSean Rhodes
The daughterboard USB 3.0 was set to port 3, which is incorrect. This patch corrects that to port 4. This fixes an issue where USB 3.0 devices are not detected when plugged in to this port. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I50f86dee1b512d0dd20d07e3ee17ebfa5e537bc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20mb/starlabs/lite/glkr: Correct USB port numbersSean Rhodes
The USB ports for the Motherboard USB 3.0 and Type-C were labelled incorrectly. This change swaps the ports, so they are labelled correctly and also corrects the over-current pins that they use. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I80484dc8bdd68dd72b3848720c790d59237a9f8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20mb/starlabs/lite/glkr: Organise USB ports by hardware portSean Rhodes
Group the USB ports by hardware ports, rather than separate USB 2.0 and 3.0 interfaces. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I2a7f50ca2b2001e83211e8eba56bfa929ecdfd74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20mb/starlabs/lite: Enable enhanced C-statesSean Rhodes
Tested on the StarLite Mk III & Mk IV with Zorin 16.2 Core. This resulted in a reduction in power consumption of approximately 3%. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I7b5f4e01bc786db02184b722c74fda7d0ca055be Reviewed-on: https://review.coreboot.org/c/coreboot/+/64709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20soc/intel/apollolake: Hook up C1e to enhanced_cstatesSean Rhodes
Hook up C1e FSP S UPD which enables enhanced C-states, to enhanced_cstates. This allows it to be enabled in the devicetree with a value of "1" as the default is disabled. C1e exists on both APL and GLK, and has been there since their initial releases. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie803a75ac9fb64a6c21b31baeea7b736e4fbf5fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/64708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20soc/intel/apollolake: Hook up UfsEnabled to devicetreeSean Rhodes
Hook up FSP S UfsEnabled UPD (1d.0) to devicetree. UFS only exist on GLK, and has been there since its initial releases. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I1976bfd340c728c64aaf36d296ac41dcd47bfc61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20mb/starlabs/lite: Configure MMIO window for ECSean Rhodes
The Nuvoton EC requires a window to be opened for updates, so open this window only if the Nuvoton EC is present. Change-Id: Iaa45aa58749c4d0bfc77e60b52eab2bcb270f3ee Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20mb/starlabs/labtop/kbl: Organise USB ports by hardware portSean Rhodes
Group the USB ports by hardware ports, rather than separate USB 2.0 and 3.0 interfaces. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib5fec81a7a04f2f5ab13784435944601902904d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20mb/starlabs/labtop/cml: Organise USB ports by hardware portSean Rhodes
Group the USB ports by hardware ports, rather than separate USB 2.0 and 3.0 interfaces. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie9bc6b3e20dddeb14cea195ef9a719432f66c6e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20mb/starlabs/lite/glk: Configure LPC IO registersSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I47523fae8d1cb0fbb972a82c43a992c9fb606ed4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20mb/starlabs/lite/glkr: Configure LPC IO registersSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I2d949af0086c231e27ac889c0aabd0d3e00c94fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/64984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20soc/intel/apollolake: Allow configuring the LPC IO registersSean Rhodes
Allow configuring the LPC IO registers in the devicetree with: * gen1_dec * gen2_dec * gen3_dec * gen4_dec Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I2a7ab3faf927cda76640227feff4e19017442897 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20intel/gma: Use bitwise or instead addition for valid bitPetr Cvek
Page table entries bit 0 is used as "valid". Its value should be set by a bitwise OR and not by an addition. Signed-off-by: Petr Cvek <petrcvekcz@gmail.com> Change-Id: I14467081c8279af4611007a25aefab606c61a058 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20mb/google/brya/var/skolas4es: Add new memory partsNick Vaccaro
Add support for the MT53E2G32D4NQ-046 WT:C and MT53E512M32D1NP-046 WT:B memory parts to skolas4es. BUG=b:236284219 BRANCH=firmware-brya-14505.B TEST=None Change-Id: I5e3534985e12535ccc4285a0d829bca04781cf1b Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65179 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-20include/smbios.h: Update misc_slot_type and smbios_onboard_device_typeElyes HAOUAS
Update according to DSP0134: https://www.dmtf.org/standards/smbios Change-Id: Iceccc672eaef0ad0bc0589797fa15d2a6a918918 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-06-18sb/intel/i82801ix/smihandler.c: Remove dead incrementElyes Haouas
The value stored to 'data' is never read. So remove dead increment and commented out code. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ifef67fc6415af1260d1a1df54f53fbe67f8860bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/62541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-06-18mb/google/dedede/var/shotzo: Add EC defines for ACPITony Huang
Update Shotzo own ec.h with the battery, lid and ps2 defines stripped. This is to ensure the correct ASL is generated so that we don't advertise PS2 keyboard support and battery/lid interrupts which don't exist. In MAINBOARD_EC_SCI_EVENTS drop following events. EC_HOST_EVENT_LID_OPEN EC_HOST_EVENT_LID_CLOSED EC_HOST_EVENT_BATTERY_LOW EC_HOST_EVENT_BATTERY_CRITICAL EC_HOST_EVENT_BATTERY EC_HOST_EVENT_BATTERY_STATUS set MAINBOARD_EC_SMI_EVENTS to 0 and drop EC_HOST_EVENT_LID_CLOSED smi event. In MAINBOARD_EC_S5_WAKE_EVENTS drop below event. EC_HOST_EVENT_LID_OPEN In MAINBOARD_EC_S3_WAKE_EVENTS drop following events. EC_HOST_EVENT_AC_CONNECTED EC_HOST_EVENT_AC_DISCONNECTED EC_HOST_EVENT_KEY_PRESSED EC_HOST_EVENT_KEY_PRESSED BUG=b:235303242 BRANCH=dedede TEST=Build Change-Id: I5717e2e8ca7549d160fe46ccde31c6d7cf9649d7 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65167 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-18soc/intel/alderlake: Skip PCIe source clock assignment if incorrectCliff Huang
When an enabled root port without pcie_rp clock being specified, the empty structure provides invalid info, which indicates '0' is the clock source and request. If a root port does not use clock source, it should still need to provide pcie_rp clock structure with flags set to PCIE_RP_CLK_SRC_UNUSED. If flags, clk_src, and clk_req are all '0', it is considered that pcie_rp clock structure is not provided for that root port. Add check and skip for enabled root port that does not have clock structure. In addition, a root port can not use a free running clock or clock set to LAN. Note that ClockUsage is either free running clock, LAN clock, or the root port number which consumes the clock. BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: I17d52374c84ec0abf888efa0fa2077a6eaf70f6c Reviewed-on: https://review.coreboot.org/c/coreboot/+/63947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-18mb/google/brya/var/agah: Remove variant_finalizeTim Wawrzynczak
The EEs and I misunderstood, and apparently the vfio-pci kernel driver will turn off the dGPU when it sees it is unused, so coreboot should leave the dGPU on so the kernel driver can save state before it shuts it down. TEST=Tested by ODM Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I30b5dead7a5302f3385ddcaecfbf134c3bb68779 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65181 Reviewed-by: Robert Zieba <robertzieba@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-17soc/intel/{alderlake, common}: Rename the pre_mem_ft structureSridhar Siricilla
The patch renames identifiers (macros, function and structure names) in the basecode/debug/debug_feature.c to generic names so that they can be used to control the features which may have to be controlled either during pre and post memory. Currently, the naming of identifiers indicate that it meant to control the features which can be controlled during only pre-memory phase. TEST=Build code for Gimble Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I53ceb25454027ab8a5c59400402beb6cc42884c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-17mb/google/brya/var/banshee: Update thermal settings PL1 and PL2Frank Wu
Update PL1 and PL2 based on the suggestion of the thermal team. Then the settings are both updated in firmware log. BUG=b:233703656, b:233703655 BRANCH=firmware-brya-14505.B TEST=FW_NAME=banshee emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Ibb81a1a8519b88ed4774385d9ccf895d64bbdc21 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-06-17cpu/intel/microcode: Fix `device enumeration` boot regressionSubrata Banik
Prior commit hash 0310d34c2 (cpu/intel/microcode: Have provision to re-load microcode patch) introduces an option to reload the microcode based on SoC selecting RELOAD_MICROCODE_PATCH config. This patch might potentially introduce a boot time regression (~30ms) when RELOAD_MICROCODE_PATCH kconfig is enabled as all cores might end up reloading the microcode without the proper need. Note: RELOAD_MICROCODE_PATCH kconfig is not yet selected by any SoC hence, it doesn't impact any coreboot project. The idea is reloading microcode depends on specific use case (for example: Skip FSP doing MP Init from Alder Lake onwards) hence, a follow up patch will create a newer API to allow reloading of microcode when RELOAD_MICROCODE_PATCH config is enabled. BUG=b:233199592 TEST=Build and boot google/kano to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie320153d25cefe153fc8a67db447384f1f20f31f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-06-17soc/amd/smm_relocate.c: Improve TSEG programmingArthur Heymans
TSEG does not need to be aligned to 128KiB but to its size, as the MSR works like an MTRR. 128KiB is a minimum TSEG size however. TESTED on google/vilboz. Change-Id: I30854111bb47f0cb14b07f71cedacd629432e0f4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64865 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-06-17soc/intel/denverton_ns: enable Denverton to use common msr definesJeff Daly
Use Intel common SoC msr.h for Denverton refactor Signed-off-by: Jeff Daly <jeffd@silicom-usa.com> Change-Id: Ic5f99fbcd2f936d4e020bd9b74b65dcd6e462bdc Reviewed-on: https://review.coreboot.org/c/coreboot/+/61016 Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-06-17soc/intel/denverton_ns: enable Denverton to use common SoC SPI codeJeff Daly
Use Intel common SoC SPI code for Denverton refactor Signed-off-by: Jeff Daly <jeffd@silicom-usa.com> Change-Id: Ic1d57c6b348adb934785b0e2bec4e856f0bf8d77 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61014 Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-17mb/google/nissa: Create joxer variantMark Hsieh
Create the joxer variant of the nissa reference board by copying the template files to a new directory named for the variant. BUG=b:236086879 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_JOXER Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I4cb74f90c4ec33818b551d5f51759930e3222677 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
2022-06-17soc/intel/denverton_ns: Define macro TOTAL_PADSEric Lai
Define total GPIO pins as TOTAL_PADS. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I220b6f1a968667a68c30c7287ab5af1912959e3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/65166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-06-17soc/intel/xeon_sp: Define macro TOTAL_PADSEric Lai
Define total GPIO pins as TOTAL_PADS. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ic7c48415d1fa3067ac62520a542058e7cab45941 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-06-17soc/intel/skylake: Define macro TOTAL_PADSEric Lai
Define total GPIO pins as TOTAL_PADS. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I40294339c79f5db1850ccd546292c67169890b2c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65161 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-17mb/google/nissa/var/pujjo: Generate SPD ID for supported memory partLeo Chou
Add pujjo supported memory parts in mem_parts_used.txt, generate SPD id for this part. 1. Samsung K3LKBKB0BM-MGCP, K3LKCKC0BM-MGCP 2. Hynix H58G56AK6BX069, H9JCNNNBK3MLYR-N6E 3. Micron MT62F512M32D2DR-031 WT:B BUG=b:235765890 TEST=Use part_id_gen to generate related settings Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I929527a219452082e416803f7a74d470be5a188c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65100 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-17mb/google/brya/var/agah: Remove stop pin declaration for LANTony Huang
Currently, the system fails to enter S0ix as the stop pin declation for LAN device will prevent system from entering suspend. So remove the stop pin declaration. Also add device_index=0 for the first NIC to get correct MAC from VPD setting. BUG=b:210970640 TEST=Build and suspend_stress_test -c 20 pass Check LAN works fine after resume Change-Id: I513bf8b4bcb4d6db2eed2790fef7f6000a441274 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65123 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-17soc/intel/alderlake/report_platform.c: Add ADL-S identificationMichał Żygowski
Based on DOC #619501, #619362 and #618427 TEST=Boot MSI PRO Z690-A DDR4 WIFI and see the silicon info is reported as ADL-S. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I8051113515ef63fc4687f53d25140a3f55aadb6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-17cpu/Makefile.inc: Fix rebuilding a new targetArthur Heymans
When switching to different board, 'make clean' needs to happen because not everything gets properly regenerated. Microcode updates are among those. You could end up with the microcode updates from the previous build which can be incorrect. Adding $(DOTCONFIG) as a dependency which gets updated when you change something in Kconfig fixes this. TESTED: swap between boards that use different microcode and see that the size changes. Change-Id: Id1edecc28d492838904e3659f1fe8c9df0a69134 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65148 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-06-17mb/supermicro/x9sae: Correct mapping of HDMI portsBill XIE
The two HDMI ports on x9sae(-v) prove to be wired to HDMI2 and HDMI3. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I07870fd70612c9ed01a833f173b18053807ad2b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-06-17mb/google/nissa/var/craask: Enable Elan touchscreenTyler Wang
Add Elan touchscreen support for craaskvin. BUG=b:235919755 TEST=Build and test on MB, touchscreen function works. Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I18e0be688705942647c42ee532fcd32e862fe78c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-06-17mb/google/nissa/var/craask: Add ALC5682I-VS codec supportTyler Wang
Add ALC5682I-VS related settings. And add codec/amplifier space in fw_config. BUG=b:229048361, b:235436515 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I567d3567318c810e19ae9e9ba5e0dc8332517866 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-06-17mb/google/nissa/var/craask: Disable SD card based on fw_configTyler Wang
Use fw_config Bit 5 to control whether to disable SD card: Bit 5 = 0 --> enable SD card Bit 5 = 1 --> disable SD card BUG=b:229048361 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Ib5e92600564e2138e32a0d2e60259b9767516a4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65129 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-17mb/google/brya/var/banshee: Update gpio configurationFrank Wu
Update gpio configuration based on GPIO_0610b.xlsx. BUG=b:226182106, b:226182090 BRANCH=firmware-brya-14505.B TEST=FW_NAME=banshee emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I2b447629645690e5e97a17fff25860838f4f3344 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2022-06-16mb/google/peach_pit: Select BOOT_DEVICE_NOT_SPI_FLASHYu-Ping Wu
CPU_SAMSUNG_EXYNOS5420 has its own boot device implementation (src/soc/samsung/exynos5420/alternate_cbfs.c), so BOOT_DEVICE_NOT_SPI_FLASH should be selected. Change-Id: I0a9f96ad68b28773ede4e99510bd33867789e185 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65109 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-16mb/google/brya/vell: Implement variant_devtree_update() for audioeddylu@ami.corp-partner.google.com
Different board versions have different audio layouts, therefore support both layouts by enabling only the appropriate devices in the devicetree via board_id(). BUG=b:207333035 BRANCH=none TEST='FW_NAME=vell emerge-brya coreboot' Change-Id: If053b8f85933f8fc75589ae175e225cc9c1e3991 Signed-off-by: Eddy Lu <eddylu@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65124 Reviewed-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-16soc/intel/alderlake: Unselect USB4 and TCSS options for ADL-SMichał Żygowski
Alder Lake-S CPUs do not have TCSS and USB4 devices. Unselect them. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ifc643d440107754dfe1a0844964f70de670cb1f1 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-16soc/intel/alderlake/fsp_params.c: Add VccIn Aux Imon IccMax for ADL-SMichał Żygowski
Based on DOC #619501. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ia95404e717787edbdb67c9e584e749526b973427 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-16mb/intel/adlrvp: Add 5G WWAN ACPI support for ADL-P RVPCliff Huang
Add FM350GL 5G WWAN support using drivers/wwan/fm and additional PM features from RTD3. PCIe root port: 6 (1 based) clock source & request: 5 (0 based) GPIOs: WWAN_PERST_N: GPPC_C5 WWAN_RST_N: GPPC_F14 WWAN_FCP_OFF_N: GPPC_F15 WWAN_WAKE_N: GPPC_D18 WWAN_PWREN: GPPC_F21 WWAN_DISABLE_N: GPPC_D15 CLKREQ5_WWAN_N: GPPC_H23 TEST=Check SSDT table to see if the PXSX device and PowerResource RTD3 are generated under the root port. BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I10902245e3a5e05cd2af9030394933e936c25396 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63941 Reviewed-by: Jeremy Compostella <jeremy.compostella@intel.corp-partner.google.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2022-06-15soc/intel/adl: Add missing claimed memory regionsEran Mitrani
The Alder Lake chipset has several more reserved memory regions that are unavailable to the resource allocator than are currently marked as such in the system agent code. This CL adds the following regions (documented in Intel docs #626540, #619503): 1. TSEG 2. GSM 3. DSM 4. PCH_RESERVED 5. CRAB_ABORT 6. APIC 7. TPM 8. LT_SECURITY Claimed regions before this change: ======================================================== base 0 size a0000 // 0 - > 0xa0000 base a0000 size 20000 // legacy VGA base c0000 size 40000 // RAM base c0000 size 76f40000 // 0xc0000 -> top_of_ram base 77000000 size 9400000 // top_of_ram -> TOLUD base c0000000 size 10000000 // PCIEXBAR base f8000000 size 2000000 // MMSPI base fb000000 size 1000 // REGBAR base fed80000 size 4000 // EDRAMBAR base fed84000 size 1000 // TBT0BAR base fed85000 size 1000 // TBT1BAR base fed86000 size 1000 // TBT2BAR base fed87000 size 1000 // TBT3BAR base fed90000 size 1000 // GFXVTBAR base fed91000 size 1000 // VTVC0BAR base fed92000 size 1000 // IPUVTBAR base feda0000 size 1000 // DMIBAR base feda1000 size 1000 // EPBAR base fedc0000 size 20000 // MCHBAR base 100000000 size 17fc00000 // 4GiB -> TOUUD Claimed regions with this change: ======================================================== base 0 size a0000 // 0 - > 0xa0000 base a0000 size 20000 // legacy VGA base c0000 size 40000 // RAM base c0000 size 76f40000 // 0xc0000 -> top_of_ram base 77000000 size 9400000 // top_of_ram -> TOLUD base 7b800000 size 800000 // TSEG base 7c000000 size 800000 // GSM base 7c800000 size 3c00000 // DSM base c0000000 size 10000000 // PCIEXBAR base f8000000 size 2000000 // MMSPI base fb000000 size 1000 // REGBAR base fc800000 size 2000000 // PCH_RESERVED base feb00000 size 80000 // CRAB_ABORT base fec00000 size 100000 // APIC base fed40000 size 10000 // TPM base fed50000 size 20000 // LT_SECURITY base fed80000 size 4000 // EDRAMBAR base fed84000 size 1000 // TBT0BAR base fed85000 size 1000 // TBT1BAR base fed86000 size 1000 // TBT2BAR base fed87000 size 1000 // TBT3BAR base fed90000 size 1000 // GFXVTBAR base fed91000 size 1000 // VTVC0BAR base fed92000 size 1000 // IPUVTBAR base feda0000 size 1000 // DMIBAR base feda1000 size 1000 // EPBAR base fedc0000 size 20000 // MCHBAR base 100000000 size 17fc00000 // 4GiB -> TOUUD BUG=b:149830546 BRANCH=firmware-brya-14505.B TEST='emerge-brya coreboot chromeos-bootimage' builds correctly. Tested on an Anahera device which successfully boots to ChromeOS with kernel version 5.10.109-15688-g857e654d1705. Also ran dmseg, and saw the added regions in e820 prints. Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I058a5c1cc59703e35ceddb8a7e26fb22a6a2b75e Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-15soc/intel/common: support for configurable memory regions claimed by SAEran Mitrani
see https://review.coreboot.org/c/coreboot/+/65072/8 BUG=b:149830546 BRANCH=firmware-brya-14505.B TEST='emerge-brya coreboot chromeos-bootimage' builds correctly. Tested on an Anahera device which successfully boots to ChromeOS with kernel version 5.10.109-15688-g857e654d1705. Change-Id: I80df95f9146934d6a2d23e525c22be3a9a7e2b9f Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64677 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-15soc/intel/alderlake: remove unnecessary test conditionJeremy Compostella
mch_id is set to zero and then unnecessarily tested. TEST=build and boot image on ADL RVP board Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I20734e1638714027b976043b3a0457cbf3cd8442 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65121 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Cliff Huang <cliff.huang@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-15soc/intel/alderlake: remove unnecessary MSR definitionJeremy Compostella
MSR_VR_MISC_CONFIG2 is not used by AlderLake code. TEST=compilation check Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I313acf01c534d0d32620a9dedba7cf3b304ed2ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/65120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2022-06-15soc/intel/alderlake/Kconfig: Unselect IPU for ADL-SMichał Żygowski
Alder Lake S CPUs do not have IPU device. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I79b084273f407119d903ed6f0cadf0084e8dda6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-15ec/google/chromeec: Add property to denote mux mode switchPrashant Malani
On some systems, the Chrome EC controls both the USB Type-C mux as well as the retimer. Introduce a boolean property "mode-switch" to denote switches which act as a mode-switch. BUG=b:235834631 TEST=None BRANCH=None Signed-off-by: Prashant Malani <pmalani@chromium.org> Change-Id: If209a8529ff7ec424f23fd96875ac95a1fe6267d Reviewed-on: https://review.coreboot.org/c/coreboot/+/65116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-15soc/intel/common/acpi: Fix warning in ASLVarshit B Pandya
Warnings are treated as errors in build. UBAR is declared inside APRT method which throws warning as follows "Static OperationRegion should be declared outside control method" Move UBAR outside APRT method to fix warning. TEST=build brya with following changes without any warnings 1. Select ACPI_CONSOLE 2. Include <soc/intel/common/acpi/acpi_debug.asl> 3. Add APRT function in any asl file. Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I40c676fd0bbd529bcbded18dd248b918f47324d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2022-06-15mb/google/brya/var/crota: Enable VNN_1.05v_bypass railTerry Chen
Some SKUs of crota have VNN 1.05v bypass rails for additional power savings in S0ix states. This patch uses FW_CONFIG to enable that feature when run on the applicable SKUs. BUG=b:233175019 BRANCH=none TEST=emerge-brya coreboot and verified pass Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: Iaade50f4fe821b7114b3e2d44bda0747816da11c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Cyan Yang <cyan.yang@intel.corp-partner.google.com> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-15cpu/x86/smm/smm_module_loader.c: Fix formatted printElyes Haouas
This fixes following errors when building GA-945GCM-S2L with clang 14.0.5. CC ramstage/cpu/x86/smm/smm_module_loader.o src/cpu/x86/smm/smm_module_loader.c:180:10: error: format specifies type 'unsigned long' but the argument has type 'size_t' (aka 'unsigned int') [-Werror,-Wformat] region_offset(&cpus[i].stub_code), i); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ src/cpu/x86/smm/smm_module_loader.c:184:20: error: format specifies type 'unsigned long' but the argument has type 'size_t' (aka 'unsigned int') [-Werror,-Wformat] __func__, region_offset(&cpus[0].stub_code), ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ src/cpu/x86/smm/smm_module_loader.c:185:10: error: format specifies type 'unsigned long' but the argument has type 'size_t' (aka 'unsigned int') [-Werror,-Wformat] region_offset(&cpus[i].stub_code), size); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ src/cpu/x86/smm/smm_module_loader.c:349:52: error: format specifies type 'unsigned long' but the argument has type 'size_t' (aka 'unsigned int') [-Werror,-Wformat] printk(BIOS_DEBUG, "%-12s [0x%lx-0x%lx]\n", name, region_offset(&region), ~~~ ^~~~~~~~~~~~~~~~~~~~~~ %zx src/cpu/x86/smm/smm_module_loader.c:350:9: error: format specifies type 'unsigned long' but the argument has type 'size_t' (aka 'unsigned int') [-Werror,-Wformat] region_end(&region)); Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I59f20aacf91cb50fb194a84082a643b34c6c1ae5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65154 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-15mb/google/brya/var/brya4es: Enable CNVi ddr rfimVarshit B Pandya
enable_cnvi_ddr_rfim enables DDR RFI mitigation feature, this feature needs to be enabled for all brya variants. Currently, it's not enabled for brya4es. BUG=b:201724512 TEST=Build, boot brya4es and check function 3 in _DSM method under \_SB.PCI0.WFA3 Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I6cc9d3e4721188dcbc8584596c9f3f89a737206f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65110 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-27 04:09:33 +0000