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authorSean Rhodes <sean@starlabs.systems>2022-05-19 22:12:46 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-06-21 12:30:46 +0000
commit600856dec27dcb32687c8d0098a92822024c7f2c (patch)
tree3abacdc2827a7895934d118badfcd11cb4921f69 /src
parent664f0c51e75f4ee168f28e549bb45782c0473d2e (diff)
mb/starlabs/lite/{glk/glkr}: Disable Sata Port 1
Disable Sata Port 1 as it is not used. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I93ecdaba5d1ce96ddcf3695edd7fb109054743e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/starlabs/lite/variants/glk/devicetree.cb1
-rw-r--r--src/mainboard/starlabs/lite/variants/glkr/devicetree.cb1
2 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb
index 303ba5ff5b..d275cd3f1d 100644
--- a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb
+++ b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb
@@ -80,7 +80,6 @@ chip soc/intel/apollolake
device pci 11.0 off end # ISH
device pci 12.0 on # SATA
register "SataPortsEnable[0]" = "1"
- register "SataPortsEnable[1]" = "1"
end
device pci 13.0 off end # PCIe-A 0 Slot 1
device pci 13.1 off end # PCIe-A 1
diff --git a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb
index 150ab57d47..b18e8f0398 100644
--- a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb
+++ b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb
@@ -80,7 +80,6 @@ chip soc/intel/apollolake
device pci 11.0 off end # ISH
device pci 12.0 on # SATA
register "SataPortsEnable[0]" = "1"
- register "SataPortsEnable[1]" = "1"
end
device pci 13.0 off end # PCIe-A 0 Slot 1
device pci 13.1 off end # PCIe-A 1