coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2023-12-16	soc/amd/genoa: rename to genoa_poc	Felix Held
2023-12-15	vc/amd: use 'openSIL' spelling in comments & help text	Felix Held
2023-12-14	vendorcode/amd/opensil/genoa_poc: add opensil_fill_fadt_io_ports	Felix Held
2023-12-12	vendorcode/amd/genoa: Parse APOB for DRAM layout	Arthur Heymans
2023-12-12	soc/amd/genoa: Add opensil MPIO chip files	Arthur Heymans
2023-12-12	vendorcode/amd/opensil: Add SATA configuration	Arthur Heymans
2023-12-12	vendorcode/amd/opensil: Add USB configuration	Martin Roth
2023-12-08	vendorcode/amd/opensil: Set up resource manager input block	Arthur Heymans
2023-12-06	vendorcode/amd/opensil: Add initial setup and API calls	Arthur Heymans
2023-11-30	vendorcode/amd/opensil: Implement cbmem_top_chipset	Arthur Heymans
2023-11-30	vendorcode/amd/opensil/genoa: Implement console callback	Arthur Heymans
2023-11-28	vendorcode/amd: Hook up opensil	Arthur Heymans
2023-11-13	Update genoa_poc/opensil submodule to upstream main	Martin Roth
2023-11-07	vc/amd/opensil/genoa_poc/openSIL: Add openSIL code as submodule	Martin Roth