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2021-12-18sb/intel/lynxpoint: Update `intel_me_status()` signatureAngel Pons
Update the parameter types of `intel_me_status()` to not be pointers. Change-Id: I0fd577c49bec7a581c340fc2fcadcadd50b1a638 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-18sb/intel/lynxpoint/me.c: Refactor MEI CSR functionsAngel Pons
Change the signature of MEI CSR functions to reduce pointer usage. Change-Id: I1e4885daf8b3e11056421e663e67c8f360699a98 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-18sb/intel/lynxpoint: Use unions for MEI registersAngel Pons
Wrap bitfield structs in unions to reduce pointer usage. This adds more uses of the `mei_dump()` function, only used for debugging. Refactoring the MEI CSR functions to not use pointers is done in a follow-up. Change-Id: I4defbb8c0e7812bf95c672ce529959f67c34537a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-18sb/intel/lynxpoint: Use unions for ME PCI registersAngel Pons
Wrap bitfield structs in unions to reduce pointer usage. Change-Id: I8ac901211beb0ef24dff926b1a06004a99e68bda Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-18sb/intel/lynxpoint: Drop typedefs of enum typeAngel Pons
There's no need to use typedefs for enum types. Get rid of it. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I830d95018b33fe6ab7e2c37ebf15bb1df6ceec38 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-18sb/intel/lynxpoint: Drop typedefs of struct typesAngel Pons
There's no need to use typedefs for struct types. Get rid of them. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I109bd690500a9f03b9da0fd72044be79abf660d3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-11lynxpoint/broadwell: Use `azalia_codecs_init()`Angel Pons
Use the functionally-equivalent common Azalia code to get rid of redundant code. Change-Id: Id25d2797a91b05264b1a76fa8faec0533dd5ac78 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59120 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-11device/azalia_device: Drop unused function parameterAngel Pons
The `dev` parameter of the `azalia_codecs_init()` function is not used. Remove it, and update all call sites accordingly. Change-Id: Idbe4a6ee5e81d5a7fd451fb83e0fe91bd0c09f0e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59119 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-11haswell/lynxpoint/broadwell: Use `azalia_codec_init()`Angel Pons
Use the functionally-equivalent common Azalia code to get rid of redundant code. Change-Id: I83cf1a3a1a3854c9283ccac5e254357a32638dda Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59118 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-11lynxpoint/broadwell: Use `azalia_program_verb_table()`Angel Pons
Use the `azalia_program_verb_table()` function in preparation to deduplicate Azalia init code. Change-Id: I22cfee41e001c9ecf4fbac37aadbd12f43ac8aaf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59116 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-11sb/intel/bd82x6x: Use `azalia_codecs_init()`Angel Pons
Use the functionally-equivalent common Azalia code to get rid of redundant code. Change-Id: I982c1725d5affe95a20aa6713a246cd6b1ad270c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59114 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-11sb/intel/ibexpeak: Use `azalia_codecs_init()`Angel Pons
Use the functionally-equivalent common Azalia code to get rid of redundant code. Change-Id: Ib3b40e5788c6315cad02b670346997c9179e5fab Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-11-11sb/intel/i82801jx: Use `azalia_codecs_init()`Angel Pons
Use the functionally-equivalent common Azalia code to get rid of redundant code. Change-Id: Idc8d272d76a031c6835baf952eca03fc2e306525 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-11-11sb/intel/i82801ix: Use `azalia_codecs_init()`Angel Pons
Use the functionally-equivalent common Azalia code to get rid of redundant code. Change-Id: I53d993ff74e7952c34fbe94d49d3ebf2489dd414 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-11-11sb/intel/i82801gx: Use `azalia_codecs_init()`Angel Pons
Use the functionally-equivalent common Azalia code to get rid of redundant code. Change-Id: Icc435dd0c7cef1b458c877b5a64e6dba1d10524c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-11-11sb/intel/i82801{ix,jx}: Initialise all codecsAngel Pons
These southbridges support four external codecs, not three. Change-Id: I3f352451d16dceefa0f3fabf413a0e57aa498df5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-11-11sb/intel/bd82x6x: Remove unused typedefAngel Pons
Change-Id: If725a369e7a12fbddd7b108e557d34a13bc78c09 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-11-11sb/intel/i82801gx: Program PC BEEP verbsAngel Pons
For consistency with other Intel southbridges, program PC BEEP verbs. None of the boards in the tree using this southbridge provide PC BEEP verbs, so this change makes no difference. Change-Id: I94d24999af819cf3951510586fd4864d1ed3f2f1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-11-11sb/intel: Use `azalia_program_verb_table()` functionAngel Pons
Use the `azalia_program_verb_table()` function in preparation to deduplicate Azalia init code. With this change, the "Azalia: verb loaded." message is now printed when programming the verbs failed. This will be addressed once `codec_init()` has been deduplicated. Change-Id: I5d9e0f19429620166f2a6ef48ec7c963ee64b59c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-11-04sb/intel: Replace bad uses of `find_resource`Angel Pons
The `find_resource` function will never return null (will die instead). In cases where the existing code already accounts for null pointers, it is better to use `probe_resource` instead, which returns a null pointer instead of dying. Change-Id: I13c7ebeba2e5a896d46231b5e176e5470da97343 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-10-22arch/x86/ioapic: Select IOAPIC with SMPKyösti Mälkki
For coreboot proper, I/O APIC programming is not really required, except for the APIC ID field. We generally do not guard the related set_ioapic_id() or setup_ioapic() calls with CONFIG(IOAPIC). In practice it's something one cannot leave unselected, but maintain the Kconfig for the time being. Change-Id: I6e83efafcf6e81d1dfd433fab1e89024d984cc1f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-22mb/emulation/qemu-i440fx: Select IOAPICKyösti Mälkki
For SMP operation IOAPIC needs to be configured. For a build with MAX_CPUS=1 emulation might still decode the IOAPIC MMIO window, it does not really matter to have it always reserved. Change-Id: Ia340fc418cd9ceda56a2a10972e130d9f289c589 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-22sb,soc/intel: Replace set_ioapic_id() with setup_ioapic()Kyösti Mälkki
This adds delivery of PIC/i8259 interrupts via ExtNMI on the affected platfoms. Change-Id: If99e321fd9b153101d71e1b995b43dba48d8763f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-22sb,soc/intel: Set IOAPIC max entries before APIC IDKyösti Mälkki
This allows to replace set_ioapic_id() call with setup_ioapic() that also clears redirection table entries. Change-Id: I854f19c997a96bcdccb11a0906431e3291788cb6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-22sb,soc/intel: Set IOAPIC redirection entry countKyösti Mälkki
The number of redirection table entries (aka interrupt vectors) inside an I/O APIC may depend of the SKU, with the related register being of type read/write-once. Provide support utilities to either lock or set this registers value. Change-Id: I8da869ba390dd821b43032e4ccbc9291c39e6bab Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-19southbridge/intel/common: Add an option to allow stitching of CSE binaryFurquan Shaikh
In the following changes, CSE binary for some platforms will be stitched at build time instead of adding a pre-built binary. This change adds a new Kconfig `STITCH_ME_BIN` which allows mainboard to select if it wants to stitch CSE binary instead of adding a pre-built one. In this case, ME_BIN_PATH is not visible to user and instead mainboard and/or SoC code is expected to provide the recipe for stitching the CSE image. BUG=b:189177580 Change-Id: I78ab377e110610f9ef4d86a2b6eeb4113897df85 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58083 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-18ACPI: Have common acpi_fill_mcfg()Kyösti Mälkki
As long as there is only one PCI segment we do not need more complicated MCFG generation. Change-Id: Ic2a8e84383883039bb7f994227e2e425366f9e13 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-14sb/intel/lynxpoint: Enable PCIe Clock PM and ASPM L1Angel Pons
Enable PCIe Clock power management and ASPM L1 substate by default. This matches what Broadwell does. Change-Id: Ic2bbcbc23d6bab0900d3e90ad8e2fbfa4aea3c16 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-05src/soc to src/superio: Fix spelling errorsMartin Roth
These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58082 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-29{sb,soc}/intel: Drop unused globalnvs.asl methodsAngel Pons
These methods are never used in the code. Drop them. Change-Id: If5568b494f821d2647ada5ae845bcd015708520e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-29{sb,soc}/intel: Drop PRMx from GNVSAngel Pons
These fields are never used in the code. Drop them. Change-Id: Icd07f2d704c19126bf6df4d740c21d5a1342061b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-29{sb,soc}/intel: Drop LCKF from GNVSAngel Pons
This field is never used in the code. Drop it. Change-Id: I88207ec369ab83823ef2f3fc40f68a0980ce9663 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-17sb/intel/ibexpeak/early_cir: add missing arch/cpu.h includeFelix Held
Including arch/cpu.h is needed to have the declaration for cpuid_eax, get_fms and struct cpuinfo_x86. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I18b60f8cf33f71c7215a97ea209b8f8cf66cf42f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-17sb/intel/bd82x6x,ibexpeak,lynxpoint/me.h: add missing includesFelix Held
Include device/device.h to have struct device defined and types.h to have bool, u8, u16 and u32 defined. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3c5d5a78c2e2dab21432ced5f84665eb78a49d52 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-09sb/intel/lynxpoint: Drop `config_t` typedefAngel Pons
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I550198aae22fbe39f4b461332a10de82c78cd191 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57498 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-09sb/intel/lynxpoint/fadt.c: Reuse length fieldsAngel Pons
Compute the bit width of FADT register blocks using their length in bytes, which is readily available from a different field. Change-Id: I4dafa3546714ae46946d6502598e4b945c2a77a0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-19acpi: Fill fadt->century based on KconfigNico Huber
Change-Id: I916f19e022633b316fbc0c6bf38bbd58228412be Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-26src/*: Specify type of `CBFS_SIZE` onceAngel Pons
There's no need to specify the type of the `CBFS_SIZE` Kconfig symbol more than once. This is done in `src/Kconfig`, along with its prompt. Change-Id: I9e08e23e24e372e60c32ae8cd7387ddd4b618ddc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56552 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14sb/intel/common: Hide IFD options if !HAVE_IFD_BINAngel Pons
When `HAVE_IFD_BIN` is not enabled, do not show IFD-related options. Change-Id: I8736f32b4c695efbd68adf551e1376726c718b56 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-07-05sb/intel/i82801gx: Prepare for x86_64Arthur Heymans
Do the usual int conversions. TESTED: BUILD_TIMELESS=1 produces identical image on foxconn/g41m. Change-Id: Idebfe4669854b307bee653df6d93e46ae3f39dec Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56020 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-29southbridge/intel/common: Move invalid PIRQ value to 0Tim Wawrzynczak
This makes structs that contain an `enum pirq` field that is default-initialized have the value PIRQ_INVALID Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Idb4c7d79de13de0e4b187a42e8bdb27e25e61cc1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55281 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-21security/intel: Add option to enable SMM flash access onlyAngel Pons
On platforms where the boot media can be updated externally, e.g. using a BMC, add the possibility to enable writes in SMM only. This allows to protect the BIOS region even without the use of vboot, but keeps SMMSTORE working for use in payloads. Note that this breaks flashconsole, since the flash becomes read-only. Tested on Asrock B85M Pro4 and HP 280 G2, SMM BIOS write protection works as expected, and SMMSTORE can still be used. Change-Id: I157db885b5f1d0f74009ede6fb2342b20d9429fa Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-16sb/intel/i82870: Use ioapic utility functionsKyösti Mälkki
Change-Id: I60ce17fd7640fab064a3d62d8d2b3703993c7b59 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55309 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-16arch/x86/ioapic: Drop irq_on_fsb as a configurable itemKyösti Mälkki
APIC Serial Bus pins were removed with ICH5 already, so a choice 'irq_on_fsb = 0' would not take effect. The related register BOOT_CONFIG 0x3 is also not documented since ICH5. For emulation/qemu-q35 with ICH9 the choice INTERRUPT_ON_APIC_BUS was wrong and ignored as BOOT_CONFIG register emulation was never implemented. For ICH4 and earlier, the choice to use FSB can be made based on the installed CPU model but this is now just hardwired to match P4 CPUs of aopen/dxplplusu. For sb/intel/i82371eb register BOOT_CONFIG 0x3 is also not defined and the only possible operation mode there is APIC Serial Bus, which requires no configuration. Change-Id: Id433e0e67cb83b44a3041250481f307b2ed1ad18 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55257 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-16sb/intel/lynxpoint: Update xHCI _PS0 and _PS3 methodsAngel Pons
Lynx Point PCH ACPI reference code version 1.9.1 has two additional magic steps, which were already present in Broadwell. Add them. Change-Id: Ia8ca6dcfcfb4ed6b0d957d249b93640ef74670d7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-16sb/intel/lynxpoint/Kconfig: Fix typo in help textAngel Pons
Lynxpont ---> LynxPoint Change-Id: I5af67079ead389beeafd9172aa1b98980dacbd38 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-15nb/intel/sandybridge: Add x86_64 supportPatrick Rudolph
Fix compilation on x86_64 by using compatible types. The MRC blob isn't supported yet as there's no x86_32 wrapper. Tested on HP8200: * Still boots on x86_32. * Boots to payload in x86_64 Change-Id: Iab29a87d52ad3f6c480f21a3b8389a7f49cb5dd8 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-12arch/x86/ioapic: Add get_ioapic_id() and get_ioapic_version()Kyösti Mälkki
Change-Id: I4ad080653c9af94a4dc73d93ddc4c8c117a682b9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-09sb/intel/lynxpoint: Add SerialIO UART console supportAngel Pons
Derived from Broadwell and adapted to follow what soc/intel does. Note that SERIALIO_UART_CONSOLE is meant to be selected from the mainboards which expose a SerialIO UART. UART_FOR_CONSOLE also needs to be set in mainboard Kconfig accordingly. It is possible that some of the UART configuration steps in bootblock are unnecessary. However, some of the steps turn off power management features and others are undocumented: omitting them could cause weird issues. Finally, add a config file to ensure the code gets build-tested. Tested on out-of-tree Compal LA-A992P, SerialIO UART 0 can be used to receive coreboot and SeaBIOS logs. Change-Id: Ifb3460dd50ed03421a38f03c80f91ae9fd604022 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52489 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-07sb/intel/lynxpoint: Drop P_LVLx support in FADTAngel Pons
IO MWAIT redirection is not enabled, and C-states are reported using the _CST ACPI object, which overrides the P_LVLx values. Change-Id: I1b623d19a85045797921b4909e01d5ba521de3ad Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-07sb/intel/bd82x6x: Drop P_LVLx support in FADTAngel Pons
IO MWAIT redirection is not enabled, and C-states are reported using the _CST ACPI object, which overrides the P_LVLx values. Change-Id: I737bd58bcda3e7c5f6591e4c2309530ff035e2c8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-07sb/intel/ibexpeak: Drop P_LVLx support in FADTAngel Pons
IO MWAIT redirection is not enabled. The code is missing, but C-states should instead be reported using the _CST ACPI object. Change-Id: I21fd2fa6ee4aa1ed57694549d5cb48159f37af26 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-07sb/intel/bd82x6x: Add missing ID for PCI bridgeJames Ye
The PCI device ID 0x244e for the "Intel Corporation 82801 PCI Bridge" for desktop platforms was missing. Change-Id: I22cdbcf518d86af7b93de7731d175088a81bbc1f Signed-off-by: James Ye <jye836@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-06-07sb/intel/bd82x6x: Use array for PCIe ASPM overridesAngel Pons
Using an array reduces the amount of boilerplate code. Change-Id: Ic6a48a01d3b96e69273dc28bdb6699ce7c0931b2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55246 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-20sb/intel/lynxpoint: Add pch_iobp_exec() functionAngel Pons
Taken from Broadwell. A follow-up will make Broadwell use the IOBP code from Lynx Point. Change-Id: Iacc90930ad4c34777c8f1af8b69c060c51a123b5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52514 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-20sb/intel/lynxpoint: Relocate SATA clock gating writeAngel Pons
Do it in the same place as Broadwell. Tested on out-of-tree Compal LA-A992P, SATA still works. Change-Id: I50bd951af52d03ad986dbf4bf70bdae348fa994b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47034 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-16sb/intel: Drop outdated SMBus I/O BAR commentAngel Pons
The SMBus I/O bar is not relocated because it's reported to the allocator as a fixed resource. Drop these out-of-date comments. Change-Id: I0149764fd231b3a4e56a5a9b7f4ae61f7954cf7a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-05-07sb/intel/common/pmclib: Use pmbase functionsArthur Heymans
Change-Id: Ic0be2c1ffaadcc6212c548332d60d40b405abbda Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-05-07sb/intel/common: Fix platform_is_resuming()Arthur Heymans
platform_is_resuming() was using the wrong register (PM1_STS) to figure out if the platform was resuming (PM1_CNT). Change-Id: I1f69dca1da158aae15c6da6d4c898c71d9cdb51f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-05-07sb/intel/common: Implement acpi_is_wakeup_s3()Arthur Heymans
acpi_is_wakeup_s3() requires acpi_get_sleep_type(). Change-Id: Ibe01863e685bcbc9652a72be0632cfbd83e18380 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-05-06src: Retype option API to use unsigned integersAngel Pons
The CMOS option system does not support negative integers. Thus, retype and rename the option API functions to reflect this. Change-Id: Id3480e5cfc0ec90674def7ef0919e0b7ac5b19b3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-05-05nb/intel: Don't select VBOOT_SEPARATE_VERSTAGEArthur Heymans
Now the bootblock is not limited to 64K so integrating vboot into the bootblock reduces the binary size. Change-Id: Ic92ecf8068f327a893d20924685ce571752d379f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52787 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-05sb/intel/lynxpoint: Fix VBOOT with !CONFIG_INTEL_LYNXPOINT_LPArthur Heymans
The Intel Basking Ridge CRB does not have a Lynxpoint LP PCH but was using the lp gpio code instead of the southbridge/intel/common code in verstage. Change-Id: I775d3dc3540fbd8a939701d873183dd016e24ba4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-27sb/intel/common: Refactor _PRT generation to support GSI-based tablesTim Wawrzynczak
Newer Intel SoCs also support _PRT tables, but they route PCI devices to more than just PIRQs, and statically specify IRQs instead of using link devices. Extend/refactor intel_acpi_gen_def_acpi_pirq to support this additional use case. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ica420a3d12fd1d64c8fe6e4b326fd779b3f10868 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-04-26sb/intel/lynxpoint: Add and use power state bit macrosAngel Pons
Tested with BUILD_TIMELESS=1, Google Wolf remains identical. Change-Id: Id85b76c0aaf481f99f55a9ce6d813ff32753e588 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-04-21ChromeOS: Use CHROMEOS_NVS guardKyösti Mälkki
Replace CONFIG(CHROMEOS) with CONFIG(CHROMEOS_NVS) for cases where the conditional and dependency are clearly about the presence of an ACPI NVS table specified by vendorcode. For couple locations also CONFIG(HAVE_ACPI_TABLES) changes to CONFIG(CHROMEOS_NVS). This also helps find some of the CONFIG(CHROMEOS) cases that might be more FMAP and VPD related and not about ChromeOS per-se, as suggested by followup works. Change-Id: Ife888ae43093949bb2d3e397565033037396f434 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50611 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21{sb,soc}/intel: Use `get_int_option` functionAngel Pons
Change-Id: I05f724785880089a513319d70dfd70fc2a6b7679 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-04-21sb/intel/bd82x6x: Use {get,set}_int_optionAngel Pons
Change-Id: Icbfea8c516c42b45d689da92b7e426cb6d5112a5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-04-21sb/intel/x/sata.c: Use `get_int_option` for `sata_mode`Angel Pons
Change-Id: Ifd1f3969281e67d1a6ab7eb99dd048799c0cb17d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-04-19sb/intel/common: Drop some PCH_LPC_DEV macrosAngel Pons
The macro definitions depend on __SIMPLE_DEVICE__ and are only used in the get_gpio_base() or lpc_get_pmbase() functions, which already guard PCH_LPC_DEV usage using __SIMPLE_DEVICE__ in preprocessor. Change-Id: I5d3681debe29471dfa143ba100eb9060f6364c93 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-11sb/intel/x/smbus.c: Correct register access widthAngel Pons
The register is 16 bits wide. Change-Id: I58d44a17613965e0a27aab5246dcdce68e1a8201 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-04-06arch/x86: Provide readXp/writeXp helpers in arch/mmio.hAngel Pons
These p-suffixed helpers allow dropping pointer casts in call-sites, which is particularly useful when accessing registers at an offset from a base address. Move existing helpers in chipset code to arch/mmio.h and create the rest accordingly. Change-Id: I36a015456f7b0af1f1bf2fdff9e1ccd1e3b11747 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51862 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06sb/intel/i82371eb: Do not read PM/SMBus I/O ports at runtimeKeith Hui
Commit 023fdaffd1 (mb/asus/p2b: Refactor southbridge ACPI stuff) moved the southbridge ACPI stuff to its own file. It also (prematurely) listed PM and SMBus I/O port ranges as a #defined fixed value. Since these two ranges are not expected to change at runtime anyway, we can simply drop the ASL code doing the read. Change-Id: Id5adb37d047621d7c8faf81607ceea4cbcac3d34 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41093 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06sb/intel/*/smihandler.c: Correct BIOS_CNTL access widthAngel Pons
The BIOS_CNTL register is 8 bits wide on all affected platforms. Change-Id: Iaf9267cf27847d54ed50e1f9ae29011d0e99cf8e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51939 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-25nb/intel/haswell: Move USB config API into Lynx PointAngel Pons
Both EHCI and xHCI USB controllers are inside the PCH (southbridge). Now that mainboard USB configuration no longer depends on pei_data.h definitions, the API declarations can be placed in southbridge code. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: Ia21991b225482b33c5bc0dc52884674d301b28ba Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-24sb/intel/common: Use new acpigen_write_PRT_*_entry functionsTim Wawrzynczak
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I9f573b9bd40260ab963c5a4a965a6ac483af91ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/51158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-22{lynxpoint/broadwell}: Set Azalia HDCFG.BCLD bitAngel Pons
Lock down several HD Audio registers by setting the HDCFG.BCLD bit. Tested on Asrock B85M Pro4, the GCAP register becomes read-only. Change-Id: Id6208289a68baaedc4aad51cc0c5355f996a1b00 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-03-22{lynxpoint,broadwell}/hda_verb.c: Drop effect-free writeAngel Pons
This bit is hardwired to 1 (Intel High Definition Audio mode). Change-Id: I3683497c5e2446f1d8319037583890b5d0a8a95c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-03-22sb/intel/lynxpoint/hda_verb.c: Add missing codec detect stepsAngel Pons
Lynx Point reference code version 1.9.1 and soc/intel/common/hda_verb.c perform these steps. Add them to Lynx Point as well. With this change, Lynx Point and soc/intel/common hda_verb.c files are now identical. Change-Id: I2fc592f73697a43bd5a3315ac80c77ff9f00da9b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-03-22mb/asus/p2b: Refactor southbridge ACPI stuffKeith Hui
Move (remaining) southbridge ACPI stuff into one file under sb/intel/i82371eb, that is simply included from the board's \_SB scope. Change-Id: Ibed49a800dec19534761e5ab22a6cbb1e6bd4a5d Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-22lynxpoint/broadwell: Rename LP GPIO config globalAngel Pons
Do not use the same name as the non-LP GPIO config. This allows checking at build-time that a mainboard uses the correct GPIO config format. Without this commit, there are no build-time errors when using the wrong format of GPIO config, but there would be undefined behavior at runtime. Tested by trying to build asrock/b85m_pro4 and hp/folio_9480m after toggling the `INTEL_LYNXPOINT_LP` Kconfig option (and trimming down the USB config arrays for asrock/b85m_pro4). In both cases, building failed because the necessary GPIO config global is not defined, as expected. Change-Id: Ib06507ef8179da22bdb27593daf972e788051f3a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51661 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22acpi/acpigen.h: Add more intuitive AML package closing functionsJakub Czapiga
Until now every AML package had to be closed using acpigen_pop_len(). This commit introduces set of package closing functions corresponding with their opening function names. For example acpigen_write_if() opens if-statement package, acpigen_write_if_end() closes it. Now acpigen_write_else() closes previously opened acpigen_write_if(), so acpigen_pop_len() is not required before it. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Icfdc3804cd93bde049cd11dec98758b3a639eafd Reviewed-on: https://review.coreboot.org/c/coreboot/+/50910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-15sb/intel/lynxpoint: Move S3 check out of `early_pch_init`Angel Pons
Done for consistency with other platforms. This also drops redundant S3 resume logging, as `southbridge_detect_s3_resume` already prints it. Tested on Asrock B85M Pro4, still boots and still resumes from S3. Change-Id: Id96c5aedad80702ebf343dd0a351fbd4e7b1c6c1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-15sb/intel/lynxpoint: Replace HPET_ADDRAngel Pons
The `HPET_ADDRESS` Kconfig option has the same value. Use it instead. Change-Id: I268e949d4396aa20e38f719b36cc4e6226efe082 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-10nb/intel/haswell: Finalize northbridge in ramstageAngel Pons
There's no need to finalize the northbridge in SMM. This also makes unification with Broadwell easier. Tested on Asrock B85M Pro4, still boots and registers get locked. Change-Id: I8b2c0d14a79e4fcd2e8985ce58542791cef9b1fe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-07sb/intel/lynxpoint/me.c: Reorder functionsAngel Pons
Rearrange the code to ease comparing against Broadwell. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I3143f07ed845e0c6b1444817029a437db3b959e3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-07sb/intel/lynxpoint: Finalize ME in ramstageAngel Pons
Performing ME finalization in SMM does not seem to be required. Tested on Asrock B85M Pro4, ME still gets finalized successfully. Change-Id: I9fde40a54f3fb8da2fba46c531443fdd2e067077 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-07sb/intel/lynxpoint/me.c: Use res2mmio()Angel Pons
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I87fa1ffb353135cc361ac6be30a4fc69e7f8ed47 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-03-07sb/intel/lynxpoint: Retype `mei_base_address` pointerAngel Pons
Also introduce uintptr_t cast and use PCI_BASE_ADDRESS_MEM_ATTR_MASK. Change-Id: I32fdcc6b1ffde1b0701218a3bd0a61ab827081b5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-07sb/intel/common/pciehp: Replace HP dummy device with common codeArthur Heymans
Use the common PCIEXP_HOTPLUG code to generate a dummy device for PCIe ports supporting hotplug. This allows to have control over how much resources are allocated to hotplug ports. Tested on thinkpad X220: now hotplugging a dGPU via the expresscard slot sometimes works. Change-Id: I3eec5214c9d200ef97d1ccfdc00e8ea0ee7cfbc6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph
2021-03-05sb/intel/lynxpoint: Refactor `usb_xhci_port_count_usb3`Angel Pons
Change the function parameters to avoid preprocessor usage. Change-Id: Iec43e057ed2a629e702e0f484ff7f19fe8a0311b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-05soc/intel/broadwell/pch: Use Lynx Point smbus.cAngel Pons
Continue unifying Lynx Point and Wildcat Point (PCH for Broadwell) code. Define the WPT-LP SMBus PCI device ID, add it to smbus.c of Lynx Point, and drop all now-unnecessary SMBus code from Broadwell. Change-Id: I864d7c2dd47895a3c559e2f1219425cda9fd0c17 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-03sb/intel/lynxpoint/lpc.c: Relocate lock bit writeAngel Pons
This lock bit can be set later, and should also be set for LynxPoint-H. This eases merging with Broadwell, which already sets this lock bit after `spi_finalize_ops()` in a dedicated finalisation function. Tested on Asrock B85M Pro4 (LynxPoint-H), the lock bit is now set. Change-Id: I5c32127f2b4cfdfeb0e30a64e5bdda89958933cb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47036 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01sb/intel/bd82x6x: Turn ME PCI register structs into unionsAngel Pons
This allows dropping the `pci_read_dword_ptr` and `pci_write_dword_ptr` wrappers. Change-Id: I7a6916e535fbba9f05451d5302261418f950be83 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49993 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01sb/intel/lynxpoint/me_9.x.c: Rename to me.cAngel Pons
This code will eventually support both ME 9.x and ME 10. Change-Id: Idc02ab668a0b0d51c31f33f1266d983e64fb5505 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-27sb/intel/ibexpeak: Drop useless bd82x6x pcie.cAngel Pons
The PCIe device IDs for Ibexpeak are not in bd82x6x's pcie.c driver. Thus, the code has always been dead code on Ibexpeak. Drop it. Change-Id: Ide2b4af2a187ecf98f39a9c979646a7ed959c74f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51067 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-27sb/intel/ibexpeak: Add all PCI IDs for LPCAngel Pons
Taken from document 322170-028 (5 series specification update). Tested on out-of-tree HP ProBook 6550b (HM57), fixes several issues. Without this patch, EHCI controllers had no IRQ assigned and there were unexpected exceptions about NMIs. With this patch, the issues are gone. Change-Id: Icd31dd89ba49e38a5e4c108a8361dbf636332ab8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51066 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-26sb/intel/lynxpoint: Update LPT-H magic as per RC 1.9.1Angel Pons
Add the missing PM initialization for Lynxpoint-H. There are some small changes to Lynxpoint-LP, since some register writes are common among both PCH variants. This is based on version 1.9.1 of reference code. Remove the `pch_fixups()` function. The DMI configuration is specific to Lynxpoint-H. It is not valid for Lynxpoint-LP, which does not have DMI. Tested on Asrock B85M Pro4, still boots. Registers have the new values. Without this patch, nearly all registers don't have the expected values. Change-Id: Ie3f96f2106f3c23aeb694dd6fb343099fc5784e5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47208 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-25sb/intel/lynxpoint/acpi: Add missing USB portsAngel Pons
Broadwell has these devices, so add them to Lynx Point as well. This is done in preparation to have Broadwell boards use Lynx Point ACPI code. Change-Id: Id66f169070cdfe3a6d166ca18916d4ddaf4a5fea Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46959 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-23sb/intel/lynxpoint: Refactor some GNVSKyösti Mälkki
Change-Id: I9524a44f8f4b8e286229d81d10704438f11c4580 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-04 17:48:05 +0000