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authorKyösti Mälkki <kyosti.malkki@gmail.com>2021-06-06 08:27:15 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2021-06-12 15:48:49 +0000
commit401ec98e067985431e8e263f7eecef31348d785c (patch)
tree6a03ac19a3dd34ddfc7d8ecc2e9d55602115a0c3 /src/southbridge/intel
parent8997e7b5aec28b00d9ac15922d451d60b6188325 (diff)
arch/x86/ioapic: Add get_ioapic_id() and get_ioapic_version()
Change-Id: I4ad080653c9af94a4dc73d93ddc4c8c117a682b9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/i82371eb/isa.c14
1 files changed, 3 insertions, 11 deletions
diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c
index 237ed361fd..3d586bdf80 100644
--- a/src/southbridge/intel/i82371eb/isa.c
+++ b/src/southbridge/intel/i82371eb/isa.c
@@ -54,23 +54,15 @@ static void isa_init(struct device *dev)
if (CONFIG(IOAPIC)) {
u16 reg16;
u8 ioapic_id = 2;
- volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
- volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
/* Enable IOAPIC. */
reg16 = pci_read_config16(dev, XBCS);
reg16 |= (1 << 8); /* APIC Chip Select */
pci_write_config16(dev, XBCS, reg16);
- /* Set the IOAPIC ID. */
- *ioapic_index = 0;
- *ioapic_data = ioapic_id << 24;
-
- /* Read back and verify the IOAPIC ID. */
- *ioapic_index = 0;
- reg32 = (*ioapic_data >> 24) & 0x0f;
- printk(BIOS_DEBUG, "IOAPIC ID = %x\n", reg32);
- if (reg32 != ioapic_id)
+ /* Set and verify the IOAPIC ID. */
+ set_ioapic_id(VIO_APIC_VADDR, ioapic_id);
+ if (ioapic_id != get_ioapic_id(VIO_APIC_VADDR))
die("IOAPIC error!\n");
}
}