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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-06-06 08:27:15 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-06-12 15:48:49 +0000 |
| commit | 401ec98e067985431e8e263f7eecef31348d785c (patch) | |
| tree | 6a03ac19a3dd34ddfc7d8ecc2e9d55602115a0c3 /src | |
| parent | 8997e7b5aec28b00d9ac15922d451d60b6188325 (diff) | |
arch/x86/ioapic: Add get_ioapic_id() and get_ioapic_version()
Change-Id: I4ad080653c9af94a4dc73d93ddc4c8c117a682b9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/x86/include/arch/ioapic.h | 2 | ||||
| -rw-r--r-- | src/arch/x86/ioapic.c | 10 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/lpc.c | 5 | ||||
| -rw-r--r-- | src/southbridge/intel/i82371eb/isa.c | 14 |
4 files changed, 16 insertions, 15 deletions
diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h index bdbcfbf415..839dba4977 100644 --- a/src/arch/x86/include/arch/ioapic.h +++ b/src/arch/x86/include/arch/ioapic.h @@ -29,6 +29,8 @@ u32 io_apic_read(void *ioapic_base, u32 reg); void io_apic_write(void *ioapic_base, u32 reg, u32 value); void set_ioapic_id(void *ioapic_base, u8 ioapic_id); +u8 get_ioapic_id(void *ioapic_base); +u8 get_ioapic_version(void *ioapic_base); void setup_ioapic(void *ioapic_base, u8 ioapic_id); void clear_ioapic(void *ioapic_base); diff --git a/src/arch/x86/ioapic.c b/src/arch/x86/ioapic.c index c148534351..dc88de1a8e 100644 --- a/src/arch/x86/ioapic.c +++ b/src/arch/x86/ioapic.c @@ -109,6 +109,16 @@ void set_ioapic_id(void *ioapic_base, u8 ioapic_id) } +u8 get_ioapic_id(void *ioapic_base) +{ + return (io_apic_read(ioapic_base, 0x00) >> 24) & 0x0f; +} + +u8 get_ioapic_version(void *ioapic_base) +{ + return io_apic_read(ioapic_base, 0x01) & 0xff; +} + void setup_ioapic_helper(void *ioapic_base, u8 ioapic_id, bool irq_on_fsb, bool enable_virtual_wire) { diff --git a/src/soc/intel/xeon_sp/lpc.c b/src/soc/intel/xeon_sp/lpc.c index dad0a4914d..7b46564588 100644 --- a/src/soc/intel/xeon_sp/lpc.c +++ b/src/soc/intel/xeon_sp/lpc.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <console/console.h> -#include <arch/ioapic.h> #include <intelblocks/lpc_lib.h> #include <soc/iomap.h> #include <soc/pcr_ids.h> @@ -23,9 +22,7 @@ void lpc_soc_init(struct device *dev) printk(BIOS_SPEW, "pch: lpc_init\n"); /* FSP configures IOAPIC and PCHInterrupt Config */ - printk(BIOS_SPEW, "IOAPICID 0x%x, 0x%x\n", - io_apic_read((void *)IO_APIC_ADDR, 0x00), - ((io_apic_read((void *)IO_APIC_ADDR, 0x00) & 0x0f000000) >> 24)); + /* Should read back the ID to fill ACPI IOAPIC accordingly. */ } void pch_lpc_soc_fill_io_resources(struct device *dev) diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index 237ed361fd..3d586bdf80 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -54,23 +54,15 @@ static void isa_init(struct device *dev) if (CONFIG(IOAPIC)) { u16 reg16; u8 ioapic_id = 2; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); /* Enable IOAPIC. */ reg16 = pci_read_config16(dev, XBCS); reg16 |= (1 << 8); /* APIC Chip Select */ pci_write_config16(dev, XBCS, reg16); - /* Set the IOAPIC ID. */ - *ioapic_index = 0; - *ioapic_data = ioapic_id << 24; - - /* Read back and verify the IOAPIC ID. */ - *ioapic_index = 0; - reg32 = (*ioapic_data >> 24) & 0x0f; - printk(BIOS_DEBUG, "IOAPIC ID = %x\n", reg32); - if (reg32 != ioapic_id) + /* Set and verify the IOAPIC ID. */ + set_ioapic_id(VIO_APIC_VADDR, ioapic_id); + if (ioapic_id != get_ioapic_id(VIO_APIC_VADDR)) die("IOAPIC error!\n"); } } |