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authorAngel Pons <th3fanbus@gmail.com>2021-02-23 14:23:49 +0100
committerNico Huber <nico.h@gmx.de>2021-03-07 19:23:14 +0000
commitd32b51466efb563f15ab53ad02b9c5c3baca803c (patch)
tree2558ac148639b419b3365186b29f64135cbf6998 /src/southbridge/intel
parenta3492d71c0dd1bc14e629fba9a81019ae3ab6a7e (diff)
sb/intel/lynxpoint/me.c: Use res2mmio()
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I87fa1ffb353135cc361ac6be30a4fc69e7f8ed47 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/lynxpoint/me.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/lynxpoint/me.c b/src/southbridge/intel/lynxpoint/me.c
index db23671808..8c7b7c80b7 100644
--- a/src/southbridge/intel/lynxpoint/me.c
+++ b/src/southbridge/intel/lynxpoint/me.c
@@ -698,7 +698,7 @@ static int intel_mei_setup(struct device *dev)
printk(BIOS_DEBUG, "ME: MEI resource not present!\n");
return -1;
}
- mei_base_address = (u8 *)(uintptr_t)res->base;
+ mei_base_address = res2mmio(res, 0, 0);
/* Ensure Memory and Bus Master bits are set */
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);