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2023-08-22soc/qualcomm: Add missing newlines for logsYu-Ping Wu
Change-Id: Ifd2e0043122946211aceb5ff88db0314de720fb9 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77336 Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-21soc: Remove SOC_SPECIFIC_OPTIONSElyes Haouas
Move specific options under the boolean and remove dummy SOC_SPECIFIC_OPTIONS. Change-Id: I6ae52ceb61489e5a050a60d1fbbf4250960407eb Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-21soc/intel/alderlake: add GPIO definitions for RPL PCHTim Crawford
The RPL PCH uses a different ACPI Device ID than ADL PCH. Ref: Intel 700 Series Chipset Family PCH Datasheet, Volume 1 (#743835) Change-Id: I03f47a43ff985213ad617e834db7f974f687d877 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-21vc/intel/fsp2_0: Add a copy of ADL-S IOT FSP MemInfoHob.h for RPL-S IOTMichał Żygowski
Similar situation happened last year when IoT FSP for ADL-S came out before the Client FSP variant: https://github.com/intel/FSP/issues/83 It seems IoT FSP publishes the MemInfoHob.h file much later due to legal reasons. Hack the missing file to get the builds using RPL-S IoT FSP from repo working properly. This change could be merged, subject for later revert (when the header file is published). Change-Id: Iec35db4573a3c3d011e4c1edf1c82a5c34438695 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-21soc/intel/alderlake: Guard PchPcie{Clock,Power}Gating on RPL FSPMichał Żygowski
PchPcieClockGating and PchPciePowerGating UPDs are not yet available in RPL-S IOT FSP. It also looks like those UPDs are not generally available in all public RaptorLake FSP headers yet, so guard it against SOC_INTEL_RAPTORLAKE to avoid build errors. Change-Id: Iedac21bafa3428957e054fc8fefa38f9f776772d Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77337 Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-08-21soc/intel/broadwell/pch/Kconfig: Remove dummy PCH_SPECIFIC_OPTIONSElyes Haouas
Change-Id: I21db0474157ba20cdf3eaef086aaf29fde29d6c5 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76701 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-21soc/intel/apollolake/chip.h: Use boolean type where applicableMichael Strosche
Change-Id: I6f2dc0fcc4392f77b8011221c0cf22af5da45172 Signed-off-by: Michael Strosche <michael.strosche@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-21meteorlake/include/soc/iomap: Remove unused HPET_BASE_ADDRESSElyes Haouas
Remove unused HPET_BASE_ADDRESS. It is already defined at <arch/hpet.h>. Change-Id: I8c517283e56915873b8e1798571642fd9d8a5764 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-08-20soc/samsung/exynos5250/clock: Remove space before semicolonElyes Haouas
Change-Id: Id0adfd0e25806aef836f75e83ff86a55a5d799d6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-20soc/intel/bdw/pch: Remove SOC_INTEL_BROADWELL conditionalElyes Haouas
broadwell/pch/Kconfig is sourced if SOC_INTEL_BROADWELL is true. So remove 'if SOC_INTEL_BROADWELL' condition and duplicated 'INTEL_LYNXPOINT_LP' Change-Id: I9b5676fd232b47e9d5f89f7faffdfd5d2c76984e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76699 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-20soc/intel/mtl: Enable IOE_PMC supportDinesh Gehlot
IOE_PMC support was not enabled on Meteor Lake platforms. This patch adds the bare minimum hooks to initialize and allocate a memory region for IOE operations. Additionally, this patch moves those IOE operations to a newly included IOE-specific file, Previously, PMC was responsible for these operations. BUG=b:287419766 TEST=build and verified on google/rex. Change-Id: I8bbc0b8a3e32dad5404c80bc7717ef07e3ec60b9 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77261 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-20soc/intel/alderlake_n: Allow using the microcode repoFelix Singer
Allow users of Alderlake N processors to use the microcode repository and also add their related microcode blob to the list of microcodes which should be included in the coreboot rom. Change-Id: I11c9cb13fa81118bfcb819bad5fb39731c7e3e76 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
2023-08-18soc/intel/meteorlake: Implement `soc_is_ish_partition_enabled` overrideSubrata Banik
This patch implements `soc_is_ish_partition_enabled()` override to uniquely identify the SKU type between ISH and non-ISH to conclude if ISH partition is enabled and need to retrieve the ISH version from CSE FPT by sending a HECI command. BUG=b:285405031    TEST=Able to uniquely identify the ISH SKUs while booting     to google/rex_ec_ish to dump the ISH version. Change-Id: I48358ad9e2e582e8b2274cbf4655de01f8792e6c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77177 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-18{driver, soc/intel/cmn/cse}: Refactor ISH FW Version implementationSubrata Banik
This patch uses the CSE firmware specific data to store Intel ISH firmware related information. Sending an ISH partition version information command on every boot cycle would impact the overall boot performance. This information is used by the auto-test framework to ensure the ISH firmware update is proper for in-field devices. BUG=b:285405031 TEST=Able to build and boot google/rex. Verified ISH FW version is getting displayed across warm resets without impacting the boot time. Change-Id: I0242c26dd90d834815799f54740d8147ff9d45b7 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-08-18soc/intel/cmn/cse: Display CSE RW FW version by default for LITE SKUSubrata Banik
This patch selects SOC_INTEL_STORE_CSE_FW_VERSION config by default for CSE LITE SKU. It helps to dump the CSE RW firmware version which further consumed by auto-test infrastructure to ensure CSE RW firmware update is successful. BUG=b:285405031 TEST=Able to build and boot google/rex. Verified CSE RW FW version (for LITE SKU) is getting displayed without impacting the boot time. Change-Id: Iba5903c73c0a45b01e6473714e0d5f759c061825 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77175 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-18soc/intel/cmn/cse: Refactor CSE RW FW Version implementationSubrata Banik
This patch introduces a CSE firmware specific data in order to store Intel CSE and associated firmware related information which requires a sync between Pre-RAM and Post-RAM phase. This information will be used further to retrieve currently running CSE RW firmware instead of fetching the version information by sending a HECI cmd (which consumes 7ms-15ms depending upon the CSE operational state). Current implementation attempts to simply the CSE RW FW version store and retrieval operations as below * CSE sync in romstage (aka Pre-RAM) - Relying on .bss segment to store the CSE info data in absence of real physical memory and sync back into the CBMEM once available (after FSP-M exits). * CSE sync in ramstage (aka Post-RAM) - Directly stored the CSE RW version into the CBMEM (as CBMEM is online). BUG=b:285405031 TEST=Able to build and boot google/rex. Verified CSE RW FW version (for LITE SKU) is getting displayed without impacting the boot time. w/o this patch: 10:start of ramstage         722,257 (43) 17:starting LZ4 decompress (ignore for x86)  723,777 (1,520) w/ this patch: 10:start of ramstage                         722,257 (43) 17:starting LZ4 decompress (ignore for x86)  723,777 (1,520) Change-Id: Ia873af512851a682cf1fac0e128d842562a316ab Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77174 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2023-08-17soc/intel/alderlake: Set PchHdaSdiEnable for Alder LakeSean Rhodes
This UPD does exist for Alder Lake, so set it there also. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If2f405804ab675aaf6dbf8b12d149566055b9eef Reviewed-on: https://review.coreboot.org/c/coreboot/+/77125 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-17soc/intel/alderlake: Add provision to show pre-boot splash screenSubrata Banik
This patch adds the ability to show a pre-boot splash screen on Meteor Lake systems using FSP-S. The patch calls into `fsp_convert_bmp_to_gop_blt()` when the `BMP_LOGO` config is enabled. This function converts a BMP file to a BLT buffer, which is then used by FSP-S to render the splash screen. Additionally, increase the heap size (malloc'able size) upto 512KB (when BMP_LOGO config is enabled) to accommodate high resolution logo file. BUG=b:284799726 TEST=Able to see splash screen while booting google/marasov with BMP_LOGO config enable. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9f4d1bc0aa991e784624ca19ba96a259ab8ddfa6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-17soc/intel/meteorlake: Enable LZ4 compression for logo CBFS fileSubrata Banik
This patch selects LZ4 decompression for logo CBFS file. Able to save 2ms of the boot time when HAVE_FSP_LOGO_SUPPORT config is enabled. However, the compressed BMP logo size is increased by ~2KB. Raw BMP Image size is ~97KB. BUG=b:284799726 TEST=Able to see pre-boot splash screen while booting google/rex with 32MB (W25Q256JWEIM) SPI-Flash. w/o this patch: sudo cbfstool image-screebo4es.bin print -r FW_MAIN_A FMAP REGION: FW_MAIN_A Name Offset Type Size Comp ... ... logo.bmp 0x167480 raw 6172 LZMA (97078 decompressed) ... 15:starting LZMA decompress (ignore for x86)  849,090 (1,022) 16:finished LZMA decompress (ignore for x86)  851,207 (2,116) w/ this patch: sudo cbfstool image-screebo4es.bin print -r FW_MAIN_A FMAP REGION: FW_MAIN_A Name Offset Type Size Comp ... ... logo.bmp 0x167480 raw 8568 LZ4 (97078 decompressed) ... 17:starting LZ4 decompress (ignore for x86)   849,419 (1,279) 18:finished LZ4 decompress (ignore for x86)   849,559 (140) Change-Id: I856c39146a5ec0faf44c1cd37fa7c0d7296bf673 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-17soc/intel: Update all references to ESE as ISSEUsha P
Intel has rebranded ESE as ISSE (Intel Silicon Security Engine),so all references to ESE is updated to ISSE in the current coreboot code. BUG=None TEST=Build all the variants based on Intel Meteor Lake SoC Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I1f8785704706d56a35e94a0f3386bc551cd1f263 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77241 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-16soc/intel/alderlake/chip.h: Use boolean type where applicableMichael Strosche
Change-Id: If26184058536590b70bbb03209913118307ff6c5 Signed-off-by: Michael Strosche <michael.strosche@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76830 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-16ACPI: Add usb_charge_mode_from_gnvs()Kyösti Mälkki
Early Chromebook generations stored the information about USB port power control for S3/S5 sleepstates in GNVS, although the configuration is static. Reduce code duplication and react to ACPI S4 as if it was ACPI S5 request. Change-Id: I7e6f37a023b0e9317dcf0355dfa70e28d51cdad9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-08-16vendorcode/fsp: Rename GLK to Gemini Lake to match other SOCsSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ic559b78e6444acec36d437fe3c139b692a3f4d0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/77126 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-08-15nb,soc/amd/*/northbridge: use mmio_range to add IOAPIC2 resourcesFelix Held
Instead of open coding this, use the mmio_range helper function to tell the resource allocator about the northbridge's IOAPIC's MMIO. This change sets the IORESOURCE_RESERVE and IORESOURCE_STORED bits in the resource flags that weren't set before, but mmio_range is already used elsewhere for similar purposes. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id66a73cdb22fd551e4359914ba5513313dcc3193 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-08-15soc/amd/common/lpc: use fixed_io_range_flags instead of open codingFelix Held
Instead of open coding the same functionality, use fixed_io_range_flags to tell the resource allocator about the FCH subtractively decoding the first 0x1000 bytes of I/O space. Also update the comment to match the code. TEST=On Mandolin the flags of this resource stay the same (0xc0040100). Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia30a87a4e37c98248568476b74af2730a3c0e88d Reviewed-on: https://review.coreboot.org/c/coreboot/+/77170 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-15soc/amd/common/data_fabric/domain: use get_iohc_fabric_idFelix Held
Use get_iohc_fabric_id() to translate the coreboot domain's number into the destination data fabric ID of the PCI root. This allows using the coreboot domain 0 as primary domain of the SoC in all cases, so it's still possible to use config_of_soc(). This allows dropping the SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN_MULTI_PCI_ROOT Kconfig option and do the check if the destination fabric ID in the PCI bus number, MMIO, and IO decode registers is the correct one for the domain without the need to use a non-zero number for the primary PCI root domain. TEST=Mandolin still boots and the PCI bus, IO and MMIO resources still get reported correctly. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I880ee0bf5c185cfe4af7de0d39581eb951ee603a Reviewed-on: https://review.coreboot.org/c/coreboot/+/77169 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-15soc/amd/*/root_complex: introduce get_iohc_fabric_idFelix Held
Implement get_iohc_fabric_id for each SoC that translates the coreboot domain number to the fabric ID of the corresponding PCI root. This allows the primary domain to have the number 0 even though the destination data fabric ID will be non-zero. Keeping the primary domain number 0 allows to use config_of_soc() which can be resolved at link time and not need to dynamically find the SoC device to get the config. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6538a777619eed974b449fc70d3fe3084ba447dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/77168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-08-15soc/nvidia/tegra210/mipi-phy: Remove space before semicolonElyes Haouas
Change-Id: I107e2952bcca864a1cacf240cca301011df44719 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-15soc/samsung/exynos5420/clock: Remove space before semicolonElyes Haouas
Change-Id: Iab1ac1609f117a1a80bc025bcbe4659189bdb676 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-14soc/mediatek/mt8173/mt6391: Remove space before semicolonElyes Haouas
Change-Id: I88668d8c69da68cc28bae287f573f650f28da32e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-08-13soc/amd/common/data_fabric: handle multiple PCI root domainsFelix Held
In the case of SoCs hat have more than one PCI root, we need to check to which PCI root the PCI bus number, IO and MMIO regions configured in the data fabric registers get routed to and only tell the resource allocator about the resources that get routed to the current PCI root domain. For this the numbers of the domains need to match the PCI root's destination data fabric ID. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib6a6412f733d321044678d2b064c33418a53861c Reviewed-on: https://review.coreboot.org/c/coreboot/+/77113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-13soc/intel/cse: Add config to enable PSR data backup for CSE Lite SKUKrishna Prasad Bhat
Intel Platform Service Record (PSR) provides on-platform persistent and tamper resistant ledgers and counters. Key events captured within the Intel PSR Event Ledger, e.g., Chassis Intrusion Detection, can be observed over the life cycle of the platform to help assess confidence. Counters for platform S0 operational use and power state transitions can be assessed to aid in the determination of general wear or correlations of other platform events when determining platform decommission plans (repurpose, resell, recycle). PSR data is created and stored in CSE data partition. In platforms that employ CSE Lite SKU firmware, a firmware downgrade involves clearing of CSE data partition which results in PSR data being lost. CSE Lite SKU firmware supports a command to backup PSR data before initiating a firmware downgrade. Add a config to support this PSR data backup flow. BRANCH=None BUG=b:273207144 Change-Id: Iad1ce2906177081c103ef4d4bcef78fa2c95026f Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-08-12soc/intel/xeon_sp/*/Kconfig: Refactor out and remove SOC_SPECIFIC_OPTIONSElyes Haouas
Move specific selections to {cpx,skx,spr} and remove dummy SOC_SPECIFIC_OPTIONS Change-Id: I71e41deb0478bf4d04395c88fc7b68df1ea83ac0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-12soc/amd/common/data_fabric: read PCI bus decoding from DF registersFelix Held
The data fabric also controls which PCI bus numbers get decoded to the PCI root. In order for the resource allocator to know how the hardware is configured, read the corresponding data fabric registers to get the information that then gets passed to the allocator. Picasso, Cezanne, Mendocino and Rembrandt only support one PCI segment with 256 buses while the Phoenix and Glinda data fabric hardware has support for more PCI segments. Due to this change, the register layout is different and incompatible between those two, so introduce the SOC_AMD_COMMON_BLOCK_DATA_FABRIC_MULTI_PCI_SEGMENT Kconfig option for a SoC to specify which implementation is needed. At the moment, coreboot doesn't have support for multiple PCI segments and the code doesn't support PCI segments other than segment 0. On Picasso the PCI bus number limit read back from the data fabric register is 255 even though CONFIG_ECAM_MMCONF_BUS_NUMBER is set to 64, so also make sure that the bus and limit returned by data_fabric_get_pci_bus_numbers is within the expected limits. TEST=PCI bus allocation still works on Mandolin (Picasso) and Birman (Phoenix). Picasso has 64 PCI buses. coreboot puts this info into the resource producer in _SB\PCI0\_CRS which the Linux kernel reads: * coreboot: PCI0 _CRS: adding busses [0-3f] * Linux: pci_bus 0000:00: root bus resource [bus 00-3f] This matches the information in the ACPI MCFG table. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ide5fa9b3e95cfd59232048910cc8feacb6dbdb94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77080 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-11soc/amd/glinda/Kconfig: fix commentFelix Held
The SOC_AMD_REMBRANDT_BASE comment at the end of Glinda's Kconfig is probably a leftover from the Mendocino/Rembrandt SoC this file was copied from. Change it to SOC_AMD_GLINDA to match the corresponding 'if SOC_AMD_GLINDA' in the file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I85132e4840c1bc713cfc2f3493f800d66edd10ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/77121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2023-08-11soc/intel/braswell: Adjust status of IOSF ACPI objectMatt DeVillier
Neither Windows nor mainline Linux make use of IOSF on the Braswell platform, so adjust the ACPI status return value based on CONFIG(CHROMEOS) to prevent an unknown device being listed in Windows device manager. TEST=build/boot Win11, Linux 6.2 on google/edgar Change-Id: Ic51624ffd816d48c007c13d510601cf8cbf1edc4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-08-11soc/intel/baytrail: Adjust status of IOSF ACPI objectMatt DeVillier
Neither Windows nor mainline Linux make use of IOSF on the Baytrail platform, so adjust the ACPI status return value based on CONFIG(CHROMEOS) to prevent an unknown device being listed in Windows device manager. TEST=build/boot Win11, Linux 6.2 on google/swanky Change-Id: I249028c57cc704955cf5a11e2088780ef58e16cf Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77141 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-11soc/intel/alderlake: Remove dummy CPU_SPECIFIC_OPTIONSElyes Haouas
Change-Id: I83574032ef506a411571e8363f476f322ac13e5e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76686 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-11soc/amd/common/data_fabric/domain: set and use max_subordinateFelix Held
Set the maximum subordinate bus number of the domain to the last PCI bus number that is decoded to this PCI root. This makes sure that the resource allocator knows the maximum number of PCI buses on this PCI root to not assign bus numbers to buses below this PCI root that aren't routed to that PCI root. Now that we have this info in the link list structure or the domain device, we can pass the max_subordinate field to the acpigen_resource_producer_bus_number call and can leave the subordinate number after pci_domain_scan_bus is done unchanged instead of setting it to the limit. TEST=On Mandolin both the bus resource producer in _SB\PCI0\_CRS and the PCI bus number allocation remain unchanged. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2ee75b2a7054a306b0c7d98c5357391c029187bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/77112 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-11soc/amd: Add definition of SPI ROM remappingZheng Bao
Change-Id: Icafa36ae2e07068c276600067bba1d0377f0824b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74258 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-11soc/intel/meteorlake: Add provision to show pre-boot splash screenSubrata Banik
This patch adds the ability to show a pre-boot splash screen on Meteor Lake systems using FSP-S. The patch calls into `fsp_convert_bmp_to_gop_blt()` when the `BMP_LOGO` config is enabled. This function converts a BMP file to a BLT buffer, which is then used by FSP-S to render the splash screen. Additionally, increase the heap size (malloc'able size) upto 512KB (when BMP_LOGO config is enabled) to accommodate high resolution logo file. BUG=b:284799726 TEST=Able to see pre-boot splash screen while booting google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3608bfacc21574e12cde0e2012a16e6388ce54df Reviewed-on: https://review.coreboot.org/c/coreboot/+/76922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-08-11soc/intel/alderlake: Disable PCIe clock gatingPatrick Rudolph
Intel requires that all enabled PCIe PCH ports have a CLK_REQ signal connected. The CLK_REQ is used to wake the silicon when link entered L1 link-state. L1 link-state is also entered on PCI-PM D3, even with ASPM L1 disabled. When no CLK_REQ signal is used, for example when it's using a free running clock the silicon will never wake from L1 link state. This will trigger a MCE. Starting with FSP MR4 the UPD 'PchPcieClockGating' allows to work around this issue by disabling ClockGating. Disabling ClockGating should be avoided as the silicon draws more power when it is idle. TEST: Verified on two boards, one with missing CLK_REQ on a PCH root port, that the code does the right decision to disable UPD PchPcieClockGating and PchPciePowerGating when necessary. Change-Id: I673bbdbadc9afbed6a7bd5ce9f35dc70716d875b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-08-10soc/amd/mendocino/include/data_fabric: fix IOMS0_FABRIC_ID for RembrandtFelix Held
Rembrandt has different data fabric component IDs compared to Mendocino. PPR #56558 Rev 3.04 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3c840a3e071a289d9e02143ee790c26faeda029d Reviewed-on: https://review.coreboot.org/c/coreboot/+/77081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-08-10soc/amd/common/psp_verstage: Enable Legacy IO only on older SoCsKarthikeyan Ramasubramanian
With reference to the Picasso PPR 55570 Rev 3.18, LegacyIoEn bit is 0 on reset and setting it will enable the decoding of the following legacy IO ports: 0x20, 0x21, 0xA0, 0xA1 (PIC); 0x40, 0x41, 0x42, 0x43, 0x61 (8254 timer); 0x70, 0x71, 0x72, 0x73 (RTC); 0x92. Verstage does not use those legacy IO ports. Also newer SoCs like Phoenix do not support Legacy I/O registers to access Power Management registers and accessing them from PSP verstage causes a hang. Hence enable legacy IO only on platforms that support it. BUG=b::284984667 TEST=Build Myst BIOS image with PSP Verstage. Boot to OS successfully with PSP verstage. Change-Id: I5e74b4cd1fa7e942770976e5e2197ded47503660 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76692 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-10soc/intel/jasperlake: Add configs for USB 3.1 Gen2 EV settingsChia-Ling Hou
Add configs for USB 3.1 Gen2 electrical validation (EV) settings so that people can set the EV settings per board in device tree. BUG=b:285811345 TEST=build coreboot and fsp with enabled fw_debug. Flashed to taranza and checked the log. All usb configs were set correctly. Change-Id: Iecd12d3db76b63ad99887dee5991d94d47f138fd Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76246 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-08-09treewide: Get rid of "NO_DDRx" selectionElyes Haouas
Change-Id: I8fa26e7a398eee855c31a76f0f89b4111368c2a6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-09soc/intel/baytrail: Specify supported memory typeElyes Haouas
Change-Id: Ie360ca3640a4774e3baec36468a69f76fcd1217b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-09soc/amd/glinda/include/data_fabric: add DF PCI config map registerFelix Held
PPRs #57254 Rev 1.52 and #57255 Rev 0.33 were used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie54fd6c5a82f368018d0b5fb811a6c9220c2c70b Reviewed-on: https://review.coreboot.org/c/coreboot/+/77079 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-09soc/amd/phoenix/include/data_fabric: add DF PCI config map registerFelix Held
PPRs #57019 Rev 3.05 and #57396 Rev 3.06 were used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id0fe478a710ecc1f2c8b36347aaf2d1634ebba9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/77078 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-09soc/amd/mendocino/include/data_fabric: add DF PCI config map registerFelix Held
PPRs #57243 Rev 3.02 and #56558 Rev 3.04 were used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibabe8faa79e3dcd02f4c885d29b9634645947b98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77077 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-09soc/amd/cezanne/include/data_fabric: add DF PCI config map registerFelix Held
PPR #56569 Rev 3.04 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idfac7d996c6de9ea7c6adf2760de0ad97ffb9ec0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-09soc/amd/picasso/include/data_fabric: add DF PCI config map registerFelix Held
PPR #55570 Rev 3.18 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ide492f4479b85cd885044bbf74d8bf18c12e552b Reviewed-on: https://review.coreboot.org/c/coreboot/+/77075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-09soc/amd/common/include/data_fabric: add missing device/device.h includeFelix Held
device/device.h provides struct device. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie03f6d15d94f2858e293b9f57505034263c03bbe Reviewed-on: https://review.coreboot.org/c/coreboot/+/77074 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-09soc/amd/*: Fix UART ACPI device statusMatt DeVillier
Prior to commit d1c0f958d198 ("acpi: Call acpi_fill_ssdt() only for enabled devices"), uart_inject_ssdt() was used to set the ACPI status (_STA) for both enabled and disabled devices. The aforementioned commit limited it to being called only on enabled devices, which left disabled devices without any _STA method at all -- which the OS assumes means that the device is present and enabled. To fix this, create the _STA method in the UART asl code for each port, and set the return value to a name variable (STAT) which defaults to 0 (not present/disabled). Then, have uart_inject_ssdt() set STAT to present and enabled (0xF) for UARTs actually present on the board. TEST=build/boot google/skyrim (frostflow), dump ACPI tables, and verify that _STA returns 0xF only for UARTs enabled in devicetree. Change-Id: Id89e74c3ea7f53280935898ee35311b7cf3b152a Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77092 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-09soc/amd/stoneyridge: use SoC common uart opsMatt DeVillier
Define the UARTs as MMIO devices in the chipset devicetrees. Drop ACPI _STA in asl since now handled by common SSDT generator. Implement wait_for_aoac_enabled() since required by SoC common code, and ensure compiled during all stages necessary. TEST=build/boot google/liara, verify console UART still functional. Change-Id: Ibecafdfa189d9c63a29b63759c5b965d03719009 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77093 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-09Revert "soc/intel/{adl, cmn/pcie}: Fix ASPM configuration enum definitions"Jeremy Soller
This reverts commit 5dfec718290609dc0fd0331070ad703107e0b7e7. Reason for revert: This change made it impossible to disable ASPM by FSP parameter. ASPM_DISABLE would result in the FSP parameter not being programmed, causing it to be the FSP default value instead. This additionally fixes MTL to match ADL. Change-Id: I60c0ea08513fcb0035449ea3fef1681de528c545 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75280 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-09soc/intel/xeon_sp/spr: Add soc_config_iio to set IIO UPD from mainboardJohnny Lin
To deduplicate mainboard mainboard_config_iio since there are a few SPR-SP mainboards now. The flow would be soc function initialize_iio_upd initializes the table with the default values which are mostly zero, then mainboard can overwrite it by soc_config_iio. Change-Id: I72d74241fcad4c85a95f6d14587418f544caadd9 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76185 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-09soc/intel/xeon_sp/ebg: Add periodic SMI bits definitionMichał Żygowski
Change-Id: Ia906a115538964628958bb4b6e3de3aa71577cce Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76252 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-08cpu/amd/pi/00730F01: Use common code for mp_initArthur Heymans
TEST=APU2 still boots and doesn't show any new errors in dmesg. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia9f0eb3df8fd2dfe395f616da981cc3a0cd3b29d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-08-08soc/amd/common/data_fabric/domain: read IO decode windows from registersFelix Held
Before add_io_regions only reported one fixed IO range to the resource allocator that covered the whole IO range from 0x0000 to 0xffff. Instead read the data fabric IO space decode base and limit address register pairs to get the actual IO port decoding from the data fabric registers. This will also help with adding support for multiple PCI root domains to the common data fabric domain code so that Genoa can use it. In that case each PCI root domain will only decode a part of the whole IO port range. Beware that the data fabric IO base and limit fields can contain values that correspond to IO port addresses far outside of the addressable IO port range. In case of Picasso, the IO limit read from the only enabled DF IO range register would be 0x1ffffff after converting the raw data to an IO port address. To not give the resource allocator wrong constraints make sure that the IO limit we report will be at maximum 0xffff. TEST=On Mandolin (Picasso) and Birman (Phoenix) the full range of IO port addresses still gets reported as a domain IO resource producer like before the patch: DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I087d96f7bdaae0d7b53089f6abaf0500a4b064e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-08soc/amd/glinda/include/data_fabric: add data fabric IO decode registersFelix Held
PPRs #57254 Rev 1.52 and #57255 Rev 0.33 were used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia58e26caa1ba910b41911991b176a1ac8c4e0065 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-08soc/amd/phoenix/include/data_fabric: add data fabric IO decode registersFelix Held
PPRs #57019 Rev 3.05 and #57396 Rev 3.06 were used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I769dc317115981391cf0f4e0b743c600407a6eb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76958 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-08soc/amd/mendocino/include/data_fabric: add DF IO decode registersFelix Held
PPRs #57243 Rev 3.02 and #56558 Rev 3.04 were used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic68e73e28362abc5d812839b40282114c7ba25ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/76957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-08soc/amd/cezanne/include/data_fabric: add data fabric IO decode registersFelix Held
PPR #56569 Rev 3.04 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifcae9c9ad664d50100cd40692fd9631845f76671 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-08soc/amd/picasso/include/data_fabric: add data fabric IO decode registersFelix Held
PPR #55570 Rev 3.18 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I61d4fca48d71010bbc4bd94a2fb8889bad08f1cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/76935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-08-08soc/amd/common/data_fabric/domain: rename add_io_regionsFelix Held
Rename add_io_regions to add_data_fabric_io_regions to be consistent with add_data_fabric_mmio_regions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia990cc14dd6dc162ad614a6e9e0b36426cb04670 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-08-08soc/amd/common/data_fabric/domain: factor out report_data_fabric_ioFelix Held
As a preparation to read the IO decode ranges from the data fabric registers instead of having it hard-coded, factor out the report_data_fabric_io function to report one IO producer region from add_io_regions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I51c3f8cd6749623f1a4bad14873d53b8a52be737 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76933 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-08soc/amd/*/include/data_fabric: add dst_ prefix to fabric_id fieldFelix Held
Rename the fabric_id struct field in the df_mmio_control union to dst_fabric_id to both better match the register definitions and also be a bit clearer about what this is doing. Also use tabs for indentation in the struct inside the df_mmio_control union. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0a17d82a5d7b66a8f84854f21fbbb319da81ac43 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-08-08soc/amd/*/include/data_fabric: reorder register definitionsFelix Held
Order the data fabric register definitions by function number and register offset. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia3066ad0f564520cb322a3e41a413eb3bf51260d Reviewed-on: https://review.coreboot.org/c/coreboot/+/76923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-08soc/amd/*/include/data_fabric: rename D18F0_DRAM_* to DF_DRAM_*Felix Held
Now that the data fabric PCI device functions are included in the register definitions, the remaining data fabric device function numbers can be dropped from the define names. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1a26402b8078d288a7e32c1668591d001fa3ede9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76889 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-08soc/amd/*/include/data_fabric: rename D18F0_MMIO_* to DF_MMIO_*Felix Held
Now that the data fabric PCI device functions are included in the register definitions, the remaining data fabric device function numbers can be dropped from the define names. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia0355838ac1d513ba562fd6fb4672342dd383498 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76888 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-08soc/amd/common/data_fabric_helper: use DF broadcast read/write functionsFelix Held
Instead of open coding the broadcast data fabric PCI register access in the functions for indirect non-broadcast data fabric register access, just use the existing data_fabric_broadcast_[read,write]32 functions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I174c1e6ee4856d97c5ec6d07bb8c217d6df9425f Reviewed-on: https://review.coreboot.org/c/coreboot/+/76887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-08soc/amd/common/include/data_fabric_defs: introduce & use DF_REG_* macrosFelix Held
To have both the PCI function number and the register offset into the config space of that function of the data fabric device in the data fabric register definitions, introduce and use the DF_REG_ID, DF_REG_FN and DF_REG_REG macros. The DF_REG_ID macro is used for register definitions where both the function number and the register offset are specified, and the DF_REG_FN and DF_REG_REG macros are used to extract the function number and the register offset from the register defines. This will allow having one define for accessing an indexed group of registers that are on different functions of the data fabric device. TEST=MMIO resources read from the data fabric's MMIO decode registers don't change on Mandolin and the ACPI CRAT table is also identical. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I63a284b26081c170a217b082b100c482f6158e7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/76886 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-08ACPI: Add helper fill_fadt_extended_pm_io()Kyösti Mälkki
Once platform code has filled in the (legacy) ACPI PM register map, added function will fill in the extended entries in FADT. TEST=samsung/lumpy and amd/mandolin FADT stays unchanged. Change-Id: I90925fce35458cf5480bfefc7cdddebd41b42058 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-06soc/mediatek/mt8188: Support ARM arch timerYidi Lin
Use ARM architectual timer by initializing frequency to 13 MHz. Since system timer is the source of the architectual timer, we also call `timer_prepare` in `init_timer`. BUG=b:229800119 TEST=run `suite:faft_bios` to verify the firmware stability. check timestamps by cbmem. Cq-Depend: chromium:4747539 Change-Id: I8b1348044e4c92984510604b7f61611e13284d86 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76919 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-06device, soc: Add SPDX license headers to MakefilesMartin Roth
To help identify the licenses of the various files contained in the coreboot source, we've added SPDX headers to the top of all of the .c and .h files. This extends that practice to Makefiles. Any file in the coreboot project without a specific license is bound to the license of the overall coreboot project, GPL Version 2. This patch adds the GPL V2 license identifier to the top of all makefiles in the device and soc directories that don't already have an SPDX license line at the top. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I89c05c7c1c39424de2e3547c10661c7e3f58b8f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2023-08-06soc/intel/common/tcss: Configure USB-C ports with attached devicesCoolStar
Inspect all type-C USB ports, check if there is a USB device attached, and if so, send the connection request to the PMC. This allows for any attached USB2/USB3 devices to be used for booting by the payload. Since this functionality is only needed by ChromeOS devices with TCSS running upstream coreboot, introduce a new Kconfig to guard its use. Boards needing it will select it in subsequent commits. TEST=tested with rest of patch train Change-Id: I69522dbcc8cae6bbf41659ae653107d0e031c812 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72909 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-06soc/intel/common/block/tcss: Fix printk formattingMatt DeVillier
Variable 'i' is unsigned, so use %zu vs %zd. Change-Id: I5f5b28796b30285e81a94c37e686a9e763cab204 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76943 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-05src/*/post_code.h: Change post code prefix to POSTCODEYuchen He
The prefix POSTCODE makes it clear that the macro is a post code. Hence, replace related macros starting with POST to POSTCODE and also replace every instance the macros are invoked with the new name. The files was changed by running the following bash script from the top level directory. header="src/soc/amd/common/block/include/amdblocks/post_codes.h \ src/include/cpu/intel/post_codes.h \ src/soc/intel/common/block/include/intelblocks/post_codes.h" array=`grep -r "#define POST_" $header | \ tr '\t' ' ' | cut -d ":" -f 2 | cut -d " " -f 2` for str in $array; do splitstr=`echo $str | cut -d '_' -f2-` grep -r $str src | cut -d ':' -f 1 | \ xargs sed -i'' -e "s/$str/POSTCODE_$splitstr/g" done Change-Id: Id2ca654126fc5b96e6b40d222bb636bbf39ab7ad Signed-off-by: Yuchen He <yuchenhe126@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76044 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-04soc/amd/phoenix: Makefile change to include split hash tableKarthikeyan Ramasubramanian
Include multiple hash tables into relevant CBFS. BUG=b:277292697 TEST=Ensure that all multiple hash tables are part of Myst BIOS image with PSP verstage enabled. Change-Id: I1601f4a01db5b2bbf8b5636ef9e69e41c1d9a980 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76589 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-04soc/amd/phoenix: Add SVC call to inject v2 hash tablesKarthikeyan Ramasubramanian
On mainboards using Phoenix SoC with PSP verstage enabled, to accommodate growing number of PSP binaries, multiple smaller hash tables are introduced. Also some hash tables are in V2 format identifying the concerned PSP binaries using UUID. Add SVC calls to support multiple hash tables with different versions. BUG=b:277292697 TEST=Build and boot to OS in Myst with PSP verstage enabled. Ensure that all the hash tables are injected successfully. Ensure that PSP validated all the signed PSP binaries using the injected hash tables successfully. Change-Id: I64e1b1af55cb95067403e89da4fb31bec704cd4f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76588 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-04soc/amd/common/psp_verstage: Support multiple hash tablesKarthikeyan Ramasubramanian
Currently PSP verstage updates PSP bootloader with one unified hash table containing hashes for all the signed PSP binaries to be validated. With growing number of PSP binaries to validate and memory constraints in PSP, there is a requirement to split and update the hash table into multiple smaller chunks. Hence change the update_psp_fw_hash_table() signature such that the hash tables are updated in a chipset specific way. BUG=b:277292697 TEST=Build and boot to OS in Myst with PSP verstage enabled. Build the Skyrim BIOS image and confirm that the hash table is identical before and after this change. Change-Id: I75aac5bc5e7f61069be25d801d0838fdf565d3d1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76587 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-04soc/amd/common/data_fabric_helper: add comment about cfg_inst_acc_enFelix Held
Since all indirect data fabric register accesses will be non-broadcast accesses that target a specific data fabric instance, the cfg_inst_acc_en bit in the DF_FICAA_BIOS register will always be set since that makes the indirect access target only a specific data fabric instance. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9aff01750c2c1e3506141b3ed293a980a64f8fac Reviewed-on: https://review.coreboot.org/c/coreboot/+/76885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-08-04soc/intel/meteorlake: Hook up UPD for C1 C-state auto-demotionSukumar Ghorai
FSP has a parameter to enable/disable c1-state autodemotion feature. Boards/Baseboard can choose to use this feature as per requirement. This patch hooks up this parameter to devicetree. BUG=b:286328295 TEST=Check code compiles & boot google/rex, and correct value has been passed to FSP. Change-Id: I2cc60bd297271fcb3000c0298af71208e3be60fc Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76826 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2023-08-04soc/intel/mtl: Change default for debug consent from 3 to 6Kane Chen
USB DBC is very helpful for SoC debug. TraceHub needs to be enabled in coreboot if debug consent == 2 or 4. Debug consent == 6 enables USB DBC without TraceHub enabled. This patch updates the Kconfig help text to meet PlatformDebugOption in MTL and changes debug consent to 6 in default to provide basic SoC debug capability. TEST=Boot to OS on screebo and DBC connection is OK. Change-Id: Ic12528bdd8b1feda7f1b65045c863341f932d3a2 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76880 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-04soc/sifive/fu540/Kconfig: Fix opensbi platformMaximilian Brune
commit 9a7a677 from opensbi project moved the fu540 platform to generic code and commit 26998f3 from opensbi removed the old non generic platform. Therefore opensbi platform needs to change to generic. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I76aa3d386936b331785a23edb8deb0d73609be47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-04soc/intel/common: Return CB_ERR when cse_data_clear_request() failsKrishna Prasad Bhat
cse_prep_for_rw_update() should return CB_ERR when cse_data_clear_request fails. It was modified to CB_SUCCESS in this commit ad6d3128f87c ("soc/intel/common: Use enum cb_err values") BRANCH=None BUG=None TEST=Verify the system goes to recovery during downgrade when cse_data_clear_request() fails. Change-Id: Ibbccb827765afa54e5ab1b386fa46093b803977a Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-08-04soc/intel/meteorlake: Generate new TME key on each warm bootPratikkumar Prajapati
Enable config TME_KEY_REGENERATION_ON_WARM_BOOT for Intel Meteor Lake SOCs. This config allows Intel FSP to programs TME engine to generate a new key for each warm boot and exclude CBMEM region from being encrypted by TME. Bug=b:276120526 TEST= Boot up the system, generate kernel crash using following commands: $ echo 1 > /proc/sys/kernel/sysrq $ echo "c" > /proc/sysrq-trigger System performs warm boot automatically. Once it is booted, execute following commands in linux console of the DUT and confirm ramoops can be read. $ cat /sys/fs/pstore/console-ramoops-0 S0ix also tested and found working. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: I3161ab99b83fb7765646be31978942f271ba1f9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/75627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-03soc/intel/common/block/cse/Kconfig: Remove unused symbolsElyes Haouas
Change-Id: I35742721e049102a3e153b857824073a5d257cc3 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76693 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03soc/intel/xeon_sp/spr/Kconfig: Remove unused MAX_MC_CHNElyes Haouas
Change-Id: Ia4011a0f29d360fbe46a5e052e2acb3d23d8ceaf Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76695 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03soc/intel/jasperlake: Remove dummy CPU_SPECIFIC_OPTIONSElyes Haouas
Change-Id: I5ad1a1bf51bb7a451239252f01a90c1d4d94ba49 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76685 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03soc/intel/skylake: Remove dummy CPU_SPECIFIC_OPTIONSElyes Haouas
Change-Id: Iea0e55c6c55635976dad0422470f3927bdc26e35 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-03soc/intel/tigerlake: Remove dummy CPU_SPECIFIC_OPTIONSElyes Haouas
Change-Id: Id268943b9347fdb54e07b55c0a2a18ac77bb3a58 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-03soc/intel/xeon_sp/Kconfig: Remove useless USE_FSP2_0_DRIVERElyes Haouas
Change-Id: Ic384ee804e217ba79f7e191f122ec61565abfc40 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-03soc/intel/xeon_sp/spr/Kconfig: Remove unused SIPI_FINAL_TIMEOUTElyes Haouas
Change-Id: I915e0e942adf33175fdc9fe055fce013824d6c0f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76698 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03soc/intel/broadwell/Kconfig: Remove dummy SOC_SPECIFIC_OPTIONSElyes Haouas
Change-Id: I4ccb8d38f18cb440f54723cc1f29e25b82dac8ee Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76700 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03soc/intel/meteorlake: Set UPDs for TME exclusion range and new key genPratikkumar Prajapati
Set UPD params GenerateNewTmeKey, TmeExcludeBase, and TmeExcludeSize when TME_KEY_REGENERATION_ON_WARM_BOOT config is enabled. These UPDs are programmed only when INTEL_TME is enabled. Bug=b:276120526 TEST=Able to build REX platform. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: Ib8d33f470977ce8db2fd137bab9c63e325b4a32d Reviewed-on: https://review.coreboot.org/c/coreboot/+/75626 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03soc/intel/common: Merge TME new key gen and exclusion range configsPratikkumar Prajapati
Merge TME_KEY_REGENERATION_ON_WARM_BOOT and TME_EXCLUDE_CBMEM_ENCRYPTION config options under new config option named TME_KEY_REGENERATION_ON_WARM_BOOT. Program Intel TME to generate a new key for each warm boot. TME always generates a new key on each cold boot. With this option enabled TME generates a new key even in warm boot. Without this option TME reuses the key for warm boot. If a new key is generated on warm boot, DRAM contents from previous warm boot will not get decrypted. This creates issue in accessing CBMEM region from previous warm boot. To mitigate the issue coreboot also programs exclusion range. Intel TME does not encrypt physical memory range set in exclusion range. Current coreboot implementation programs TME to exclude CBMEM region. When this config option is enabled, coreboot instructs Intel FSP to program TME to generate a new key on every warm boot and also exclude CBMEM region from being encrypted by TME. BUG=b:276120526 TEST=Able to build rex. Change-Id: I19d9504229adb1abff2ef394c4ca113c335099c2 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76879 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03soc/intel/alderlake/meminit.c: Guard CsPiStartHighinEct properlyMichał Żygowski
Build issue introduced by patch CB:76418 (commit hash 01025d3ae78e02192d389f22abd36747e3d8c63b) for Google boards. Patch has not been rebased to latest master and tested before submission causing the Jenkins jobs to fail. Change-Id: I95bd2485b98be4ab3a39eaaebb9efb34db93bbe8 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76915 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03src/soc/intel/alderlake: add SOC_INTEL_RAPTORLAKE_PCH_S symbolMichał Żygowski
Introduce new symbol SOC_INTEL_RAPTORLAKE_PCH_S that can be selected by board with RPL-S PCH. For now only the IoT variant of RPL-S FSP is available for use with 700 series chipsets. Boards with 600 series chipsets can still use RPL CPUs with the ADL-S C.0.75.10, which contains minimal RPL-S CPU support. Change-Id: I303fac78dac1ed7ccc9d531a6c3c10262f7273ee Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-15 13:34:49 +0000