diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-08-03 16:02:40 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-08-08 19:44:11 +0000 |
| commit | 1b02483ab6e152c9987b384849f42d21eb5c4d92 (patch) | |
| tree | 34fb4a6ed1ac043611c1d9f4fb50e7be1725febb /src/soc | |
| parent | 3f3f93bf0668acc88bf6e06c20a87f3bef2d6be9 (diff) | |
soc/amd/picasso/include/data_fabric: add data fabric IO decode registers
PPR #55570 Rev 3.18 was used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I61d4fca48d71010bbc4bd94a2fb8889bad08f1cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/picasso/include/soc/data_fabric.h | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/include/soc/data_fabric.h b/src/soc/amd/picasso/include/soc/data_fabric.h index 1e0b28a3a3..f63b027dec 100644 --- a/src/soc/amd/picasso/include/soc/data_fabric.h +++ b/src/soc/amd/picasso/include/soc/data_fabric.h @@ -11,6 +11,40 @@ #define D18F0_VGAEN DF_REG_ID(0, 0x80) #define VGA_ADDR_ENABLE BIT(0) +#define DF_IO_BASE0 DF_REG_ID(0, 0xc0) +#define DF_IO_LIMIT0 DF_REG_ID(0, 0xc4) + +#define DF_IO_REG_COUNT 8 + +#define DF_IO_REG_OFFSET(instance) ((instance) * 2 * sizeof(uint32_t)) +#define DF_IO_BASE(reg) (DF_IO_BASE0 + DF_IO_REG_OFFSET(reg)) +#define DF_IO_LIMIT(reg) (DF_IO_LIMIT0 + DF_IO_REG_OFFSET(reg)) + +union df_io_base { + struct { + uint32_t re : 1; /* [ 0.. 0] */ + uint32_t we : 1; /* [ 1.. 1] */ + uint32_t : 3; /* [ 2.. 4] */ + uint32_t ie : 1; /* [ 5.. 5] */ + uint32_t : 6; /* [ 6..11] */ + uint32_t io_base : 13; /* [12..24] */ + uint32_t : 7; /* [25..31] */ + }; + uint32_t raw; +}; + +union df_io_limit { + struct { + uint32_t dst_fabric_id : 8; /* [ 0.. 7] */ + uint32_t : 4; /* [ 8..11] */ + uint32_t io_limit : 13; /* [12..24] */ + uint32_t : 7; /* [25..31] */ + }; + uint32_t raw; +}; + +#define DF_IO_ADDR_SHIFT 12 + #define DF_DRAM_HOLE_CTL DF_REG_ID(0, 0x104) #define DRAM_HOLE_CTL_VALID BIT(0) #define DRAM_HOLE_CTL_BASE_SHFT 24 |