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authorTim Crawford <tcrawford@system76.com>2023-08-11 13:21:04 -0600
committerMartin L Roth <gaumless@gmail.com>2023-08-21 23:10:38 +0000
commita129f8f2fe41dcb1ffbedb062818c2f1664dea1f (patch)
tree21a163873010424b7eb688ad87781fe998335ba5 /src/soc
parent3ee08719ca2651dba1049be5f14eeb656a062575 (diff)
soc/intel/alderlake: add GPIO definitions for RPL PCH
The RPL PCH uses a different ACPI Device ID than ADL PCH. Ref: Intel 700 Series Chipset Family PCH Datasheet, Volume 1 (#743835) Change-Id: I03f47a43ff985213ad617e834db7f974f687d877 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/alderlake/include/soc/gpio.h6
1 files changed, 5 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/include/soc/gpio.h b/src/soc/intel/alderlake/include/soc/gpio.h
index 14338e9024..1cea6cc766 100644
--- a/src/soc/intel/alderlake/include/soc/gpio.h
+++ b/src/soc/intel/alderlake/include/soc/gpio.h
@@ -3,7 +3,11 @@
#ifndef _SOC_ALDERLAKE_GPIO_H_
#define _SOC_ALDERLAKE_GPIO_H_
-#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
+#if CONFIG(SOC_INTEL_RAPTORLAKE) && CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
+#include <soc/gpio_defs_pch_s.h>
+#define CROS_GPIO_NAME "INTC1085"
+#define CROS_GPIO_DEVICE_NAME "INTC1085:00"
+#elif CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
#include <soc/gpio_defs_pch_s.h>
#define CROS_GPIO_NAME "INTC1056"
#define CROS_GPIO_DEVICE_NAME "INTC1056:00"