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2022-02-15soc/intel/apollolake: Add function to clear PMCON status bitsSubrata Banik
This patch adds an SoC function to clear GEN_PMCON_A status bits to align with other IA coreboot implementations. BUG=b:211954778 TEST=None. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I982f669b13f25d1d0e6dfaec2fbf50d3200f74fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/61651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-02-15soc/intel/skylake: Add function to clear PMCON status bitsSubrata Banik
This patch adds an SoC function to clear GEN_PMCON_A status bits to align with other IA coreboot implementations. Additionally, move the PMCON status bit clear operation to finalize.c to cover any such chances where FSP-S NotifyPhase requested a global reset and PMCON status bit remains set. BUG=b:211954778 TEST=None. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie786e6ba2daf88accb5d70be33de0abe593f8c53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-02-15soc/intel/elkhartlake: Fix PCR ID for eSPIWerner Zeh
According to the Datasheet Volume 1 (doc #636112, [1]) the PCR port ID for eSPI is 0x72 (see chapter 25.2.2). Fix it in the header file. [1]: https://cdrdv2.intel.com/v1/dl/getContent/636112?explicitVersion=true Test=Read and modify PCR registers of eSPI controller. Change-Id: I5b07ef0f3a285f981791b1f4b4cdbda98ccf05ad Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61841 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-15soc/intel/common/block/pcie/rtd3: Fix bit checksAngel Pons
Fix always-true conditions to properly test whether a bit is set. Change-Id: Ibfeafe222c0c2b39ced5b77f79ceb0c679a471b5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-15Revert "soc/intel/adl: Skip sending MBP HOB to save boot time"MAULIK V VAGHELA
This reverts commit 9a7fbbc98e8610a0a5314470edd8d5dafe676a06. SkipMbpHob UPD skips generation of MBP Hob within FSP. Skipping MBP Hob generation also skips syncing correct version of chipset data with CSE since FSP uses version information from MBP HOB. In absence of MBP Hob, FSP is unable to get version information and hence chipset data sync is skipped. This creates an issue while platform tries to enter deeper sleep states. BUG=b:215448362 BRANCH=None TEST= FSP can get version information from MBP HOB and chipset sync is performed. It has been Verified using FSP debug logs on Brya board. Change-Id: I9a160fee72b61ae9eecababf9a16900e6bd4acff Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-15soc/apollolake: Make IO decode / enable register configurableSean Rhodes
This allows the one 32bit register to be configured in the devicetree in the same way that Skylake can be. i.e. register "lpc_ioe". Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I598baca0f31b5350a4e6fdb7b7356fa6fb2d71ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/61195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-15soc/intel/cnl: Enable CSE FW sync for CSE LITE SKUMatt DeVillier
Boards based on google/puff baseboard (hatch variant) use CSE LITE, which utilizes RO and RW firmware. If the CSE does not switch to the RW firmware, the HECI1 interface is disabled, and dependent drivers (like SOF audio firmware) fail to load. Use the same logic as other platforms utilizing CSE LITE (eg, TGL/JSL) to check if an ME RW firmware update is available, and if not jump to the onboard RW firmware. Test: built/boot Manjaro 21.x on google/wyvern, verify CSE RW firmware loaded via cbmem console, HECI1 interface is present vis lspci, and the SOF DSP firmware is correctly loaded via dmesg. Change-Id: I0ae21adde4a64bbcc5fa4fb144436a0430e92280 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-15soc/amd/sabrina: Select ACP gen2Fred Reitberger
Select ACP gen2 for Sabrina Change-Id: I107ebd390732b597629a3236d0e7d1f5e2c51379 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-15soc/amd/common/acp: add acp_gen2Fred Reitberger
The gen2 ACP register definitions and locations are different from previous models. Specific code is refactored into acp_gen1 and acp_gen2. Update ACP register locations and definitions for gen2. Change-Id: If665b93cddf22435512f1276fcfee2f497dc6ef5 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-14soc/intel/graphics: Repurpose graphics_get_memory_base()Ethan Tsao
create SOC_INTEL_GFX_MEMBASE_OFFSET for platform to map graphic memory base if required, because it may vary by platfrom. BUG=b:216756721 TEST= Check default offset for existing platform and update platform specific offset in Kconfig under SoC directory. Change-Id: I6b1e34ada9b895dabcdc8116d2470e8831ed0a9e Signed-off-by: Ethan Tsao <ethan.tsao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61389 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-13soc/amd/common/include/ioapic: make IOAPIC IDs not depend on MAX_CPUSFelix Held
Since the APIC bus isn't used since a long time and the IOAPIC and LAPIC talk to each other via the system bus, there is no longer the requirement that the IOAPIC IDs mustn't overlap with the LAPIC IDs that start at 0 and end at CONFIG_MAX_CPUS - 1. The current Intel code uses 2 as the IOAPIC ID while most of their CPUs have more than 2 logical cores resulting in the IOAPIC having the same ID as one of the LAPICs. All chipsets in soc/amd use the defines for FCH_IOAPIC_ID and GNB_IOAPIC_ID for initializing the IOAPIC register, writing both MADT and IVRS ACPI tables and there's no MPTable support for those SoCs that might also rely on those IDs being consistent. This patch changes the definitions for FCH_IOAPIC_ID and GNB_IOAPIC_ID from CONFIG_MAX_CPUS and CONFIG_MAX_CPUS + 1 to 0 and 1. This also makes sure that the IOAPIC IDs still fit in 4 bits despite Cezanne having a CONFIG_MAX_CPUS of 16 resulting in the IOAPIC IDs being larger than 4 bits with the old code. While the Cezanne FCH IOAPIC supports 8 bits of IOAPIC IDs, this is non-standard. TEST=AMD Mandolin and Google Liara still work. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: Id3a356480bb8407e0347cb5cef691fde7edc8deb Reviewed-on: https://review.coreboot.org/c/coreboot/+/55430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-02-12soc/intel/apl: Use Kconfig to enable CseRbpSean Rhodes
This patch makes SKIP_CSE_RBP=y default for Apollo Lake if Boot Device is memory mapped and ensures SkipCseRbp UPD is guarded against this config. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ifd01a25443e2582a90529e55be8d34a88342a103 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-12soc/amd/cezanne/psp_verstage/uart: Fix off by 1 errorRaul E Rangel
FCH_UART_ID_MAX == 2, and there are 2 UARTS, so we don't need the -1. BUG=b:215599230 TEST=Build guybrush Found-by: Coverity CID 1469611 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5f0171ed2d3da7f86ba3cfd0457f60d2d5722625 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61869 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-12soc/amd/cezanne: Allow to specify SPL table path in KconfigZheng Bao
BUG=b:216096562 Change-Id: I4a5ee335ea8808b595dc65ebafd15baedfbdd06e Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-12soc/amd/common: Scan bridge devices behind SoCs GPU ControllerKevin Chiu
Scan devices behind SoCs GPU controller to expose more buses. BUG=b:204401306 BRANCH=guybrush TEST=emerge-guybrush coreboot Change-Id: Ib78e6570f101c71efaf9cc1843defcb05301cd30 Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-12soc/mediatek: Fix printing SPM versionYu-Ping Wu
Currently the SPM version string is stored at the end of the blob, possibly without a trailing '\0'. Therefore, we should be careful not to print characters beyond the blob size. BUG=b:211944565 TEST=emerge-corsola coreboot TEST=SPM version looked good in AP console BRANCH=asurada,cherry Change-Id: Icfeb686539dc20cf5b78de77c27bdbb137b5d624 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-02-11soc/intel/common: Re-use Alder Lake-M device IDs for Alder Lake-NUsha P
Few of the Alder Lake-N Device IDs according to EDS, are named as ADL_M IDs in the current code. Hence rename those device IDs as ADL_M_N and use them for Alder Lake-N platform. Document Number: 619501, 645548 Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I6042017c6189cbc3ca9dce0e50acfb68ea4003f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-11soc/amd/common/acp: introduce acp_gen1Fred Reitberger
Refactor existing acp code into acp_gen1 variant as preparation for gen2 variant in sabrina. Change-Id: Id9248584237196b5404b79d3a8552cb90fe4491e Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-11soc/amd/common/fsp: check fsp image revisionJulian Schroeder
Check if FSP binary and coreboot FSP structures (fspmupd.h) match sufficiently. A change in minor number denotes less critical changes or additions to the FSP API that still allow for the boot process to proceed. A change of the AMD image revision major number will halt boot. The Fspmupd.h header now defines IMAGE_REVISION_ macros for AMD Picasso, Cezanne and Sabrina APUs. BUG=b:184650244 TEST=build, boot and check fsp image revision info. Example: FSP major = 1 FSP minor = 0 FSP revision = 5 FSP build = 0 Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com> Change-Id: I0fbf9413b0cf3e6093ee9c61ff692ff78ebefebc Reviewed-on: https://review.coreboot.org/c/coreboot/+/61281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-11soc/amd/cezanne,picasso,sabrina: Fix incorrect values of CBFS amdfw position ↵Robert Zieba
makefile variables Currently apu/amdfw_a-position and apu/amdfw_b-position currently depend on CEZANNE_FW_A_POSITION and CEZANNE_FW_B_POSITION. This causes error messages from awk as these variables are sourced from fmap_config.h and these variables are expanded before fmap_config.h is built. However these variables should not be set to CEZANNE_FW_*_POSITION. These files end up in the FW_MAIN_* fmap regions. These regions are placed at the proper locations through the chromeos.fmd file. The apu/amdfw_*-position variables are the positions within these regions where the files end up. These variables should be set to 0x40 to coincide with the beginning of the FW_MAIN_* regions, accounting for the size of struct cbfs_file + filename + metadata, aligned to 64 bytes. Currently they end up in the correct locations only because fmap_config.h does not exist when the apu/amdfw_*-position variables are expanded. This change explicity sets the value of these variables to 0x40, removing the errors from awk and ensuring that these files end up in the correct location in the resulting image. These changes are also applied to the Picasso and Sabrina makefiles as well. BUG=b:198322933 TEST=Verified that the apu/amdfw_* files end up in the correct locations as reported by cbfstool during the build, did timeless builds and confirmed that coreboot.rom images were identical, tested AP firmware on guybrush and zork devices Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: If1c2b61c5be0bcab52e19349dacbcc391e8aa909 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-02-11soc/amd/common/block/lpc/espi_util: add decode range register helpersFelix Held
Introduce and use functions to translate eSPI IO/MMIO decode range IDs into the corresponding register bits and the IO/MMIO range and size register IDs into register offsets. This is a preparation to support the additional eSPI decode ranges on Sabrina where not all enable bits and base/size registers for one type of decode ranges are consecutive. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id91fe32447a06b049e33dfdacc8edfa2ebb2df39 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-11soc/amd/common/block/include/espi: rename IO/MMIO base/size registersFelix Held
This aligns the register names more with the PPR. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4e7dc8dfc0fa5e86b9d4425f2496be86e039b686 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-11src/soc/intel/common/block/i2c: Use early BAR in ENV_PAYLOAD_LOADERTim Wawrzynczak
There may be occasions where an I2C device was initialized during "early initialization," but when used again in ENV_PAYLOAD_LOADER before resource allocation happens, it would currently return that it has not been assigned a BAR. However, because of the early BAR assigned to it, it should still be valid to use that until proper resources have been assigned, therefore return any BAR that may have been assigned to the device during early initialization. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I8ab599199592a72ae96cd9f95accfaa0d84e66b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-11soc/mediatek/mt8186: Lower SPI NOR speed to 52MHizYu-Ping Wu
The current SPI NOR speed mainpll_d7_d2 (78MHz) is too fast for MT8186's HW design, which is capable of up to 52MHz. Therefore, lower the speed to univpll_d3_d8 (52MHz). BUG=b:218775654 TEST=emerge-corsola coreboot TEST=Boot time didn't increase significantly BRAHCH=none Change-Id: I5a03e41d4ce47d45b97a805b9b98877ef0dac7b7 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-02-11soc/mediatek: Only update required bits when triggering WDT resetRex-BC Chen
To prevent to modify original value of wdt_mode, we use setbits32 to update required bits. BUG=b:218420108 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I743c1af3583c18ec8500fc1eb89f31cdbce5317c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61729 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-10soc/intel/common: Add Crash Log and PMC SRAM PCI device IDsTim Wawrzynczak
Add Alder Lake and Tiger Lake specific Crash Log and PMC SRAM device IDs. Document Number: 619501, 645548 Change-Id: I64b58b8c345bd54774c4dab7b65258714cd8dc9e Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-02-10soc/mediatek/mt8173/dramc_pi_calibration_api.c: Remove duplicated "ERROR" in ↵Elyes HAOUAS
log message Change-Id: I846c21bd690372ec416fb3d3b3954bf181b0204c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61637 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-09vendorcode/intel/fsp: Add FSP header file for Alder Lake N FSP v2503_00Ronak Kanabar
The headers added are generated as per Alder Lake N FSP v2503_00. Changes include: - Add all header files for Alder Lake N FSP. - List of header files: FirmwareVersionInfoHob.h, FspmUpd.h, FspsUpd.h, FspUpd.h, MemInfoHob.h - Select FSP_HEADER_PATH BUG=b:213828776 BRANCH=None Change-Id: I97afa6d47cc825703a8dc82216250bfc5e09dc9b Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-09soc/intel/common/gpio: Add PAD_NC_LOCK and PAD_CFG_GPI_SCI_LOCK macroEric Lai
Add PAD_NC_LOCK and PAD_CFG_GPI_SCI_LOCK macro to support mainboard to lock NC and GPI_SCI pins as applicable. BUG=b:216583542 TEST=build passed Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ie44d72f4152b55183d900228df3e3670358f7518 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61655 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-09soc/amd/common/block/psp: introduce AMD_SOC_SEPARATE_EFS_SECTIONFred Reitberger
On systems that use the first 128kByte of the SPI flash for the EC firmware, it is not possible to place the EFS/amdfw part at the lowest location in flash where the on-chip PSP firmware will look for the EFS, since this is at an offset of 128kByte into the flash which is where the cbfs master header resides when the main CBFS is placed right after the EC firmware. This patch introduces the AMD_SOC_SEPARATE_EFS_SECTION option that allows putting the EFS in a separate FMAP section that can be located right after the EC firmware FMAP section. The EFS FMAP partition is checked to ensure it begins at the expected location. Change-Id: I5ed0f76c9c9c9c180ee5f1b96f88689d0979bb5e Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-09soc/intel/alderlake: Define USB2_PORT_MAX_TYPE_C macroSridhar Siricilla
The patch defines USB2_PORT_MAX_TYPE_C macro to allow mark the type_c flag.The USB2_PORT_MAX_TYPE_C macro modifies the USB2 configuration to indicate the port mapped to Type-C and sets Max TX and Pre-emp settings. This is an extension to existing macro USB2_PORT_MAX. The change is required to enable port reset event on a USB2 port. This event is passed to USB3 upstream ports to upgrade back to super speed (USB3) after a downgrade during low power state. BUG=b:193287279 TEST=Build the code for Gimble board Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I464f139d8e367907191c04f9170ac53d327776ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/61623 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-09soc/intel/common/cse: Add function to perform global reset lockSubrata Banik
This patch implements `cse_control_global_reset_lock()` as per ME BWG (doc: 627331) recommendation. It is recommended that BIOS should set this bit early on in the boot sequence, and then clear it and set the CF9LOCK bit prior to loading the OS in both an Intel CSME Enabled and a Intel CSME Disabled system. Note: For CSE-Lite SKUs BIOS should set CF9LOCK bit unconditionally. BUG=b:211954778 TEST=Able to build and boot Brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3894b2cd8b90dc033f475384486815ab2fadf381 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-02-09soc/mediatek/mt8186: Fix issue of clearing watchdog statusRex-BC Chen
The implementation of clearing watchdog status is wrong in CB:58835. The value written to the 'wdt_mode' register should be 'wdt_mode | 0x22000000' instead of 'wdt_status | 0x22000000'. BUG=b:204229208 TEST=check watchdog status is cleared. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I8c5dbaab2ac43d3867037bc4160aa5af2d79284f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-02-09soc/mediatek/mt8186: Support DRAM fast calibration using blobXi Chen
For most MediaTek SoCs (MT8183, MT8192, MT8195) we rely on an external program (e.g., the "DRAM blob") to do the full DRAM calibration first, then store and and apply the generated parameters to the reference "fast DRAM calibration" in the vendor/mediatek folder for normal system boot. Starting with MT8186 the implementation of fast calibration may need to be changed, and a "DRAM blob" only path is introduced for devices that have to do both full and fast calibration using the external blob. TEST=fast calibration pass on kingler/krabby BUG=b:204226005 Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: If25a7dd6aa6261ecff79a1b4df8b1f2e53d896dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/61133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-02-08soc/amd/sabrina/Kconfig: remove SOC_AMD_COMMON_BLOCK_PCI_MMCONF TODOFelix Held
Sabrina uses the same MMIO_CONF_BASE MSR as the previous AMD CPUs to configure the PCI MMCONF base address. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7e3064bab5ca1e277b04f9aae98f9adabce75399 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-08soc/intel/quark/storage_test.c: Remove duplicated "ERROR" in log messageElyes HAOUAS
Change-Id: I7697512a63b58ca7d7200c74a409822389db0762 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-08soc/amd/cezanne: Disable CONSOLE_CBMEM_PRINT_PRE_BOOTBLOCK_CONTENTSRaul E Rangel
Now that PSP verstage can directly write to the UART, we no longer need to manually dump the cbmem contents. Ideally if we can get picasso to add support for mapping the UART, or if we implement bit banging we can delete this functionality completely. BUG=b:215599230 TEST=Boot guybrush and verify verstage logs aren't printed twice Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Id70b24625c3b2f3d6fe470cf227a0083f5b974f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-08soc/amd/common/psp_verstage: Add UART support to PSP consoleRaul E Rangel
This will allow PSP verstage to write logs to the serial console. We are no longer dependent on using a serial enabled PSP boot loader. Ideally we would delete this psp printk and use the standard printk. Since picasso doesn't currently support mapping the UART though, I'll keep it for now. BUG=b:215599230 TEST=Boot guybrush and verify PSP logs are output on serial console Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ibd77cc754fae5baccebe7adc5ae0790c79236d26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-08soc/amd/sabrina/psp_verstage: Implement get_uart_baseRaul E Rangel
The Sabrina PSP doesn't support mapping the UART, so add a dummy function to return NULL. BUG=b:215599230 TEST=None Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Idad8e4874e78bb96730feecb5a7b17334d12217c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-08soc/amd/picasso/psp_verstage: Implement get_uart_baseRaul E Rangel
The Picasso PSP doesn't support mapping the UART, so add a dummy function to return NULL. BUG=b:215599230 TEST=Build and boot morphius Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ie1f033ff86ebb0f755a9a0b6ff293aa3c8bbbeb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-08soc/amd/cezanne/psp_verstage: Implement get_uart_baseRaul E Rangel
This will allow directly using the UART console. On PSP releases that don't support mapping the UART, we will just return NULL which is perfectly acceptable. BUG=b:215599230 TEST=Boot guybrush and verify verstage can print to the console Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic8d7f0fe00794a715756f92e3fb32c6b512cb8aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/61607 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-07treewide: Remove "ERROR: "/"WARN: " prefixes from log messagesJulius Werner
Now that the console system itself will clearly differentiate loglevels, it is no longer necessary to explicitly add "ERROR: " in front of every BIOS_ERR message to help it stand out more (and allow automated tooling to grep for it). Removing all these extra .rodata characters should save us a nice little amount of binary size. This patch was created by running find src/ -type f -exec perl -0777 -pi -e 's/printk\(\s*BIOS_ERR,\s*"ERROR: /printk\(BIOS_ERR, "/gi' '{}' ';' and doing some cursory review/cleanup on the result. Then doing the same thing for BIOS_WARN with 's/printk\(\s*BIOS_WARNING,\s*"WARN(ING)?: /printk\(BIOS_WARNING, "/gi' Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I3d0573acb23d2df53db6813cb1a5fc31b5357db8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Lance Zhao Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-02-07soc/amd/cezanne: Add the fw SPL to fw.cfgZheng Bao
SPL: Security Patch Level The data in SPL is used for FW anti-rollback, preventing rollback of platform level firmware to older version that are deemed vulnerable from a security point of view. BUG=b:216096562 Change-Id: I0aa456b8b4eec506fbb319293f0903b293325cb0 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-07soc/intel/common/block/pcie/rtd3: Add optional _OFF and _ON skip controlCliff Huang
- Optional feature to provide mechanism to skip _OFF and _On execution. - It is used for the device to skip _OFF and _ON during device driver reload. - OFSK is used to skip _OFF Method at the end of device driver removal. - ONSK is used to skip _ON Method at the beginning of driver loading. - General flow use case: 1. Device driver is removed by 'rmmod' command. 2. Device _RST is called. _RST perform reset. 3. Device increments OFSK in _RST to skip the following _OFF invoked by OSPM. 4. OSPM invokes _OFF at the end of driver removal. 5. _OFF sees OFSK and skips current execution and decrements OFSK so that _OFF will be executed normally next time. 6. _OFF increments ONSK to skip the following _ON invoked by OSPM. 7. Device driver is reloaded by 'insmod/modprobe' command. 8. OSPM invokes _ON at the beginning of driver loading. 9. _ON sees ONSK and skip current execution and decrements ONSK so that _ON will be executed normally next time. - In normal case: When suspend, OSPM invokes _OFF. Since OFSK is zero, the device goes to deeper state as expected. When resume, OSPM invokes _ON. Sinc ONSK is zero, the device goes to active state as expected. - Generated changes: PowerResource (RTD3, 0x00, 0x0000) Name (ONSK, Zero) Name (OFSK, Zero) ... Method (_ON, 0, Serialized) // _ON_: Power On { If ((ONSK == Zero)) { ... } Else { ONSK-- } } Method (_OFF, 0, Serialized) // _OFF: Power Off { If ((OFSK == Zero)) { ... } Else { OFSK-- ONSK++ } } Test: Enable and verify OFSK and ONSK Name objects and the if-condition logic inside _OFF and _ON methods is added. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Ic32d151d65107bfc220258c383a575e40a496b6f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-07soc/intel/common/block/pcie/rtd3: Add PM methods to the device.Cliff Huang
Add L23 enter/exit, modPHY power gate, and source clock control methods. DL23: method for L2/L3 entry. L23D: method for L2/L3 exit. PSD0: method for modPHY power gate. SRCK: method for enabling/disable source clock. These optional methods are to be used in the device ACPI to construct flows with root port's power management functions. Test: Enable and verify DL23, L23D, PSD0, SRCK methods in ssdt. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I79de76f26c8424b036cb7d2719df68937599ca2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-07soc/intel/common: Define enum cpu_perf_eff_type type for core typesSridhar Siricilla
The patch defines enum values for small and big cores and uses them to indicate the big or small core. TEST=Verify the build for Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I740984a437da9d0518652f43180faf9b6ed4255e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2022-02-07soc/intel/apollolake: Convert to ASL 2.0Elyes HAOUAS
Change-Id: Ieb362b5be05421b6ad2b2a3126c2943b7d55d135 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-07soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_UARTFelix Held
Sabrina is compatible with the common AMD UART block and also with the DRIVERS_UART_8250MEM_32 driver it selects. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I432414c1d501ffbd1047b378996e06d281a9fb6f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-02-05soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_IOMMUFelix Held
Sabrina is compatible with the common AMD SOC_AMD_COMMON_BLOCK_IOMMU code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4c2e8553fde9467ca1b5e9085e36c33d138b7156 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-05nb,soc/amd/*/iommu: fix comment about IOMMU MMIO resourceFelix Held
This comment was added with the AMD family 15h Trinity IOMMU support in commit 88ebbeb7e2a914330c869147bacb190b4270532f and looks like a copy of the comment about the subtractive decode ranges in the LPC device. The IOMMU doesn't have any subtractively decoded I/O or MMIO ranges and this is also not what the code does. This resource is the MMIO region to configure the IOMMU instead, so fix the comment in all copies of the IOMMU support code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2e1e3a46b839b9e58b836932c1bc9b41b1b1dc02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-05soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_ACPIMMIOFelix Held
Sabrina is compatible with the common AMD ACPIMMIO function block mapping and access functions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I890375654a9cb1156e481c5586007ac81ab84120 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-05soc/amd/common/include/acpimmio: drop 16 and 32 bit PM2 access functionsFelix Held
The PM2 ACPIMMIO region should only be accessed with 8 bit accesses. Using 16 or 32 bit read accesses will return the data from the first byte for all 2 or 4 bytes and 16 or 32 bit write accesses will result in only the first byte being written which is both unexpected behavior. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5ace50d3b81b5bf3ea3b10aa02f25c58a6ea99b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-05soc/amd/common/block/acpimmio/print_reset_status: extend bit name tableFelix Held
Bit 23 in the PM_RST_STATUS register is called LtReset on Stoneyridge and ShutdownMsg on Picasso/Cezanne/Sabrina. Bit 30 is reserved on Stoneyridge and defined as SdpParityErr on the newer SoCs. Bit 31 is only defined for Sabrina. Since the default value of undefined bits is 0 it isn't a problem to have descriptions for reserved reset status bits on some SoCs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0782116d327fcad3817a10eb237ac6c8294846b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-05cpu/x86/lapic: Move LAPIC configuration to MP initKyösti Mälkki
Implementation for setup_lapic() did two things -- call enable_lapic() and virtual_wire_mode_init(). In PARALLEL_MP case enable_lapic() was redundant as it was already executed prior to initialize_cpu() call. For the !PARALLEL_MP case enable_lapic() is added to AP CPUs. Change-Id: I5caf94315776a499e9cf8f007251b61f51292dc5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-04soc/amd/sabrina/include/amd_pci_int_defs.h: remove PIRQ_SATAFelix Held
Sabrina has no SATA controller, so remove the corresponding PIRQ mapping. This was verified with PPR #57243 Rev 1.53. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I98ffa3675c361e8a74c50ebfc37e79ae63dacc85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-04soc/amd/sabrina/Kconfig: remove SOC_AMD_COMMON_BLOCK_DATA_FABRIC TODOFelix Held
The common AMD data fabric register access code is valid for Sabrina. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I97fb2c6006c09297584845a83342e75058d35713 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-04soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_SMUFelix Held
The common AMD SMU code and the common AMD SMN access code that gets selected by the common SMU code are valid for Sabrina. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic220dbb2f73b89554ac7e7b7e6dc7525ae8e9faa Reviewed-on: https://review.coreboot.org/c/coreboot/+/61599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-04soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_AOACFelix Held
The common AMD FCH AOAC bit definitions and helper functions are correct for Sabrina. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie791cca0dc760e53e0f5c69c63ac78270ba6ad4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-04soc/intel/alderlake: Enable USB2 port reset message on Type-C portsAnil Kumar
This change is added to address the issue of USB3 ports downgrading to high speed during low power modes and not returning back to super speed. The patch enables port reset event on USB2 ports. This event is is passed to USB3 upstream ports to upgrade back to super speed (USB3) after a downgrade during low power state BUG=b:193287279 TEST=Built coreboot on Gimble and tested type A pen drive detects as super speed device Change-Id: Iabc6f308992bf3868da66f152c6d7b0164e64bea Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-04soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_I2CFelix Held
Sabrina uses an identical I2C controller as Picasso and Cezanne. Also both the type and version read-only register of the I2C controller contain identical values. The dma_cr, dma_tdlr, dma_rdlr and clr_restart_det registers that are defined in the dw_i2c_regs struct in the common Designware I2C code aren't defined in the PPRs of Picasso, Cezanne and Sabrina, but since common DW I2C code doesn't access those, this is no problem. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I90732aa98518010686f73f80bee229b13e9bc89c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-04soc/amd/common/block/i2c/i23c_pad_ctr: add & use I23C pad configurationFelix Held
I2C bus 0..2 on Sabrina uses a different pad type which supports 1.1V and 1.8V levels, but doesn't support 3.3V I2C levels. Compared to the existing I2C pad control registers the bit definitions are different, so add a separate function to configure those pads which however still has the same function signature and is compatible with same data structs used for the devicetree settings. PPR #57243 Rev 1.50 was used as a reference. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie210c3437f2608d1e9fb99dcb151fc4190721375 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-04soc/intel/alderlake: Remove `soc_gpio_lock_config()` override functionSubrata Banik
This patch removes `gpios_to_lock` lists and `soc_gpio_lock_config` override function from Alder Lake SoC as the required config (SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS) to perform GPIO PAD lock configuration using SMM is not enabled. Note: The current assumption is that the responsibility of locking the sensitive GPIOs (from getting reprogrammed by OS or other SW) remains with the mainboard. BUG=b:208827718 TEST=Able to build and boot brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I2e22e8453b0ec7d34c0f7cb4c17e3336286581c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-04soc/intel/common: Remove GPIO PAD lock config override from mainboardSubrata Banik
This patch removes mainboard capability to override GPIO PAD lock configuration using `mb_gpio_lock_config` override function as the variant GPIO pad configuration table is now capable of locking GPIO PADs. BUG=b:208827718 TEST=Able to build and boot brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6769f51afaf79b007d4f199bccc532d6b1c4d435 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-04soc/intel/{adl, common}: Add routines into CSE IA-common codeSubrata Banik
This patch adds routines to keep CSE and other HECI devices into the lower power device state (AKA D0I3). - cse_set_to_d0i3 => Set CSE device state to D0I3 - heci_set_to_d0i3 => Function sets D0I3 for all HECI devices Additionally, creates a config `MAX_HECI_DEVICES` to pass the HECI device count info from SoC layer to common CSE block. As per PCH EDS, the HECI device count for various SoCs are: ADL/CNL/EHL/ICL/JSL/TGL => 6 (CSE, IDE-R, KT, CSE2, CSE3 and CSE4) APL => 1 (CSE) SKL/Xeon_SP => 5 (CSE, IDE-R, KT, CSE2 and CSE3) BUG=b:211954778 TEST=Able to build and boot Brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie32887196628fe6386896604e50338f4bc0bedfe Reviewed-on: https://review.coreboot.org/c/coreboot/+/61518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-03soc/amd/*/i2c: factor out common I2C pad configurationFelix Held
The I2C pad control registers of Picasso and Cezanne are identical and the one of Sabrina is a superset of it, so factor out the functionality. To avoid having devicetree settings that contain raw register bits, the i2c_pad_control struct is introduced and used. The old Picasso code for this had the RX level hard-coded for 3.3V I2C interfaces, so keep it this way in this patch but add a TODO for future improvements. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1d70329644b68be3c4a1602f748e09db20cf6de1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-03soc/amd/*/i2c: introduce and use MISC_I2C_PAD_CTRL(bus) macroFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9d098a55a5c6f6e022c3896750c752e2759e101b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-03soc/amd/*/i2c: drop unused mainboard_i2c_overrideFelix Held
No mainboard in the current tree implements mainboard_i2c_override. In a follow-up commit the i2c_pad_control struct is introduced to be able to make more parameters controllable by devicetree settings in the future. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8f9ed5d50d26e4623dc5888cc8af090fdd00fc03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61566 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-03soc/intel/apollolake: Rename PWRMBASE macro and functionSubrata Banik
This patch ensures PWRMBASE macro name and function to get PWRMBASE address on APL SoC is aligned with other IA SoC. PMC_BAR0 -> PCH_PWRM_BASE_ADDRESS read_pmc_mmio_bar() -> pmc_mmio_regs() Additionally, make `pmc_mmio_regs` a public function for other IA common code may need to get access to this function. BUG=None TEST=None Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3a61117f34b60ed6eeb9bda3ad853f0ffe6390f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-03soc/intel/cannonlake: Forbid FSP from disabling HECI1Subrata Banik
The functionality of disabling HECI1 device has been moved from the FSP to coreboot (using `DISABLE_HECI1_AT_PRE_BOOT` config), hence, always set the `Heci1Disabled` UPD to `0`. BUG=none TEST=Boot to OS, verify HECI1 is disabled on hatch system using coreboot when mainboard selects DISABLE_HECI1_AT_PRE_BOOT config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia8908c080ca9991e7a71e795ccb8fc76d99514f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-02-02soc/amd/cezanne: Rename PSP_POSTCODES_ON_ESPI to PSP_INIT_ESPIRaul E Rangel
This flag only controls eSPI init in the PSP Stage 2 Boot Loader. It doesn't control if port 80s are written. This flag also doesn't currently control LPC init. The PSP is currently hard coded to remove any LPC init. BUG=b:215425753 TEST=build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Idf3f0dcc216df2fd15b016f9458a208b7e15c720 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61534 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-02soc/amd/cezanne,vc/cezanne: Implement svc_write_postcodeRaul E Rangel
This will allow verstage to write post codes. BUG=b:215425753 TEST=Boot guybrush and verify PSP post codes are printed 22-01-31 15:12:03.214 (S3->S0) 22-01-31 15:12:03.214 03 04 0f 0e f0 f1 f2 01 10 a0 a2 <--new Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I6ceee8fcb094f462de99c07aef8e96425d9c3270 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61522 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-02soc/intel/cannonlake: Add `disable_vmx` devtree optionAngel Pons
This option isn't meant to be assigned statically through devicetrees, but at runtime according to some config mechanism. It works in conjunction with the existing Kconfig option. Change-Id: Ia760be61466bc6a0ec187746e6e32537029512b4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
2022-02-02soc/intel/alderlake: Use PMC IPC to disable HECI1Subrata Banik
This patch allows common CSE block to disable HECI1 device using PMC IPC command `0xA9`. Select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC config for Alder Lake to disable HECI1 device using PMC IPC. Additionally, remove dead code that deals with HECI1 disabling using in SMM as HECI1 disabling using PMC IPC is simpler solution. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I11a677173fd6fb38f7c09594a653aeea0df1332c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-02-02soc/intel/tigerlake: Use PMC IPC to disable HECI1Subrata Banik
This patch allows common CSE block to disable HECI1 device using PMC IPC command `0xA9`. Select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC config for Tiger Lake to disable HECI1 device using PMC IPC. Additionally, remove dead code that deals with HECI1 disabling using in SMM as HECI1 disabling using PMC IPC is simpler solution. BUG=none TEST=None Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Id5f1e3f622f65cd0f892c0dc541625bfd50d038e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-02soc/intel/jasperlake: Use SBI msg to disable HECI1Subrata Banik
Select HECI_DISABLE_USING_SMM config for Jasper Lake to disable HECI1 device using the SBI msg in SMM. BUG=none TEST=None Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3e8568750ec941fc8b8e7407bad027f7175953c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-02soc/intel/cannonlake: Use SBI msg to disable HECI1Subrata Banik
Select HECI_DISABLE_USING_SMM config for Cannon Lake to disable HECI1 device using the SBI msg in SMM. BUG=none TEST=None Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6882b619506d1bf4131f68c2c9a32ef4f7d6f6d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-02soc/intel/apollolake: Use PCR write to disable HECI1Subrata Banik
Set the SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR config for Apollo Lake to disable HECI1 device using PCR writes. BUG=none TEST=None Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8df9544296f0bea095c5415805a596cb5b36885e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-02-02soc/intel/skylake: Use PCR write to disable HECI1Subrata Banik
Set the SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR config for Skylake to disable HECI1 device using PCR writes. BUG=none TEST=None Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib6bfa7c48660a6df8d0944de675a4f30fe248d1b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-02-02soc/intel/elkhartlake: Use SBI msg to disable HECI1Subrata Banik
Select HECI_DISABLE_USING_SMM config for Elkhart Lake to disable HECI1 device using the SBI msg in SMM. BUG=none TEST=None Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4ef7ff7aa234ce411092d70bcb2c9141609be90e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-02-02soc/intel/common/cse: Rework heci_disable functionSubrata Banik
This patch provides the possible options for SoC users to choose the applicable interface to make HECI1 function disable at pre-boot. `SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_SBI` config is used for disabling heci1 using non-posted sideband write (inside SMM) after FSP-S sets the postboot_sai attribute. Applicable from CNL PCH onwards. `SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PMC_IPC` config is used for disabling heci1 using PMC IPC command `0xA9`. Applicable from TGL PCH onwards. `SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PCR` config is used for disabling heci1 using private configuration register (PCR) write. Applicable for SoC platform prior to CNL PCH. Additionally, add PID_CSME0 macro for SKL, Xeon_SP and APL to fix the compilation failure. Finally, rename heci_disable() function to heci1_disable() to make it more meaningful. BUG=none TEST=Able to build and boot brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7e0bab0004013b999ec1e054310763427d7b9348 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-02-02soc/intel/common/cse: Make cse_disable_mei_devices a public functionSubrata Banik
This patch export cse_disable_mei_devices() function instead of marking it static. Other IA common code may need to get access to this function for making `heci1` device disable. BUG=none TEST=Able to build and boot brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib2a1eb2fdc9d4724bd287b82be4238893c967046 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-02-01psp_verstage: report developer mode to PSPKangheui Won
Add platform_report_mode function which report current developer mode status to the PSP. L1 widevine app in the PSP will use this information to select key box. BUG=b:211058864 TEST=build and boot guybrush TEST=build picasso chrome os boards Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I04b5fcfa338b485b36f1b946203f32823385c0b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-01psp_verstage: add new svc for cezanneKangheui Won
Add svc_set_platform_bootmode svc to cezanne. PSP will use this information to select proper widevine keybox. BUG=b:211058864 TEST=build guybrush Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I6bcc9e49a2b73d486cfecd7b240bf989cad94630 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-01soc/samsung/exynos5420: Remove unuseful 'return' in void functionElyes HAOUAS
Change-Id: I6c093e8326733a079ab3c41dfd2c77fe1883a9d4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2022-02-01soc/nvidia/tegra124/sor.c: Remove unuseful 'return' in void functionElyes HAOUAS
Change-Id: I8539eb9028f3141dfbeb926a1e19e3ad94be3edf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2022-02-01soc/nvidia/tegra210/sor.c: Remove unuseful 'return' in void functionElyes HAOUAS
Change-Id: Ifaaf8a240436758a83216037994493255935f158 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2022-02-01soc/rockchip/rk3399/display.c: Remove unuseful 'return' in void functionElyes HAOUAS
Change-Id: I8b5537bb6d0cb934aadb0eba8ba4f51dd53026c2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2022-02-01soc/qualcomm/ipq40xx/spi.c: Remove unuseful 'return' in void functionElyes HAOUAS
Change-Id: I0ca7cbbf6c4884b58b4ec8a8e3cbc77f118a42f2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2022-02-01soc/intel/xeon_sp/acpi.c: Remove unuseful 'return' in void functionElyes HAOUAS
Change-Id: Ib964939468ebb8cd0a537d514060ee5b8b13e320 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2022-02-01soc/samsung/exynos5250: Add missing 'void' in function definitionElyes HAOUAS
Change-Id: I59203253ba9e66e4db3ff5dcae347b68d1203f21 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2022-02-01drivers/i2c/designware/dw_i2c: return enum cb_err from dw_i2c_initFelix Held
Using enum cb_err as return type instead of int improves the readability of the code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I55e6d93ca141b687871ceaa763bbbbe966c4b4a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-02-01soc/intel/common: Add the Primary to Sideband bridge libraryJohn Zhao
New platforms have additional Primary to Sideband bridge besides the PCH P2SB. This change puts the common functions into the P2SB library. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I63f58584e8c3bfe42cdd81912e1e5140337c2d55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-01soc/intel/appololake: Allow to configure SATA ALPM via devicetreeMario Scheithauer
Add a devicetree option to disable SATA Aggressive Link Power Management. ALPM is a method of saving power. The corresponding FSP-S UPD parameter is enabled by default. It may be that this feature is unwanted, for example for a real-time system. Therefore, allow to disable ALPM using the devicetree. Change-Id: Ica8920a87ebebe83f5d8cb4d6c8c0a6105e183e4 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-02-01soc/intel/alderlake: Add PMC register base for ADL-NUsha P
Add PCR_PSF3_TO_SHDW_PMC_REG_BASE for Alderlake-N.This value is updated from the FSP code. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I7c788e149744bfae2c5260c996b16fc1ce2070c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61148 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-01soc/intel/alderlake: Select SOC_INTEL_COMMON_BLOCK_SCS for Alder Lake NKrishna Prasad Bhat
Alder Lake N has eMMC storage device. Select SOC_INTEL_COMMON_BLOCK_SCS Kconfig for Alder Lake N. Change-Id: I577ffdc80ef09471309c827551a347d4397a33d1 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-01soc/intel/alderlake: Add eMMC PCR Port ID for Alder Lake NKrishna Prasad Bhat
Alder Lake N has eMMC storage device. Add PCR Port ID for it. Reference: Alder Lake N platform EDS Doc# 645548. Change-Id: I6dc494d1748e66b8b4058954f127ec226863e8af Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-01soc/intel/alderlake: Add GPP_I GPIO group for Alder Lake N SOCKrishna Prasad Bhat
Add definitions for GPP_I GPIO group pins on Alder Lake N SOC and GPIO IRQ routing information. GPP_I GPIO group belongs to GPIO community 1. Hence GPIO community 1 in Alder Lake N contains GPP_S, GPP_I, GPP_H, GPP_D GPIO groups. GPIO groups 1-6 in Doc# 645550 Chapter 36 corresponds to GPIO communities 5-0 respectively. BUG=b:213535859 Change-Id: Ia71a399c03cb7d098a381bd9439d448e8a620761 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61106 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-31soc/intel/adl: Update devicetree based on remapping for TBT PCIeMAULIK V VAGHELA
ADL has 4 TBT root ports which are PCIe compliant. TBT uses PCIe coalescing logic where in case root port 0 is disabled, other enabled root port is remapped to port 0. coreboot handles this remapping scenarios for PCH and CPU PCIe root ports and not for TBT root ports. This patch uses the same function used for PCIe remapping to update devicetree based on coalescing and SoC needs to pass correct function number and number of slots. BUG=b:210933428 BRANCH=None TEST=Check if TBT remapping happens correctly and ACPI tables are generated correctly. Change-Id: Ied16191d6af41f8e2b31baee80cb475e7d557010 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-31intel/common/block/pcie: Add NULL/count check in pcie_rp_update_devtreeMAULIK V VAGHELA
pcie_rp_update_devicetree function takes pcie_rp_group strcuture as an argument and SoC code passes the parameter in this structure. This pointer can be NULL and common code may try to dereference this NULL pointer. Also, group might have no data and SoC may pass this by indicating group count as zero (For example, for CPU or TBT root ports). These checks will prevent function from executing redundant code and returning early from the call as it's not required. BUG=b:210933428 BRANCH=None TEST=check if function returns early for group count 0 and there is no issue while booting board in case group count = 0. Change-Id: I132319bb05fdef1590c18302fc64cc76e15bea6d Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-31soc/amd/sabrina: Add PRE_X86_CBMEM_CONSOLE_SIZEFelix Held
Commit 86302a806c5cc9b575424305e761753710417692 (soc/amd/{common, cezanne,picasso}: Add PRE_X86_CBMEM_CONSOLE_SIZE) added this Kconfig option before the initial commit that added soc/amd/sabrina as copy of soc/amd/cezanne landed in the tree, so port the change forward to Sabrina. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2e8df5e7b7f1ac0af772e8c565f616a68b28e29e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-15 02:35:47 +0000