diff options
| author | Zheng Bao <fishbaozi@gmail.com> | 2022-02-11 11:53:32 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-12 17:07:09 +0000 |
| commit | c5b912f788765560c1db08f3341826b9c548b865 (patch) | |
| tree | 4a825193a60a1bb4e7012918bf772649abd29593 /src/soc | |
| parent | 514965a9ce2ea698e6a67d3b7dd38e98381e3699 (diff) | |
soc/amd/cezanne: Allow to specify SPL table path in Kconfig
BUG=b:216096562
Change-Id: I4a5ee335ea8808b595dc65ebafd15baedfbdd06e
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/cezanne/Kconfig | 14 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/Makefile.inc | 7 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/fw.cfg | 1 |
3 files changed, 21 insertions, 1 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 40ba4c1024..c0c500d3fa 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -377,6 +377,20 @@ config PSP_WHITELIST_FILE depends on HAVE_PSP_WHITELIST_FILE default "3rdparty/amd_blobs/cezanne/PSP/wtl-czn.sbin" +config HAVE_SPL_FILE + bool "Have a mainboard specific SPL table file" + default n + help + Have a mainboard specific SPL table file, which is created by AMD + and put to 3rdparty/blobs. + + If unsure, answer 'n' + +config SPL_TABLE_FILE + string "SPL table file" + depends on HAVE_SPL_FILE + default "3rdparty/amd_blobs/cezanne/PSP/TypeId0x55_SplTableBl_CZN.sbin" + config PSP_SOFTFUSE_BITS string "PSP Soft Fuse bits to enable" default "28 6" diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 332268ccf8..302deaa4ce 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -127,6 +127,11 @@ ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y) PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE) endif +# type = 0x55 +ifeq ($(CONFIG_HAVE_SPL_FILE),y) +SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) +endif + # # BIOS Directory Table items - proper ordering is managed by amdfwtool # @@ -196,6 +201,7 @@ OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), -- OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) +OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table) # Add all the files listed in the config file POUND_SIGN=$(call strip_quotes, "\#") @@ -213,6 +219,7 @@ AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ --combo-capable \ $(OPT_TOKEN_UNLOCK) \ $(OPT_WHITELIST_FILE) \ + $(OPT_SPL_TABLE_FILE) \ $(OPT_PSP_SHAREDMEM_BASE) \ $(OPT_PSP_SHAREDMEM_SIZE) \ $(OPT_EFS_SPI_READ_MODE) \ diff --git a/src/soc/amd/cezanne/fw.cfg b/src/soc/amd/cezanne/fw.cfg index f26e21555e..9757d7249e 100644 --- a/src/soc/amd/cezanne/fw.cfg +++ b/src/soc/amd/cezanne/fw.cfg @@ -28,7 +28,6 @@ UNIFIEDUSB_FILE TypeId0x44_UnifiedUsb_CZN.sbin DRTMTA_FILE TypeId0x47_DrtmTA_CZN.sbin KEYDBBL_FILE TypeId0x50_KeyDbBl_CZN.sbin KEYDB_TOS_FILE TypeId0x51_KeyDbTos_CZN.sbin -SPL_TABLE_FILE TypeId0x55_SplTableBl_CZN.sbin DMCUERAMDCN21_FILE TypeId0x58_DmcuEramDcn21.sbin DMCUINTVECTORSDCN21_FILE TypeId0x59_DmcuIntvectorsDcn21.sbin PSPBTLDR_AB_FILE TypeId0x73_PspBootLoader_AB_CZN.sbin |