diff options
| author | MAULIK V VAGHELA <maulik.v.vaghela@intel.com> | 2022-01-21 14:17:53 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-31 10:33:47 +0000 |
| commit | 3e4f28f8c2596ffbc2d7dec4095c6ecfc4b25f19 (patch) | |
| tree | 7237bb439271c16e35395a6b02c9ec79b9c7628d /src/soc | |
| parent | 948ed24ac5d437c2cbda9fc6beb076b72c3f2a4a (diff) | |
soc/intel/adl: Update devicetree based on remapping for TBT PCIe
ADL has 4 TBT root ports which are PCIe compliant. TBT uses PCIe
coalescing logic where in case root port 0 is disabled, other enabled
root port is remapped to port 0.
coreboot handles this remapping scenarios for PCH and CPU PCIe root
ports and not for TBT root ports.
This patch uses the same function used for PCIe remapping to update
devicetree based on coalescing and SoC needs to pass correct function
number and number of slots.
BUG=b:210933428
BRANCH=None
TEST=Check if TBT remapping happens correctly and ACPI tables are
generated correctly.
Change-Id: Ied16191d6af41f8e2b31baee80cb475e7d557010
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/alderlake/Kconfig | 6 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/chip.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/include/soc/pcie.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/pcie_rp.c | 10 |
4 files changed, 20 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 89d0c93791..dc7d32b6c1 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -207,6 +207,12 @@ config MAX_CPU_ROOT_PORTS default 0 if SOC_INTEL_ALDERLAKE_PCH_N default 3 if SOC_INTEL_ALDERLAKE_PCH_P +config MAX_TBT_ROOT_PORTS + int + default 0 if SOC_INTEL_ALDERLAKE_PCH_N + default 2 if SOC_INTEL_ALDERLAKE_PCH_M + default 4 if SOC_INTEL_ALDERLAKE_PCH_P + config MAX_ROOT_PORTS int default MAX_PCH_ROOT_PORTS diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index 1fa78fbcd9..9127c5e302 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -142,6 +142,9 @@ void soc_init_pre_device(void *chip_info) /* Swap enabled PCI ports in device tree if needed. */ pcie_rp_update_devicetree(get_pch_pcie_rp_table()); + + /* Swap enabled TBT root ports in device tree if needed. */ + pcie_rp_update_devicetree(get_tbt_pcie_rp_table()); } static void cpu_fill_ssdt(const struct device *dev) diff --git a/src/soc/intel/alderlake/include/soc/pcie.h b/src/soc/intel/alderlake/include/soc/pcie.h index cd76d09e4a..6b3ca5406f 100644 --- a/src/soc/intel/alderlake/include/soc/pcie.h +++ b/src/soc/intel/alderlake/include/soc/pcie.h @@ -7,5 +7,6 @@ const struct pcie_rp_group *get_pch_pcie_rp_table(void); const struct pcie_rp_group *get_cpu_pcie_rp_table(void); +const struct pcie_rp_group *get_tbt_pcie_rp_table(void); #endif /* __SOC_ALDERLAKE_PCIE_H__ */ diff --git a/src/soc/intel/alderlake/pcie_rp.c b/src/soc/intel/alderlake/pcie_rp.c index 26ce785e8e..f38105af71 100644 --- a/src/soc/intel/alderlake/pcie_rp.c +++ b/src/soc/intel/alderlake/pcie_rp.c @@ -61,6 +61,16 @@ const struct pcie_rp_group *get_cpu_pcie_rp_table(void) return cpu_rp_groups; } +static const struct pcie_rp_group tbt_rp_groups[] = { + { .slot = SA_DEV_SLOT_TBT, .count = CONFIG_MAX_TBT_ROOT_PORTS}, + { 0 } +}; + +const struct pcie_rp_group *get_tbt_pcie_rp_table(void) +{ + return tbt_rp_groups; +} + static bool is_part_of_group(const struct device *dev, const struct pcie_rp_group *groups) { |