diff options
-rw-r--r-- | src/soc/intel/alderlake/Kconfig | 6 | ||||
-rw-r--r-- | src/soc/intel/alderlake/chip.c | 3 | ||||
-rw-r--r-- | src/soc/intel/alderlake/include/soc/pcie.h | 1 | ||||
-rw-r--r-- | src/soc/intel/alderlake/pcie_rp.c | 10 |
4 files changed, 20 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 89d0c93791..dc7d32b6c1 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -207,6 +207,12 @@ config MAX_CPU_ROOT_PORTS default 0 if SOC_INTEL_ALDERLAKE_PCH_N default 3 if SOC_INTEL_ALDERLAKE_PCH_P +config MAX_TBT_ROOT_PORTS + int + default 0 if SOC_INTEL_ALDERLAKE_PCH_N + default 2 if SOC_INTEL_ALDERLAKE_PCH_M + default 4 if SOC_INTEL_ALDERLAKE_PCH_P + config MAX_ROOT_PORTS int default MAX_PCH_ROOT_PORTS diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index 1fa78fbcd9..9127c5e302 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -142,6 +142,9 @@ void soc_init_pre_device(void *chip_info) /* Swap enabled PCI ports in device tree if needed. */ pcie_rp_update_devicetree(get_pch_pcie_rp_table()); + + /* Swap enabled TBT root ports in device tree if needed. */ + pcie_rp_update_devicetree(get_tbt_pcie_rp_table()); } static void cpu_fill_ssdt(const struct device *dev) diff --git a/src/soc/intel/alderlake/include/soc/pcie.h b/src/soc/intel/alderlake/include/soc/pcie.h index cd76d09e4a..6b3ca5406f 100644 --- a/src/soc/intel/alderlake/include/soc/pcie.h +++ b/src/soc/intel/alderlake/include/soc/pcie.h @@ -7,5 +7,6 @@ const struct pcie_rp_group *get_pch_pcie_rp_table(void); const struct pcie_rp_group *get_cpu_pcie_rp_table(void); +const struct pcie_rp_group *get_tbt_pcie_rp_table(void); #endif /* __SOC_ALDERLAKE_PCIE_H__ */ diff --git a/src/soc/intel/alderlake/pcie_rp.c b/src/soc/intel/alderlake/pcie_rp.c index 26ce785e8e..f38105af71 100644 --- a/src/soc/intel/alderlake/pcie_rp.c +++ b/src/soc/intel/alderlake/pcie_rp.c @@ -61,6 +61,16 @@ const struct pcie_rp_group *get_cpu_pcie_rp_table(void) return cpu_rp_groups; } +static const struct pcie_rp_group tbt_rp_groups[] = { + { .slot = SA_DEV_SLOT_TBT, .count = CONFIG_MAX_TBT_ROOT_PORTS}, + { 0 } +}; + +const struct pcie_rp_group *get_tbt_pcie_rp_table(void) +{ + return tbt_rp_groups; +} + static bool is_part_of_group(const struct device *dev, const struct pcie_rp_group *groups) { |