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2024-08-22soc/intel/common/tcss: Move AUX bias ctrl reg defines to SOC hdrCliff Huang
These field defines are SOC-specific. The AUX bias virtual wire field positons are shifted in PTL. In MTL SOC and older: 7:0 GROUP_ID Group ID in PCH GPIO 10:8 BIT_NUM Data bit Position in PCH GPIO 23:16 VW_INDEX VW Index in PCH GPIO In PTL SOC: 15:0 GROUP_ID Group ID in PCH GPIO; targeted SB_PORTID 18:16 BIT_NUM Data bit Position in PCH GPIO 31:24 VW_INDEX VW Index in PCH GPIO BUG=361048817 TEST=boot to OS and use iotools to read AUX Bias Ctrl register to verify the group ID, bit number, and vw index. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I0f9c895590465b2f539c91834cf331fcd7efa996 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83980 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2024-08-22soc/intel/jasperlake: Add CrashLog implementation for Intel JSLJędrzej Ciupis
Extend support for CrashLog to Intel Jasperlake based platforms. This commit is based on 15cbc3b5996ae64aff2e4741c4c3ec3d7f5cc1a7, originally reviewed on https://review.coreboot.org/c/coreboot/+/49943. BUG=b:354834461 TEST=CrashLog can be enabled in Kconfig for Jasperlake based platforms and can generate a BERT table, if enabled. Change-Id: Ia18a79d8de849d556b4b8fd0e6b43090311eb23f Signed-off-by: Jędrzej Ciupis <jciupis@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-08-22soc/intel/alderlake: Refactor eSOL for late CSE sync text messageSubrata Banik
This patch extends the eSOL implementation on Alder Lake to render text messages during late CSE sync (from ramstage). Currently, the eSOL is limited to the early boot phase (until romstage) and only displays FSP-M memory training warnings or messages during early CSE sync (at romstage). Platforms like Nissa/Nirul and Trulo, which use CSE sync from ramstage, cannot display any eSOL messages, resulting in a brief black screen during CSE firmware updates. This patch implements the following logic to scale eSOL for late CSE sync (at ramstage) without recompiling eSOL code for ramstage: 1. During boot, check if the MRC cache is available. This indicates the need for memory/DRAM training and triggers an eSOL message. 2. For CSE lite SKUs (applicable to CrOS), leverage the `is_cse_fw_update_required` API to check if the current CSE RW firmware version differs from the CBFS metadata file version. If so, trigger an eSOL message indicating a CSE sync is required. 3. If either condition #1 and/or #2 is true, the AP firmware renders an eSOL text message using LibGfxInit for the Alder Lake platform. BUG=b:359814797 TEST=eSOL text messages are displayed during CSE sync and FSP updates. tirwen-rev3 ~ # elogtool list 0 | ... | Log area cleared | 4088 1 | ... | Early Sign of Life | MRC Early SOL Screen Shown 1 | ... | Early Sign of Life | CSE Sync Early SOL Screen Shown 2 | ... | System boot | 197 3 | ... | Memory Cache Update | Normal | Success 4 | ... | System boot | 198 5 | ... | Firmware Splash Screen | Enabled Change-Id: I1c7d4475ed5cf6888df1beebab0641ee4203b497 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83975 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com>
2024-08-22soc/intel/alderlake: Preserve eSOL for late CSE syncSubrata Banik
This patch prevents the eSOL screen from being wiped out on Alder Lake platforms that use late CSE sync (from ramstage). This allows the eSOL text message to remain visible until ramstage. Currently, the eSOL only functions during the early boot phase (until romstage), so platforms like Nissa/Nirul and Trulo, which use CSE sync from ramstage, cannot display any eSOL messages to the user. A future patch will ensure the eSOL remains relevant for CSE sync in ramstage, but this patch is necessary to avoid tearing down the IGD text mode when exiting romstage. BUG=b:359814797 TEST=eSOL text mode is not torn down when exiting romstage. Change-Id: I81548b4057ab95ce3da0dbc69703977baf0581f1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-08-21soc/intel/ptl: Dump SoC QDF from report_cpu_info in bootblockJamie Ryu
This enables SOC_QDF_DYNAMIC_READ_PMC and adds pmc_dump_soc_qdf_info to report_cpu_info to dump QDF information from bootblock. Change-Id: Iaf6f46cd9be831dde345c3b3728cd66145746d68 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Saurabh Mishra <mishra.saurabh@intel.com>
2024-08-21soc/intel/cmn/pmc: Add pmc_ipc to bootblockJamie Ryu
This adds pmc_ipc to bootblock if SOC_INTEL_COMMON_BLOCK_PMC is enabled. The good place to report SoC QDF can be report_cpu_info in bootblock. QDF read is done by PMC IPC Command, so this adds pmc_ipc to bootblock to enable calling pmc_dump_soc_qdf_info. Change-Id: Id0391eae48fc53cd652acd09e6380ca6802eaf88 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-21soc/intel/common/block/cpu: Round up the number of waysJeremy Compostella
`CONFIG_DCACHE_RAM_SIZE' is not necessarily a multiple of way size. As a result, when the `div' instruction is called to compute the needed number of ways, there could be a remainder. When there is, one extra way should be added to cover `CONFIG_DCACHE_RAM_SIZE'. BUG=b:360332771 TEST=Verified on PTL Intel reference platform Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521e Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83982 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-21soc/intel/common/block/cpu: Fix ways count computation regressionJeremy Compostella
Commit 16ab9bdcd578612bb3822373547f939eb90afd82 ("soc/intel/common: Calculate and configure SF Mask 2") breaks the computation of the number of ways and as result, all the derived masks. It results in MSR such as `IA32_L3_MASK_1' to be improperly programmed yielding unpredictable NEM issues such as hangs. Indeed, this commit has introduced a backup of 0x1 into %edx before comparing the requested cache-as-RAM size against the way size. When the requested cache-as-RAM is larger, it reaches the second part of the algorithm which computes the necessary number of ways to fit the requested cache-as-RAM. This algorithm uses the `div' instruction. Per specification, the div instruction divides the 64 bits combination of %edx and %eax register. Since 0x1 got backed up in %edx and assuming a `CONFIG_DCACHE_RAM_SIZE' of 0x200000, we end up dividing 0x100200000 by the way size instead of 0x200000 which result in a necessary number of ways of 4098 for a way size of 0x100000. This commit clears the %edx register before calling the `div' instruction. BUG=b:360332771 TEST=Verified on PTL Intel reference platform Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521d Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83948 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-21soc/intel/common: fix CrashLog size in legacy modeJędrzej Ciupis
Intel's PMC CrashLog size in legacy mode is expressed in DWORDs and therefore needs to be explicitly recalculated to bytes. BUG=None TEST=Built and checked the size in logs Change-Id: I2678d537439c24fbd10aa3ceffee63c9a849d28b Signed-off-by: Jędrzej Ciupis <jciupis@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-08-21soc/intel/pantherlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENTSubrata Banik
This patch replaces the SoC-specific config option `SOC_INTEL_PANTHERLAKE_DEBUG_CONSENT` with the generic `SOC_INTEL_COMMON_DEBUG_CONSENT`. TEST=Able to build and boot google/fatcat without any functional impact while debugging. Change-Id: I36bbe14d02654ed9dbda21df0d9a6a6769b87754 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83962 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-21soc/intel/meteorlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENTSubrata Banik
This patch replaces the SoC-specific config option `SOC_INTEL_METEORLAKE_DEBUG_CONSENT` with the generic `SOC_INTEL_COMMON_DEBUG_CONSENT`. Additionally, updates the FSP configuration to use the new generic config option. TEST=Able to build and boot google/rex0 without any functional impact while debugging. Change-Id: I657d20a38e15eee333a4e45c0c600736148173d4 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83961 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-21soc/intel/alderlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENTSubrata Banik
This patch replaces the SoC-specific config option `SOC_INTEL_ALDERLAKE_DEBUG_CONSENT` with the generic `SOC_INTEL_COMMON_DEBUG_CONSENT`. Additionally, updates the FSP configuration to use the new generic config option. TEST=Able to build and boot google/redrix without any functional impact while debugging. Change-Id: I9a9c81b72d707f5ed2e1a53c139ee22be0e30068 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-08-21soc/intel/tigerlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENTSubrata Banik
This patch drops the SoC-specific config option `SOC_INTEL_TIGERLAKE_DEBUG_CONSENT`. Additionally, updates the FSP configuration to use the new generic config option. TEST=Able to build and boot google/volteer without any functional impact while debugging. Change-Id: I3e96b20e7e8b3ce3c2e4884abd315a5cc55fe71d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-08-21soc/intel/jasperlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENTSubrata Banik
This patch drops the SoC-specific config option `SOC_INTEL_JASPERLAKE_DEBUG_CONSENT`. Additionally, updates the FSP configuration to use the new generic config option. TEST=Able to build and boot google/dedede without any functional impact while debugging. Change-Id: I3e7abaf5fb3a0d5528041af5ce767a15fc738870 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83960 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-21soc/intel/elkhartlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENTSubrata Banik
This patch drops the SoC-specific config option `SOC_INTEL_ELKHARTLAKE_DEBUG_CONSENT`. Additionally, updates the FSP configuration to use the new generic config option. TEST=Able to build and boot intel/elkhartlake_crb without any functional impact while debugging. Change-Id: Idb8db7230c432792e742218d41d891c529b2114f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83959 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-21soc/intel/cannonlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENTSubrata Banik
This patch drops the SoC-specific config option `SOC_INTEL_CANNONLAKE_DEBUG_CONSENT`. Additionally, updates the FSP configuration to use the new generic config option. TEST=Able to build and boot google/hatch without any functional impact while debugging. Change-Id: Ifad11652b5fa6ff14f713f55a721cdbbfbfde471 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83958 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-20soc/intel/meteorlake/chip.h: Use boolean type where applicableMichael Strosche
Change-Id: I15dfd5ed0541352930c3b70252b3e536ad1e6efd Signed-off-by: Michael Strosche <michael.strosche@gmail.com> Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-08-20soc/intel/cmn/basecode/debug: Add SOC_INTEL_COMMON_DEBUG_CONSENT configSubrata Banik
This patch adds a generic config option, SOC_INTEL_COMMON_DEBUG_CONSENT, to control the debug interface on Intel SoCs. This eliminates the need for SoC-specific config options like SOC_INTEL_<SOC_NAME>_DEBUG_CONSENT. Default values are provided for various debug types: - 0: Disabled - 1: Enabled (DCI OOB + [DbC]) - 2: Enabled (DCI OOB) - 3: Enabled (USB3 DbC) - 4: Enabled (XDP/MIPI60) - 5: Enabled (USB2 DbC) - 6: Enabled (2-wire DCI OOB) - 7: Manual Specific SoCs can override the SOC_INTEL_COMMON_DEBUG_CONSENT value using SoC config override methods. TEST=Able to build google/rex. Change-Id: I84ad03f0ffe5da4bc53c665489c430fe9b65ede7 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-08-20soc/intel/elkhartlake: Select SOC_INTEL_COMMON_BASECODESubrata Banik
This patch selects the SOC_INTEL_COMMON_BASECODE option for Elkhart Lake so that future patches can incorporate the common code debug feature with it. TEST=Able to build the EHL platform. Change-Id: I71d95352fe627a7f1912f802aa971ad1ebbbead7 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-08-16soc/intel/ptl: Do initial Panther Lake SoC commit till romstageSaurabh Mishra
List of changes: 1. Add required SoC programming till romstage 2. Include only required headers into include/soc 3. Fill required FSP-M UPD to call FSP-M API 4. Ref: Processor EDS documents Panther Lake U/H 12Xe/H 4Xe External Design Specification (EDS) Rev. 0.7, vol 1 of 2 #815002 and Volume 2 of 2 #813030 BUG=b:348678529 TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Change-Id: I27e1a6c56bca01e7f5f53fbf3cb6855bac7b2848 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-15soc/intel/xeon_sp/uncore_acpi: use is_dev_on_domain0 where possibleFelix Held
Replace 'is_domain0(dev_get_domain(dev))' with 'is_dev_on_domain0(dev)' which is a helper function that does exactly the same, but slightly simplifies the call. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8b0c52a9176288039e6414a09c3fe0662db79e4b Reviewed-on: https://review.coreboot.org/c/coreboot/+/83908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-08-15soc/intel/alderlake: Correct ISH partition availability checkSubrata Banik
The previous implementation incorrectly assumed that the presence of a UFS device implied the availability of the ISH partition. This is not always true, especially on Alder Lake platforms where ISH may be enabled by default even without UFS. This patch fixes the issue by directly checking for the presence of the ISH device to determine if the ISH partition is available. BUG=b:359440547 TEST=1. Able to dump the ISH version with UFS device: ``` tirwen-rev3 ~ # cbmem -c -1 | grep ISH [DEBUG] ISH version: 5.4.2.7780 ``` 2. Able to dump the ISH version with eMMC device: ``` trulo-rev1 ~ # cbmem -c | grep ISH [DEBUG] ISH version: 5.4.2.7780 ``` Change-Id: I411e36606c0697f91050af40e0636f7c64810e95 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-08-14soc/intel/adl,mtl/romstage/fsp_params: fix clock request warningFelix Held
If a root port doesn't use a clock request pin, we shouldn't check if this pin number, which defaults to 0 when not set, is already used. This fixes the following spurious warning that was previously printed for each external PCIe port which has the 'PCIE_RP_CLK_REQ_UNUSED' flag set and didn't set 'clk_req' to some unused clock request pin number: Found overlapped clkreq assignment on clk req 0 Tested on the cw-al-4l-v2.0 mainboard that uses an Alder Lake N100 SoC which I'm currently porting coreboot to. Also changing this for Meteor Lake, since they have the same implementation in their romstage fsp_params.c file Change-Id: I3ee66ca5ed5a2d06dfb68c45a50e11eb2b93daa0 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-08-13soc/intel/mtl: enable FSP uGOP config in MTL for eSOLJayvik Desai
This patch updates the platform-specific Meteor Lake early sign-of-life config (SOC_INTEL_METEORLAKE_SIGN_OF_LIFE) with a generic ChromeOS eSOL config (CHROMEOS_ENABLE_ESOL) which uses the Intel FSP uGOP driver as an underlying technology for rendering eSOL screen. This patch does not change the binary or the system behaviour. BUG=b:352651132 TEST=Able to build google/rex and checked the config in output. Change-Id: Ib4589f52080229b1c83915b51272a042b7ac32cd Signed-off-by: Jayvik Desai <jayvik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83769 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-13soc/intel/adl: update libgfx config to a generic eSOL configJayvik Desai
This patch updates the early libgfx init config (MAINBOARD_HAS_EARLY_LIBGFXINIT) used for Alder Lake SoC with a generic CrOS/ChromeOS early sign of life config (CHROMEOS_ENABLE_ESOL) This patch does not change the binary or the system behaviour and is only meant to bind the early GFX initialization with a generic eSOL config. BUG=b:352651132 TEST=Able to build google/tivviks and checked the config in output Change-Id: Ibc1b9190ac0e4d25f3c5517d74c9b519bc3bb349 Signed-off-by: Jayvik Desai <jayvik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83841 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-11soc/intel/xeon_sp/gnr: Remove VPD from GNR KconfigGang Chen
Remove the unused config VPD from GNR Kconfig. Change-Id: I3fc45ba05df5fc23e326081d6ce9e53b2046464c Signed-off-by: Gang Chen <gang.c.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82975 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-08-11soc/intel/ptl: Do initial Panther Lake SoC commit till bootblockSaurabh Mishra
List of changes: 1. Add required Pather Lake SoC programming till bootblock. 2. Include only required headers into include/soc. 3. Include PTL related DID, BDF. 4. Includes additional minimal code required to compile the PTL SoC and google/fatcat mainbaord. 5. Ref: Processor EDS documents vol0.51 #815002 BUG=b:348678529 TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83354 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-11soc/intel/common/block/gpmr: Allow soc to have specific gpmr definitionYuchi Chen
This patch add a new Kconfig HAVE_SPECIFIC_GPMR and use it to include soc/gpmr.h if necessary. Change-Id: I94797a72af75fc96ab2cacb1d46b581605a15387 Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83317 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-11azalia: Get rid of "return {-1,0}Elyes Haouas
Use 'enum cb_err' instead of {-1,0}. Change-Id: Icea33ea3e6a5e3c7bbfedc29045026cd722ac23e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-08-11region: Introduce region_create() functionsNico Huber
We introduce two new functions to create region objects. They allow us to check for integer overflows (region_create_untrusted()) or assert their absence (region_create()). This fixes potential overflows in region_overlap() checks in SMI handlers, where we would wrongfully report MMIO as *not* overlapping SMRAM. Also, two cases of strtol() in parse_region() (cbfstool), where the results were implicitly converted to `size_t`, are replaced with the unsigned strtoul(). FIT payload support is left out, as it doesn't use the region API (only the struct). Change-Id: I4ae3e6274c981c9ab4fb1263c2a72fa68ef1c32b Ticket: https://ticket.coreboot.org/issues/522 Found-by: Vadim Zaliva <lord@digamma.ai> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-08-10tree: Remove duplicated <arch/mmio.h>Elyes Haouas
<device/mmio.h> is supposed to chain-include <arch/mmio.h>. See `Documentation/contributing/coding_style.md` section `Headers and includes` Change-Id: I08f7480650b42df1613994146a026bd1e12dbf66 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-08-10tree: Remove unused <smbios.h>Elyes Haouas
Change-Id: Iab7e9f3d17c87576761333c4b62c40eea5e424a5 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-08-10soc/mediatek/common: Refactor EINT driverYidi Lin
Refactor EINT driver by - Move `pos_bit_calc_for_eint` to `common/gpio_eint_v1.c` and rename to `gpio_calc_eint_pos_bit`. - Implement `gpio_get_eint_reg` to obtain EINT base address. This change is prepared for the driver change in MT8196. BUG=b:334723688 TEST=EINT works on Geralt Change-Id: Ie53abc23971bfa39250ebd7dd48e28d6b91c5973 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83703 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-10soc/intel/common/block/gpio/gpio.c: Improve GPIO debug infosYuchi Chen
1. print host software ownership, SMI enable and NMI enable registers after configuring 2. read and print GPIO configuration dword registers after writing 3. use %zu to print size_t values according to CI reporting. Change-Id: I8820956f6db91c7bcc26b46a4361da3dfa8f77b5 Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83316 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-09soc/amd/*: pass PSP RPMC NVRAM base and size to amdfwtoolFelix Held
Pass the PSP NVRAM base and size to amdfwtool for all SoCs except Genoa and Stoneyridge which don't use/support this. If a mainboard has an section named 'PSP_RPMC_NVRAM' in its FMAP file, the start and length of it in the flash will be passed to amdfwtool which then adds the base and length to the corresponding type 0x54 PSP directory table entry. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id9f8a7eec68a5222be63e46173132f1c4a461b4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/83815 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-08-09device/pci_ids: Add new Intel PTL device IDs for TracehubBora Guvendik
This patch adds new North Peak PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the tracehub driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Boot to OS using PTL Silicon, verify if above 4GB IMR region is reserved. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ifa1a0a57c504e06d686e7e0826547251b456cc8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/83786 Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-09soc/intel/cmn/block/cse: Add support for explicit CSE_RW_VERSIONSubrata Banik
This change adds support for specifying the CSE_RW_VERSION directly in Kconfig. * If `CONFIG_SOC_INTEL_CSE_RW_VERSION` is defined, its value will be used directly as the CSE_RW version. * Otherwise, the version will be extracted from the CSE_RW binary file as before. Platform prior to Intel Meteor Lake still requires to override the CSE RW version using CONFIG_SOC_INTEL_CSE_RW_VERSION config rather reading the CSE RW version from CSE RW partition. BUG=b:327842062 TEST=CSE RW update successful on Karis with this patch using below recipe: 1. Overriding the CONFIG_SOC_INTEL_CSE_RW_VERSION="18.0.5.2269" 2. Without overriding the CONFIG_SOC_INTEL_CSE_RW_VERSION="" Platform prior to Intel Meteor Lake would be using #1 and platform starting with Meteor Lake expected to use #2 recipe. Change-Id: I1327c813b7aef77c65766eb9c40003bb8a71d4b6 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83831 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-08-09soc/intel/cmn/pmc: Add API to dump silicon QDF informationJamie Ryu
This adds pmc_dump_soc_qdf_info function and PMC_IPC_CMD_SOC_REG_ACC PMC IPC Command to read and print Intel SoC QDF information using PMC interface if SOC_QDF_DYNAMIC_READ_PMC is enabled. QDF read command is supported from Panther Lake SoC. QDF is a four digit code that can be used to identify enabled features and capabilities. This information will be useful to debug issues found during the development phase and in the field as well. Change-Id: I927da1a97e6dad4ee54c4d2256fea5813a0ce43d Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83784 Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-08soc/amd/*: pass PSP NVRAM base and size to amdfwtoolFelix Held
Pass the PSP NVRAM base and size to amdfwtool for all SoCs except Genoa which doesn't use/support this. This was previously only implemented for Picasso, but not for the SoCs that support this, so add the support to those other SoCs as well. If a mainboard has an section named 'PSP_NVRAM' in its FMAP file, the start and length of it in the flash will be passed to amdfwtool which then adds the base and length to the corresponding type 0x04 PSP directory table entry. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I785ede8eb0df2473a4390b2c305add20f38d7ede Reviewed-on: https://review.coreboot.org/c/coreboot/+/83814 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-08-08soc/amd/picasso/Makefile: move PSP_NVRAM_[BASE,SIZE]Felix Held
Move PSP_NVRAM_BASE and PSP_NVRAM_SIZE from the BIOS directory table items to the PSP Directory Table items, since the corresponding region will be referenced by the PSP directory table and not the BIOS directory table. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iff7568ea05c701ecd346cc7590cf93b091ff31a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83813 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-08-07soc/amd/common/psp_smi_flash: add buffer overflow checksFelix Held
Before 'handle_psp_command' calls any of the functions in this file, it make sure that the 'size' field in the command buffer's header doesn't indicate that the command buffer is larger than the SMM memory region reserved for it. The read/write command buffer has a 'num_bytes' field to indicate how many bytes should be read from the SPI flash and put into the data buffer within the command buffer or how many bytes from this buffer should be written to the flash. While we should be able to assume that the PSP won't send us malformed command buffer, we should still better check this just to be sure. Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib4e8514eedc3ad154a705c8a1e85d367e452dbed Reviewed-on: https://review.coreboot.org/c/coreboot/+/83778 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-07soc/amd/common/psp_smi_flash: implement SPI read/write/erase commandFelix Held
Use coreboot's SPI flash access infrastructure to do the flash read, write, or erase operations as requested from the PSP. This patch is a modified version of parts of CB:65523. Document #55758 Rev. 2.04 was used as a reference. Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Change-Id: I4957a6d316015cc7037acf52facb6cc69188d446 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2024-08-07soc/amd/common/psp_smi_flash: implement SPI info commandFelix Held
Detect the block size of the SPI flash and number of flash blocks reserved for the flash region corresponding to the 'target_nv_id' field in the command buffer. This information is then written to the corresponding fields in the command buffer. Since detecting the flash chip still might result in accesses to it, make sure that it's available for use and not currently used by an OS driver. Since this code is inside the SMI handler, we don't have to worry about this code to be interrupted, so we don't need to set some bit to tell other code that we're currently using the SPI controller in the SMI handler. This patch is a modified version of parts of CB:65523. Document #55758 Rev. 2.04 was used as a reference. Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Change-Id: I19041a27a9e8f901d42c3f60af834df625455ea6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83776 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-07soc/amd/common/psp_smi_flash: add spi_controller_availableFelix Held
The SPI_SEMAPHORE_DRIVER_LOCKED bit in the SPI_MISC_CNTRL register doesn't affect the hardware, but it re-used by AMD as a semaphore to synchronize the access to the SPI controller between SMM and non-SMM software like an OS-level driver. Since it doesn't affect the hardware, it's marked as reserved in the PPRs. Add the 'spi_controller_available' helper function to check this bit to see if some software or driver outside of SMM is currently using the SPI flash controller to avoid interfering with that operation. This patch is a slightly reworked version of parts of CB:65523. Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Change-Id: I49218e03a5dd555b2b2d34eaad86673e9fc908c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83775 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-07soc/amd/common/psp_smi_flash: add find_psp_spi_flash_device_regionFelix Held
Add 'find_psp_spi_flash_device_region' to get a pointer to the spi_flash struct of the SPI flash used in the system and the region_device struct for the target FMAP region specified by the target NV ID from the PSP to x86 mailbox command. In order to have small patches, the newly added static 'find_psp_spi_flash_device_region' function is marked as inline; that inline will be removed in a following patch that calls this new function. This patch is a slightly reworked version of parts of CB:65523. Document #55758 Rev. 2.04 was used as a reference. Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Change-Id: I64b8fba2392de46ecd4c786cef0d5b6acdbd865a Reviewed-on: https://review.coreboot.org/c/coreboot/+/83774 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-07soc/amd/common/psp_smi_flash: validate target SPI region IDFelix Held
Add and use functions to validate the target non-volatile storage ID in the different command buffer structs. This patch is a slightly reworked version of parts of CB:65523. Document #55758 Rev. 2.04 was used as a reference. Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Change-Id: Idda0166c862d41d380b2ed21345eead5e0a1c135 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83758 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-07soc/amd/common/psp_smi_flash: add command-specific data structuresFelix Held
This patch is a slightly modified version of parts of CB:65523. Document #55758 Rev. 2.04 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Change-Id: I41efeecf9243ddbbd8dc3f842c5ce11058bb7999 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83757 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-07soc/amd/common/psp: add and call PSP SMI SPI access function stubsFelix Held
Add stub functions for the SPI flash access from the PSP SMI handler and call them for the corresponding P2C mailbox commands. Parts of this patch are taken from CB:65523. Document #55758 Rev. 2.04 was used as a reference. Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Change-Id: Iedbc9d41eb0d4e8d81eeba9c01281161eb839991 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83756 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-07soc/amd/common/psp_smi: implement P2C mailbox handlingFelix Held
When the PSP wants to access the SPI flash during runtime, but isn't the owner of the SPI flash controller, it sends an SMI to the x86 side. The corresponding SMI handler then checks the P2C (PSP to core) mailbox for the command and data, processes the command, and if needed puts the requested data into the P2C buffer. The P2C mailbox is a memory region in TSEG aka SMM memory. Both location and size are communicated to the PSP via the PSP SMM info mailbox command which is sent right after mpinit is done. This commit adds the code to access the P2C mailbox to the PSP SMI handler code, but the handling of the actual mailbox commands the PSP sends to the SMI handler is added in later patches to keep the patch size manageable. This patch is a heavily reworked version of parts of CB:65523. Document #55758 Rev. 2.04 was used as a reference. Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Change-Id: I50479bed2332addae652026c6818460eeb6403af Reviewed-on: https://review.coreboot.org/c/coreboot/+/83740 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-08-07soc/amd/common/include/spi: add and use SPI_MISC_CNTRL defineFelix Held
This register is currently used by the SPI DMA code that sets an undocumented bit. A later patch will add and use some other bit in this register. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I48447dcfb3cee07619a9b42434731f0b21458021 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83773 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-06intel/alderlake: Add helper functions for Power ManagementSean Rhodes
Clock Power Management, ASPM and L1 Substates have been configured the same way since Skylake. The main control to enable or disable is Kconfig, and then the level can be overridden in devicetree. Despite the UPDs remaining the same since Skylake, this is not the case for Alder Lake, Raptor Lake and Meteor Lake. Taking `starlabs/starbook` as an example, at the time of this commit it has PCIEXP_CLK_PM, PCIEXP_ASPM and PCIEXP_L1_SUB_STATE enabled. On Comet Lake, this results in the correct configuration, verified with the lspci command: ``` LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L1, Exit Latency L1 <8us ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+ LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+ ExtSynch- ClockPM+ AutWidDis- BWInt- AutBWInt- ``` On Raptor Lake: ``` LnkCap: Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+ LnkCtl: ASPM Disabled; RCB 64 bytes, Disabled- CommClk+ ``` Clock Power Management, ASPM and L1 Substates are also not configured for CPU root ports. Add helper functions to configure these correctly based on Kconfig, but retain the capability to override the specific levels from devicetree. Change-Id: I9db18859f9a04ad4b7c0c3f7992b09e0f9484a81 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81638 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-08-06soc/intel/common/intelblocks/gpio.h: Allow specifying the pad ownershipYuchi Chen
Add pad_own_reg_0 to `struct pad_community`. Pad ownership indicates whether the GPIO is owned by host or Intel Management Engine. If owned by host, then host ownership indicates whether the GPIO is owned by ACPI or driver. Change-Id: I30a934fd00a7a42cb156341da1954e4e4b1231d8 Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83315 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-06soc/intel/common: Add CPU and PCIe IDs for Snow Ridge platformYuchi Chen
CPU and PCIe IDs are from Intel Atom Processor C5100, C5300, P5300 and P5700 Product Families EDS, doc No. 575160 rev 2.0. Change-Id: I3f5d612765bbe9adffe0b6c7a4151f32b33e88b4 Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83314 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-05soc/amd: add PSP SMI handler stubFelix Held
The PSP can send SMIs to the x86 side to have the SMI handler service requests from the PSP. This commit adds an empty PSP SMI handler; the actual implementation is added in later patches to keep the patches relatively small. This patch is a slightly modified version of parts of CB:65523. Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Change-Id: I65989ff529d728cd9d2cd60b384295417bef77ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/83739 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-02soc/ti/am335x: Remove superfluous formatsArthur Heymans
These formats are already included in memlayout.ld. Change-Id: I89d226440308ce3fbe00382698dcd8c88863e694 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-08-02soc/ti/am335x: Use Linker instead of compiler to linkArthur Heymans
Clang does not work that well as a linker for the header as it will default to other linkers which do not work well here. Instead just use the linker directly. Change-Id: Id6ba42b470349a4b138a65b2a037f16a65982ef7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-08-02soc/intel/common/block/cse: Enforce CSE sync with pertinent GBB flagDinesh Gehlot
The patch enforces CSE sync when the GBB flag GBB_FLAG_FORCE_CSE_SYNC is enabled and the system is currently booting from the RO section. Additionally, it integrates forced CSE sync into eSOL decision-making. BUG=b:353053317 TEST=Verified forced CSE sync on rex0 with GBB 0x200000 Cq-Depend: chromium:5718196 Change-Id: I228bc8ebf58719776f6c39e0bfbb7ad53d9bfb7f Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-02soc/ti/am335x: Change and optimize memlayoutArthur Heymans
Clang builds (bootblock: 20800 bytes) are slightly larger than GCC builds (bootblock: 18688 bytes) so increase the size of both bootblock and romstage. The technical reference manual mentions no upper limit to the size of the bootblock in the TI header so increasing the bootblock size is allowed. To be able to link the clang bootblock increase it from 20K to 22K. Change-Id: I8719bc3728d4cc8dba8d939cc154c3fc0884d47b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-08-01soc/amd/common/smi_util: add PSP SMI helper functionsFelix Held
The PSP can send SMIs to the x86 side of the system. Add helper functions to configure and to reset the PSP SMI generation. Since Stoneyridge also selects SOC_AMD_COMMON_BLOCK_SMI, add the SMITRIG0_PSP define and rename SMITYPE_FCH_FAKE0 to SMITYPE_PSP in its SoC-specific smi.h to bring it in line with the newer SoCs. This patch is split out from CB:65523. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Change-Id: I525a447c9a75fdb95b9750e85a02896056315edf Reviewed-on: https://review.coreboot.org/c/coreboot/+/83702 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-01soc/intel/xeon_sp: Add acpigen_write_pci_root_portLu, Pen-ChunX
acpigen_write_pci_root_port writes SSDT device objects for PCIe root port, _ADR and _BBN are provided. SSDT objects for direct subordinate devices will also be created (if detected), _ADR and _SUN are provided. TEST=Build and boot on intel/archercity CRB Change-Id: I434fea7880a463c2027abfa22ba2b3bb985815c0 Signed-off-by: Lu, Pen-ChunX <pen-chunx.lu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-07-31soc/amd/common/psp: move buffer sizes to common headerFelix Held
Since the P2C_BUFFER_MAXSIZE value will be needed in another compilation unit, move the define to the common psp_def.h. P2C_BUFFER_MAXSIZE is moved there too for consistency reasons. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8d4d93760c90ad6e0ecadf70600b1d697a02fa82 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83701 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-31soc/amd/common/psp_smm: introduce and use send_psp_command_smmFelix Held
When sending mailbox commands to the PSP from SMM, the SMM flag needs to be set right before sending the mailbox command and cleared right after the command is sent. In order to not have this code duplicated, factor it out into a function. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3628463dece9d11703d5a068fe7c604108b69c1f Reviewed-on: https://review.coreboot.org/c/coreboot/+/83700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-07-31soc/amd/common/psp_smm: add comments to psp_notify_smmFelix Held
The reasoning behind this and the positive side effects of this aren't too clear from the code, so point those out in a comment. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4f4121031fc1ef600cdf5551f61f1ef4e03b56a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-07-31soc/amd/common/psp_smm: add/improve comments to buffers and flagsFelix Held
Since it's not exactly obvious what 'c2p_buffer', 'p2c_buffer' and 'smm_flag' are used for, add comments to those. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4ec092a92fe9f0686ffb7103e441802fc05381f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-07-31device/path: rename domain path struct element to 'domain_id'Felix Held
Rename the 'domain' element of the 'domain_path' struct to 'domain_id' to clarify that this element is the domain ID. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Martin Roth <gaumless@gmail.com> Change-Id: I3995deb83a669699434f0073aed0e12b688bf6e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83677 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-07-31device: introduce and use dev_get_domain_idFelix Held
To avoid having constructs like 'dev->path.domain.domain' in the SoC code, create the 'dev_get_domain_id' helper function that returns the domain ID of either that device if it's a domain device or the corresponding domain device's domain ID, and use it in the code. If this function is called with a device other than PCI or domain type, it won't have a domain number. In order to not need to call 'die', 'dev_get_domain_id' will print an error and return 0 which is a valid domain number. In that case, the calling code should be fixed. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3d79f19846cea49609f848a4c42747ac1052c288 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83644 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-31soc/intel/adl: Update DCACHE_BSP_STACK_SIZEKarthikeyan Ramasubramanian
During the stages which use Cache-as-RAM (CAR), coreboot needs more than 1 KiB as configured in DCACHE_BSP_STACK_SIZE. After studying the UPDs for various SoCs(ADL-P, ADL-N, RPL), coreboot stack requirement is estimated to be 32 KiB. Update DCACHE_BSP_STACK_SIZE accordingly. BUG=None TEST=Build Brox BIOS image and boot to OS. Change-Id: I723ba1f4289c393fe7376f989d760b26e75b33da Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83680 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-07-29soc/mediatek/mt8196/memlayout: Fix the location of BOOTBLOCK commentYu-Ping Wu
The comment for the BOOTBLOCK region should be written right above the BOOTBLOCK declaration. BUG=b:317009620 TEST=none BRANCH=none Change-Id: I7afdf74844a9d97169b4e4a23c3c9c6060e886d9 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83649 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-27Revert "soc/intel/adl: Guard TWL SoC missing UPDs for build integrity"Subrata Banik
This reverts commit 59ee65d271c7c617bcc240019231da4f0bd04db6. Reason for revert: - Usb4CmMode & CnviWifiCore Upds are available starting with TWL FSP version v5222.01. Therefore, no special handling is required. BUG=b:330654700 TEST=Able to build google/tivviks. Change-Id: I3c74ec5b9924e88a26984fe8d3275ba80edb14ab Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2024-07-26soc/intel/meteorlake: Remove unnecessary #if ENV_RAMSTAGESubrata Banik
TEST=Able to build google/rex. Change-Id: I0de87a2ff5ecb37f00ec745ad930e83f6356a3fe Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83637 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-26soc/intel/xeon_sp/gnr: Add dimm_slot configurationJincheng Li
Add sample DIMM slot configuration table for avenuecity CRB and beechnutcity CRB. This table will be used to fill SMBIOS type 17 table. TEST=Boot on intel/avenuecity CRB It will help to update Locator, Bank Locator and Asset Tag with the value described in dimm_slot_config_table Change-Id: I53556c02eb75204994a1bcb42eccb940e83bd532 Signed-off-by: Jincheng Li <jincheng.li@intel.com> Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83326 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-26soc/intel/mtl: Increase CAR_STACK_SIZE by 31KB for coreboot compatibilityRishika Raj
This change increases the DCACHE_BSP_STACK_SIZE from 512KB + 1KB to 512KB + 32KB, addressing a requirement specified by coreboot where stack usage is higher than 1KB alone. BUG=None TEST=None Change-Id: Iba3620b3b7c470176330f5e07989cd3f6238713e Signed-off-by: Rishika Raj <rishikaraj@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83540 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-07-26soc/mediatek/mt8188/memlayout: Add a space in SRAM_L2C_START commentYu-Ping Wu
Change-Id: I1888fedcc66ae13c76331d3f2f4465197ae51d35 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-07-25soc/amd/common/psp_gen2: use MMIO access againFelix Held
Now that we have a get_psp_mmio_base function that will work on all SoCs that use the psp_gen2 code, we can move back to accessing the PSP registers via their MMIO mapping. This sort-of reverts commit 198cc26e4951 ("soc/amd/common/block/psp/psp_gen2: use SMN access to PSP"). When doing SMN accesses from the SMI handler after the OS has taken over ownership of the platform, there's the possibility to cause trouble by clobbering the SMN access index register from SMM. So that should be either avoided completely or the SMI code needs to save and restore the original contents of the SMN index register. The PSP MMIO base will be set up by the FSP before the resource allocation in coreboot and be treated like a fixed resource by the allocator. The first SMI where corresponding handler calls 'get_psp_mmio_base' happens when ramstage triggers the APM_CNT_SMMINFO SMI right after mpinit which happens after the resource allocation. So the PSP MMIO base address is expected to be configured and so the 'get_psp_mmio_base' function will cache the base address and won't need to do any SMN access in subsequent calls that might happen after the OS has take over control. This isn't currently an issue, since the only PSP mailbox command from the SMI handler after coreboot is done and the OS has taken over will be during the S3/S4/S5 entry, and this will be triggered by the OS as the last step after it is done with all its preparations for suspend/ shutdown. There will however be future patches that add SMI-handlers which can send PSP mailbox commands during OS runtime, and so we have to make sure we don't clobber the SMN index register. TEST=PSP mailbox commands are still sent correctly on Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I25f16d575991021d65b7b578956d9f90bfd15f6c Reviewed-on: https://review.coreboot.org/c/coreboot/+/83448 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-25soc/amd/common/psp_gen2: return status from soc_read_c2p38Felix Held
This sort-of reverts commit 00ec1b9fc7ba ("soc/amd/common/block/psp/ psp_gen2: simplify soc_read_c2p38") and is done as a preparation to switch back to using the MMIO access to the PSP mailbox registers. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icca3c7832295ae9932778f6a64c493e474dad507 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2024-07-25soc/amd/common/block/psp_gen2: add get_psp_mmio_baseFelix Held
Add get_psp_mmio_base which reads the PSP MMIO base address from the hardware registers. Since this function will not only be called in ramstage, but also in SMM, we can't just look for the specific domain resource consumer like it is done for the IOAPICs in the northbridge, but have to get this base address from the registers. In order to limit the performance impact of this, the base address gets cached in a static variable if an enabled PSP MMIO base register is found. We expect that this register is locked when it was configured and enabled; if we run into the unexpected case that the PSP MMIO register is enabled, but not locked, set the lock bit of the corresponding base address register to be sure that it won't change until the next reset and that the hardware value can't be different than the cached value. This is a preparation to move back to using MMIO access to the PSP registers and will also enable cases that require the use of the MMIO mapping of the PSP registers. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1d51e30f186508b0fe1ab5eb79c73e6d4b9d1a4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/83446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2024-07-25soc/amd: add SoC-specific root_complex.c to SMMFelix Held
The PSP code introduced in a following patch needs both SoC-specific functions get_iohc_info and get_iohc_non_pci_mmio_regs to also be available in SMM, so add those compilation units to the corresponding target. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4e32084b45f07131c80b642bc73d865fc57688a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-07-25soc/amd/*/root_complex: introduce and use domain_iohc_info structFelix Held
Instead of implementing the functions get_iohc_misc_smn_base and get_iohc_fabric_id in the SoC code, move those functions to the common AMD code, and implement get_iohc_info in the SoC code that returns a pointer to and the size of a SoC-specific array of domain_iohc_info structs that contains the info needed by the common code instead. This allows to iterate over the domain_iohc_info structs which will be used in a later patch to find the PSP MMIO base address in both ramstage and smm. TEST=Mandolin still boots and all non-PCI MIO resources are still reported to the resource allocator Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifce3d2b540d14ba3cba36f7cbf248fb7c63483fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/83443 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2024-07-25acpi,soc: use is_domain0 functionFelix Held
No need to open-code this when we have a function for this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iae570ba750cb29456436349b4263808e2e410e2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/83643 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-07-25device: move is_domain0 and is_dev_on_domain0 to common codeFelix Held
Move is_domain0 and is_dev_on_domain0 from the Intel Xeon SP code to the common coreboot code so that it can be used elsewhere in coreboot too, and while moving also implement it as functions instead of macros which is more in line with the rest of helper functions in that new file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I954251ebc82802c77bf897dfa2db54aa10bc5ac4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83642 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-25soc/amd: Ensure bank 0 is selected before accessing VBNV in CMOSYu-Ping Wu
In AMD platforms, the bit 4 of CMOS's Register A (0x0a) is DV0 bank selection (0 for Bank 0; 1 for Bank 1) [1]. Since the MC146818 driver accesses VBNV via Bank 0, the bit must be cleared before we can save VBNV to CMOS in verstage. Usually there's no problem with that, because the Register A is configured in cmos_init() in ramstage. However, if CMOS has lost power, then in the first boot after that, the bit may contain arbitrary data in verstage. If that bit happens to be 1, then CMOS writes in verstage will fail. To fix the problem, define vbnv_platform_init_cmos() to call cmos_init(0), which will configure the Register A and therefore allow saving VBNV to CMOS in verstage. [1] 48751_16h_bkdg.pdf BUG=b:346716300 TEST=CMOS writes succeeded in verstage after battery cutoff BRANCH=skyrim Change-Id: Idf167387b403be1977ebc08daa1f40646dd8c83f Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83495 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-25soc/amd/psp_verstage: Add -Oz flag for clangYu-Ping Wu
When we tried to add CMOS support to PSP verstage (CB:83495), the clang builds failed on boards with cezanne SoC (such as Guybrush), due to over-sized verstage. On the other hand, there is no such problem for gcc builds on the same boards. Building PSP verstage by clang generates much larger verstage size (81K) compared with using gcc (67K). To unblock adding features to verstage, temporarily enable -Oz for clang builds. Change-Id: I033458556986ade88fb8e68499b632deae4dd419 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-07-24soc/intel/xeon_sp: Share save_dimm_info among Xeon-SP SoCsJincheng Li
TEST=Build and boot on archercity CRB No changes in boot log and 'dmidecode' result under centos TEST=Build and boot on avenuecity CRB It will add DMI type 16,17,19,20 Change-Id: I2f5b7a4ffabed033d54d4724b3c41246503166fe Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-07-23soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoCJarried Lin
Add new folder and basic drivers for Mediatek SoC 'MT8196'. Refer to MT8196_Chromebook_Application_Processor_Datasheet_V1.0 for MT8196 SPEC detail. This patch also enables UART and ARM arch timer. TEST=saw the coreboot uart log to bootblock BUG=b:317009620 Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-07-22lib/smbios: Create SMBIOS type 4 entryJincheng Li
One smbios type 4 should be provided for each CPU instance. Create SMBIOS type 4 entry according to socket number, with a default value of 1. TEST=Boot on intel/archercity CRB No changes in boot log and 'dmidecode' result under centos Change-Id: Ia47fb7c458f9e89ae63ca64c0d6678b55c9d9d37 Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83331 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-22soc/mediatek: Move memmory macros into MediaTek common directoryJarried Lin
To reduce duplicate memmory macros of MediaTek SoCs, move the header file to a common directory. TEST=Build geralt pass BUG=b:317009620 Change-Id: Iea4add8fe3735085c13438a2e177bec177913191 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83571 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-22soc/mediatek: Move symbols.h into MediaTek common directoryJarried Lin
To reduce duplicate region declarations of MediaTek SoCs, move the header file to a common directory. BUG=b:317009620 TEST=Build geralt pass. Change-Id: Iad1c9f520cdc5c6ad2b55e8f4ec6149fa47b17b1 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83570 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-22soc/intel/xeon_sp/spr: Return updated resource index for create_ioat_domainShuo Liu
create_ioat_domain creates the domain device with a number of resources. Return the updated resource index so that the updated index could be used as the starting index for additional resource creation outside create_ioat_domain. TEST=Build and boot on intel/archercity CRB Change-Id: I9e719ae8407c7f31f88dbb407f003e2ded8f0faf Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-07-22soc/intel/alderlake/tcss: Add definition of IOM_READY bitMichał Żygowski
Add definition of the IOM_READY bit in the IOM_TYPEC_STATUS_1 register. Needed by Protectli VP66XX boards to poll for this bit for about 2 seconds before FSP Silicon Init to have USB functionality. ME is supposed to start fetching and executing the TCSS IPs FW right after DRAM Init Done message, which happens after MRC. For most platforms the time interval between the end of MemoryInit and start of SiliconInit is enough for IOM_READY to get set. TEST=Poll the IOM_READY bit on VP66XX platform and observe the TCSS XHCI is up in lspci. Change-Id: If868a77852468ebb73526b1571191cbdeb1804b9 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83356 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-22soc/amd/common/root_complex: move IOHC_MMIO_EN definition to headerFelix Held
To be able to use the IOHC_MMIO_EN define in other compilation units, move the define to the corresponding header file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If88950418406d1709ed95b3d05f7e6ad66438f95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-07-21soc/intel/meteorlake/chip.h: Drop unused PmTimerDisabled settingFelix Singer
Change-Id: I6155ec45408dca83573c86e6db1ead5a82a0d77a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for CNViSubrata Banik
This patch adds new CNVi PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the CNVi driver's `pci_device_ids` list to include these new IDs. Finally, dropped unused BT PCI IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I7d80403b87537aea41ff48ff6d274180577f1ac6 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83520 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for XDCISubrata Banik
This patch adds new XDCI PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the XDCI driver's `pci_device_ids` list to include these new IDs. Finally, dropped unused TCSS XDCI PCI IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I51196401904e2402ac7669fa852a541bb7c2d453 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83518 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for CSE0Subrata Banik
This patch adds new CSE0 PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the CSE0 driver's `pci_device_ids` list to include these new IDs. Finally, dropped unused CSE1-3 PCI IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I5656aeb8c5439c8361aeb3a3d759df1216d84f8b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83517 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for AudioSubrata Banik
This patch adds new Audio (HDA/DSP) PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the Audio driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I3c9e420a6ae19d00fb5510c99d4c219dc43ad3c0 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83516 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for SRAMSubrata Banik
This patch adds new SRAM PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the SRAM driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: Ib6d62dad59965258dab453533dface9c359de586 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83515 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for P2SBxSubrata Banik
This patch adds new P2SBx PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the P2SBx driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: Ie1c36bc1c014bb1e219afe0cafb6c9941f253b0c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for XHCI/TCSS XHCISubrata Banik
This patch adds new XHCI/TCSS XHCI PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the XHCI driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I5ae8f493374087a5e684e0a04486cd64cea6f335 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83513 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for SMBUSSubrata Banik
This patch adds new SMBUS PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the SMBUS driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I4b8b59cf4e005f0e17a25d0fbe761404dab432b3 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83512 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for Fast-SPI and GSPIxSubrata Banik
This patch adds new Fast-SPI and GSPIx PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the SPI driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I5c7c0be6f219c93d4520494857d31ce1cf939f36 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83511 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-29 00:39:20 +0000