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BUG=b:182963902
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_HEROBRINE -x -a -B
Change-Id: I3ec557bdf2286c3f60902d5ac018b536fe99afa3
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57896
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This file does not exist in the coreboot tree. One should place this
file in the `site-local` subdirectory and specify the paths by means
of `site-local/Kconfig`.
Change-Id: I86ac2a6176947f12194bec6b63bedd7db79820a0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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mb_set_up_early_espi should only be called when
SOC_AMD_COMMON_BLOCK_USE_ESPI is selected.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic8ad724a2a79c1995fbe9d97f11a0f69eed9435c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Enable CCP DMA use in PSP verstage. This helps to reduce the boot time.
BUG=b:194990811
TEST=Build and boot to OS in Guybrush. Observed a 35 - 40 ms improvement
in the boot time.
Before CCP DMA:
508:finished loading body 898,286 (287,576)
Total Time: 2,146,182
After CCP DMA:
508:finished loading body 853,627 (240,061)
Total Time: 2,110,117
Cq-Depend: chrome-internal:4116566
Change-Id: I6e4f081622a2ec78763adf56548204efc1bccf39
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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PSP verstage can access the boot device either in Programmed I/O mode or
DMA mode. Introduce a boot device driver and use the appropriate mode
based on the SoC support.
BUG=b:194990811
TEST=Build and boot to OS in Guybrush.
Change-Id: I8ca5290156199548916852e48f4e11de7cb886fb
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57563
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add support to access the boot device from PSP through Crypto
Co-Processor (CCP) DMA. Implement a SVC call to use CCP DMA on SoCs
where it is supported and a stub on SoCs where it is not supported. This
provides an improved performance while accessing the boot device and
reduces the boot time by ~45 ms.
BUG=b:194990811
TEST=Build and boot to OS in guybrush. Perform cold and warm reboot
cycling for 250 iterations.
Change-Id: I02b94a842190ac4dcf45ff2d846b8665f06a9c75
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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The Always On Always Connected block is referenced as AOAC in the code,
so add that acronym in the comment and change the "Connect" to
"Connected".
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6a23e0ccff62c6ceddae70e1bef5c5abf872c495
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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`intel_microcode_find()` function uses cached ucode data hence it would
avoid locating ucode.bin from CBFS while passing ucode.bin pointer to
FSP.
Change-Id: I8f92c9f20dfb055c19c6996e601c8c24767aecb7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This change replaces the device tree walks with device pointers by
using alias for tcss_usb3_port* devices.
Change-Id: I65d9c83a9d0aab5a42f5a7cc6df98a154e79d16a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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TEST=Timeless build for Mandolin results in identical image.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib2fb6c29b9f42c00f252994ae2a40b7ff668105a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Since the binaryPI glue code is specific to a binary interface, but not
for a hardware block, move it out of the common blocks directory. This
also brings the binaryPI support in line with the FSP support which is
used on the newer generations. This also drops the
SOC_AMD_COMMON_BLOCK_PI Kconfig option and makes use of the already
existing SOC_AMD_PI Kconfig option instead.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I014e538f2772938031950475e456cc40dd05d74c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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The code in soc/amd/common/block/s3 is specific to the AMD binaryPI
coreboot integration, so move the code to soc/amd/common/block/pi. This
drops the SOC_AMD_COMMON_BLOCK_S3 Kconfig option and integrates the
dependencies and selections into the SOC_AMD_COMMON_BLOCK_PI Kconfig
option. Since only selecting SOC_AMD_COMMON_BLOCK_PI but not
SOC_AMD_COMMON_BLOCK_S3 resulted in missing functions in the linking
process, we don't lose support for any working configuration by only
having one Kconfig option for both parts.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib2bd99a88d8b05216688bc45d9c4f23a007ce870
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This change add MaxDramSpeed for variants usage to config dram speed.
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: Iba0fae0ab4ff0121dc63af792458492eeb21ec2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This brings the AMD SoC GPIO code in line with the Intel SoC code and
removes the not really needed suffix.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie2dbec81dfe503869beb2872b01a7475e2b88b33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This brings the AMD SoC GPIO code in line with the Intel SoC code and
removes the not really needed suffix.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3dfcca2f126eb49c962b5cc32cbcf72e04f3f170
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Use the same function name as in soc/intel for this functionality. This
also brings the function name more in line with the extended version of
this function gpio_configure_pads_with_override which additionally
supports passing a GPIO override configuration.
This might cause some pain for out-of-tree boards, but at some point
this should be made more consistent, so I don't see a too strong reason
not to do this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I88852e040f79861ce7d190bf2203f9e0ce156690
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Explicitly point out that gpio_configure_pads_with_override will ignore
GPIOs that are only in the override configuration, but not in the base
configuration.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1bdfcac89b81fef773938133a2699897c6ee9415
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Some headers in vendorcode are still needed but the UPD definitions
can be taken from the FSP repo.
Change-Id: I7bb96649ecba9d313cfce50af202aabcf610680f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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coreboot expects different names for FSP UPDs so use some CPP to make
it happy.
Change-Id: I4b2c2dd6ba40cb58bc2089eb9204fd4f70b037aa
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Reference: Intel doc# 633935-005 and 547817 rev1.5.
Change-Id: I38c20288a9839f8c3cf895f7b49941387bdca5e2
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Lance Zhao
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
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Reference: Intel doc# 631120-001.
Change-Id: Iaf3a1b7bc38a1b30f8cc901bd6496e77f2d92cfd
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Reference: Intel doc# 341081-002.
Change-Id: If6e0503cc042c26c4077b8b32bb447d4e3a9bb6a
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add NMI_EN and NMI_STS registers, so NMI interrupts can be used.
References:
- XEON-SP: Intel doc# 633935-005 and 547817 rev1.5
- ICL-LP: Intel doc# 341081-002
- TGL-LP: Intel doc# 631120-001
- TGL-H: Intel doc# 636174-002
- JSL: Intel doc# 634545-001
- EHL: Intel doc# 636722-002
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I2621f4495dfd4f95f9774d9081e44c604de830a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lance Zhao
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There is another gpio group, namely HVCMOS, between GPP_C and GPP_E. Add
it, so the group index calculation for GPI/SMI/NMI results in the
correct value.
Reference: Linux linux/drivers/pinctrl/intel/pinctrl-icelake.c
Change-Id: I7725191173ddc0d43bbe940cdf3b0dc2aa3e5f8d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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SPD files are being moved from the soc and mainboard directories to a
centralised spd/ directory. This change migrates all dedede variants to
use this new location. The contents of the new SPDs are identical, only
their file paths have changed.
The variant Makefile.inc and dram_id.generated.txt files were generated
using the part_id_gen tool. E.g. for cret:
util/spd_tools/bin/part_id_gen \
JSL \
lp4x \
src/mainboard/google/dedede/variants/cret/memory \
src/mainboard/google/dedede/variants/cret/memory/mem_parts_used.txt
For cappy, the Makefile.inc was manually modified to use the new
placeholder value.
BUG=b:191776301
TEST=Check that each variant's coreboot.rom is the same with and without
this change. Built using:
abuild -p none -t google/dedede -a -x --timeless
Change-Id: I2871ff45d6202520d4466b68a4d5bb283faf2b63
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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SPD files are being moved from the soc and mainboard directories to a
centralised spd/ directory. This change migrates all volteer variants to
use this new location. The contents of the new SPDs are identical, only
their file paths have changed.
The variant Makefile.inc and dram_id.generated.txt files were generated
using the part_id_gen tool. E.g. for voema:
util/spd_tools/bin/part_id_gen \
TGL \
lp4x \
src/mainboard/google/volteer/variants/voema/memory \
src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt
BUG=b:191776301
TEST=Check that each variant's coreboot.rom is the same with and without
this change. Built using:
abuild -p none -t google/volteer -a -x --timeless
Change-Id: Ibd4f42fd421bfa58354b532fe7a67ee59dac5e1d
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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SPD files are being moved from the soc and mainboard directories to a
centralised spd/ directory. This change migrates all brya variants to
use this new location. The contents of the new SPDs are identical, only
their file paths have changed.
The variant Makefile.inc and dram_id.generated.txt files were generated
using the part_id_gen tool. E.g. for anahera:
util/spd_tools/bin/part_id_gen \
ADL \
lp4x \
src/mainboard/google/brya/variants/anahera/memory \
src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt
BUG=b:191776301
TEST=Check that each variant's coreboot.rom is the same with and without
this change. Built using: abuild -p none -t google/brya -a -x --timeless
Change-Id: I08efe1d75438c81161d9b496af2fa30ce6f59ade
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Move existing UART driver from sc7180 to common folder.
This implements UART driver for QCOM SoC's
BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board.
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I7bc2d3765f956e04bae3e45c3a9b9e2ad424c7b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Before this patch, gpio_configure_pads_with_override called
program_gpios once for each GPIO that needed to be configured which
resulted in base_num_pads - 1 unneeded master_switch_set/
master_switch_clr sequences for the gpio_configure_pads_with_override
call. Instead implement gpio_configure_pads_with_override as the more
generic function and program_gpios as a special case of that which
passes an empty override configuration and override pad number to
gpio_configure_pads_with_override.
TEST=GPIO configuration and multiplexer register values are the same for
all GPIOs on google/guybrush right before jumping to the payload before
and after the patch.
Change-Id: Ia8e47b2a278a1887db5406c1f863ddafa6a68675
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Earlier generation platform used `HeciEnabled` chip config (set to 0)
and HECI_DISABLE_USING_SMM Kconfig to make the CSE function disable at
the end of the post. `HeciEnabled` chip config remains enabled in all
latest generation platforms hence drop HECI_DISABLE_USING_SMM Kconfig
selection from SoC Kconfig as CSE remains default enabled.
BUG=b:200644229
TEST=No functional impact during boot as CSE (B:0, D:0x16, F:0) device
is listed with `lspci`.
Change-Id: I5278e5c2e015b91bb3df3a3c73a6c659a56794b5
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
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In this file bool, uint8_t and uint32_t are used, so include types.h
directly to have those types defined instead of relying to have those
included indirectly via amdblocks/gpio_banks.h.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6f4626a50219fab818e8bc5087961a731b44e71b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This implements the SPI driver for the QUP core.
BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board.
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I7e5d3ad07f68255727958d53e6919944d3038260
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56399
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:182963902
TEST=Validated on qualcomm sc7280 developement board
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I34a45422e38ea3a47f29e9856fc5679e8aebbcdf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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This implements qup spi driver for qualcomm chipsets
Rename header file names for trogdor to prevent breakage.
BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board.
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I2f2b25b6661fcd518f70383da0c7788c5269c97b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55953
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:182963902
TEST=Validated on qualcomm sc7280 developement board
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I58c2b79ea2feeab0ad4c2b7cdaa041984160a7ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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copy existing I2C driver from /soc/qualcomm/sc7180 to common folder.
This implements i2c driver for qualcomm chipsets
BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I16e6fc2c1c24b9814d1803bffd5cfbb657201cfb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Enable common qup driver in sc7280
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I0e9049557ff63898037210e72333e1739ab62413
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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The aliases are defined in the chipset devicetree, so the device
pointers will be available for all boards using this SoC.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id4c921575e978bb29e61f35e78ff2a1711acf06a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The aliases are defined in the chipset devicetree, so the device
pointers will be available for all boards using this SoC.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id655e9eba9b8e9898fa01bf03876074e136cc7c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Normally for vboot-enabled x86 board, the VBNV region is stored in CMOS
and backed up to flash (RW_NVRAM). However, on the very first boot after
a flash of the full SPI image (so RW_NVRAM is empty), if
RTC_BATTERY_DEAD is set, coreboot persistently requests recovery before
FSP-M finishes (which appears to be the current location that
RTC_BATTERY_DEAD is cleared on this platform). This is because
vbnv_cmos_failed() will still return 1. Therefore, immediately after
reading RTC_BATTERY_DEAD, it is cleared. This prevents an infinite boot
loop when trying to set the recovery mode bit.
Note that this was the behavior for previous generations of Intel PMC
programming as well (see southbridge/intel, soc/skylake, soc/broadwell,
etc).
BUG=b:181678769
Change-Id: I95753fa536fae8ca4bb95007419875815c1bcb06
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Normally for vboot-enabled x86 board, the VBNV region is stored in CMOS
and backed up to flash (RW_NVRAM). However, on the very first boot after
a flash of the full SPI image (so RW_NVRAM is empty), if
RTC_BATTERY_DEAD is set, coreboot persistently requests recovery before
FSP-M finishes (which appears to be the current location that
RTC_BATTERY_DEAD is cleared on this platform). This is because
vbnv_cmos_failed() will still return 1. Therefore, immediately after
reading RTC_BATTERY_DEAD, it is cleared. This prevents an infinite boot
loop when trying to set the recovery mode bit.
Note that this was the behavior for previous generations of Intel PMC
programming as well (see southbridge/intel, soc/skylake, soc/broadwell,
etc).
BUG=b:181678769
Change-Id: I1a55df754c711b2afb8939b442019831c25cce29
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Normally for vboot-enabled x86 board, the VBNV region is stored in CMOS
and backed up to flash (RW_NVRAM). However, on the very first boot after
a flash of the full SPI image (so RW_NVRAM is empty), if
RTC_BATTERY_DEAD is set, coreboot persistently requests recovery before
FSP-M finishes (which appears to be the current location that
RTC_BATTERY_DEAD is cleared on this platform). This is because
vbnv_cmos_failed() will still return 1. Therefore, immediately after
reading RTC_BATTERY_DEAD, it is cleared. This prevents an infinite boot
loop when trying to set the recovery mode bit.
Note that this was the behavior for previous generations of Intel PMC
programming as well (see southbridge/intel, soc/skylake, soc/broadwell,
etc).
BUG=b:181678769
Change-Id: Idfaa9a24f7b7fefa4f63ab8e3bc4ee6a0f1faedf
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
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Normally for vboot-enabled x86 board, the VBNV region is stored in CMOS
and backed up to flash (RW_NVRAM). However, on the very first boot after
a flash of the full SPI image (so RW_NVRAM is empty), if
RTC_BATTERY_DEAD is set, coreboot persistently requests recovery before
FSP-M finishes (which appears to be the current location that
RTC_BATTERY_DEAD is cleared on this platform). This is because
vbnv_cmos_failed() will still return 1. Therefore, immediately after
reading RTC_BATTERY_DEAD, it is cleared. This prevents an infinite boot
loop when trying to set the recovery mode bit.
Note that this was the behavior for previous generations of Intel PMC
programming as well (see southbridge/intel, soc/skylake, soc/broadwell,
etc).
BUG=b:181678769
Change-Id: Ie86822f22aa5899a7e446398370424ca5a4ca43d
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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This enables runtime power management for the I2C controllers.
BUG=b:182556027, b:183983959
TEST=enable dynamic debug in kernel and check i2c D3/D0 transitions
during suspend_stress_test.
Change-Id: Ia6b9ca95d751f32b7cd701494377f15091c22d2f
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56462
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This enables runtime power management for the UART controllers.
BUG=b:183983959
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4e57d6312feda459cec65f330c6d2072774d4eb5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Currently, Intel TME (Total Memory Encryption) can be enabled regardless
of SoC support. Add a Kconfig to guard the option depending on actual
support.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Ia20152bb0fc56b0aec3019c592dd6d484829aefe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Migrate the last two platforms to using Kconfig through
`get_valid_prmrr_size()` instead of hardcoded values in the devicetree.
Change-Id: I93aa177f741ca8b2a2d50fae2515606b96784e83
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Apart from the bool type, uint8_t, uint32_t and uint64_t are used in
this file, so include types.h instead of stdbool.h.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I30088d68132058f40b974fbaa822f322b58ed6c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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When using a debug build of the FSP, the FSP-M binary is larger than the
memory region we have allocated for it, so increase the size to make the
binary of the debug build fit in there. Also adjust the VERSTAGE_ADDR so
that it starts right after the the FSP-M memory region.
TEST=coreboot builds now successfully when using a debug version of the
FSP
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib64806bcf948d5ed4bcf8e1f50004091f125dc7e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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vboot_reference is introducing a new field (ctx) to store the current
boot mode in crrev/c/2944250 (ctx->bootmode), which will be leveraged
in both vboot flow and elog_add_boot_reason in coreboot.
In current steps of deciding bootmode, a function vb2ex_ec_trusted
is required. This function checks gpio EC_IN_RW pin and will return
'trusted' only if EC is not in RW. Therefore, we need to implement
similar utilities in coreboot.
We will deprecate vb2ex_ec_trusted and use the flag,
VB2_CONTEXT_EC_TRUSTED, in vboot, vb2api_fw_phase1 and set that flag
in coreboot, verstage_main.
Also add a help function get_ec_is_trusted which needed to be
implemented per mainboard.
BUG=b:177196147, b:181931817
BRANCH=none
TEST=Test on trogdor if manual recovery works
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Change-Id: I479c8f80e45cc524ba87db4293d19b29bdfa2192
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57048
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:179699789
TEST=build morphius
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I298ce1ee436a5c8eb8375dc5fe55665bbf977463
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Needed for cpuid_ext.
BUG=b:179699789
TEST=build morphius
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib3a132bea06443ee4c1501b1c746400c541fd805
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Update the TLMM register values for eMMC and SD card on Trogdor,
Herobrine and Mistral boards.
BUG=b:196936525
TEST=Validated on qualcomm sc7280 and sc7180 development board and checked
basic boot up.
Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org>
Change-Id: Iccdb7757027c6de424a82e4374bad802501ac83c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57450
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Updated return type as CB_SUCCESS and aligned indentation.
BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Change-Id: Ifabe0508a37a841779965f4e38172f680e18d38a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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FspMultiPhaseSiInit API was introduced with FSP 2.2 specification
onwards. EnableMultiPhaseSiliconInit is an arch UPD also introduced
as part of FSP 2.2 specification to allow calling FspMultiPhaseSiInit
API.
However, some platforms adhere to the FSP specification but
don't have arch UPD structure, for example : JSL, TGL and Xeon-SP.
Out of these platforms, TGL supports calling of FspMultiPhaseSiInit
API and considered EnableMultiPhaseSiliconInit as a platform-specific
UPD rather than an arch UPD to allow calling into FspMultiPhaseSiInit
API.
It is important to ensure that the UPD setting and the callback for
MultiPhaseInit are kept in sync, else it could result in broken
behavior e.g. a hang is seen in FSP if EnableMultiPhaseSiliconInit
UPD is set to 1 but the FspMultiPhaseSiInit API call is skipped.
This patch provides an option for users to choose to bypass calling
into MultiPhaseSiInit API and ensures the EnableMultiPhaseSiliconInit
UPD is set to its default state as `disable` so that FSP-S don't
consider MultiPhaseSiInit API is a mandatory entry point prior to
calling other FSP API entry points.
List of changes:
1. Add `FSPS_HAS_ARCH_UPD` Kconfig for SoC to select if
`FSPS_ARCH_UPD` structure is part of `FSPS_UPD` structure.
2. Drop `soc_fsp_multi_phase_init_is_enable()` from JSL and Xeon-SP
SoCs, a SoC override to callout that SoC doesn't support calling
MultiPhase Si Init is no longer required.
3. Add `FSPS_USE_MULTI_PHASE_INIT` Kconfig for SoC to specify if
SoC users want to enable `EnableMultiPhaseSiliconInit` arch UPD (using
`fsp_fill_common_arch_params()`) and execute FspMultiPhaseSiInit() API.
4. Presently selects `FSPS_USE_MULTI_PHASE_INIT` from IA TCSS common
code.
5. Add `fsp_is_multi_phase_init_enabled()` that check applicability of
MultiPhase Si Init prior calling FspMultiPhaseSiInit() API to
honor SoC users' decision.
6. Drop `arch_silicon_init_params()` from SoC as FSP driver (FSP 2.2)
would check the applicability of MultiPhase Si Init prior calling
FspMultiPhaseSiInit() API.
Additionally, selects FSPS_HAS_ARCH_UPD for Alder Lake as Alder Lake
FSPS_UPD structure has `FSPS_ARCH_UPD` structure and drops
`arch_silicon_init_params()` from SoC
`platform_fsp_silicon_init_params_cb()`.
Skip EnableMultiPhaseSiliconInit hardcoding for Tiger Lake and uses
the fsp_is_multi_phase_init_enabled() function to override
EnableMultiPhaseSiliconInit UPD prior calling MultiPhaseSiInit FSP API.
TEST=EnableMultiPhaseSiliconInit UPD is getting set or reset based on
SoC user selects FSPS_USE_MULTI_PHASE_INIT Kconfig.
Change-Id: I019fa8364605f5061d56e2d80b20e1a91857c423
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch selects SOC_INTEL_COMMON_BLOCK_TCSS from Alder Lake SoC
Kconfig and drops SOC_INTEL_COMMON_BLOCK_TCSS Kconfig selection from
specific mainboard (brya) to ensure all Alder Lake mainboards can make
use of common TCSS block.
BUG=b:187385592
TEST=Type-C pendrive/Gen-2 SSD detected as Super speed.
Change-Id: I85f6a967eb34ea760418131a9586bfdeb13c9b5d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Commit 2eb100dd12 added PMC LPM requirements to the the PEP ACPI
objects, but it was not made clear that one of the pointer arguments to
the mentioned function is not supposed to be NULL and Coverity
complained. Make the intention clear by instead asserting that `info`
cannot be NULL.
Fixes: Coverity CID 1462119
Change-Id: I9e8862a100d92f4a7ed1826d3970a5110b47f4c4
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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copy existing QUP driver from /soc/qualcomm/sc7180 to common folder.
This QUP common driver provide QUP configurations, GPI and SE
firmware loading and initializations.
BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board.
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I95a0fcf97b3b3a6ed26e62b3084feb4a2369cdc9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Instead of always passing LB_FB_ORIENTATION_NORMAL, allow the chipsets
implementing the callback to pass in an orientation.
BUG=b:194967458
BRANCH=dedede
Change-Id: I4aacab9449930a75aca9d68bf30d019f86035405
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
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When the FSP driver fills out framebuffer information for the coreboot
tables, it assumes the orientation is always normal. This patch provides
a field for a mainboard to override the panel orientation from the
default (LB_FB_ORIENTATION_NORMAL). Later patches will have the FSP
driver use this value when filling out framebuffer information.
BUG=b:194967458
BRANCH=dedede
Change-Id: I559b3d6a076112a1c020ce5e296430d7ccba9ee4
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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Add igd device name in soc_acpi_name(), and src/drivers/gfx/generic
can generate device in GFX0 scope in ssdt.
BUG=b:198188272
TEST=emerge-brya coreboot and check ssdt.
Change-Id: Id0c50254a8a25b47368e932c99243f4f02250b82
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Fixes:
27c51a0 ("Revert "soc/intel/broadwell/pch: Replace ACPI device NVS"")
which reverted the removal of device NVS, but was not boot tested on any
Broadwell Chromebooks. It was recently discovered that the DNVS
object was not being loaded, due to a weak function setting the size
as zero not being defined for the platform/soc. Add the missing
overloaded function and required headers.
Test: build/boot google/auron variants LULU ans SAMUS, verify
touchpad functional and no ACPI errors in kernel boot log.
Change-Id: Icd317d117dbb068bb6da80fe56c06c0267c7b2ae
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
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Additionally, convert MAX_TYPE_C_PORTS from macro to enum value.
Change-Id: I3c596d8a015adc0449b44710c6d517753904ecd6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
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Due to CL:55000 modified MT53E1G32D2NP-046 WT:B settings
and CL:56597 add new memory in global_lp4x_mem_parts.json.txt,
update SPDs using gen_spd.go for JSL:
Modify:
1.MT53E1G32D2NP-046 WT:B(lp4x-spd-5.hex --> lp4x-spd-3.hex)
Add:
1.H54G46CYRBX267,lp4x-spd-1.hex
2.H54G56CYRBX247,lp4x-spd-3.hex
3.K4U6E3S4AB-MGCL,lp4x-spd-1.hex
4.K4UBE3D4AB-MGCL,lp4x-spd-3.hex
BUG=b:199032134
TEST=emerge-dedede coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I45b9275403fc4166fc56ae4c368c7a222141e150
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Intel TGL BIOS specification (doc ##611569) Revision 0.7.6 Section
7.2.5.1.5 recommends reserving the following resources for each PCIe
USB4 root port:
- 42 buses
- 194 MiB Non-prefetchable memory
- 448 MiB Prefetchable memory
This change enables reserving of resources for USB4 when mainboard
selects the newly added Kconfig SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES.
This is similar to the change for ADL in commit 8d11cdc6fa
("soc/intel/alderlake: Add Kconfig for recommended PCIe TBT resources").
Change-Id: I25ec3f74ebd5727fa4b13f5a3b11050f77ecb008
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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We use cpuid_eax to get the cpuid family.
BUG=b:179699789
TEST=build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib73e66241bb0cfd99a035c217c527338aa2d0e4d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
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Our MIPI panel initialization framework differentiates between DCS and
GENERIC commands, but the exact interpretation of those terms is left to
the platform drivers. In practice, the MIPI DSI transaction codes for
these are standardized and platforms always need to do the same
operation of combining the command length and transfer type into a
correct DSI protocol code. This patch factors out the various
platform-specific DSI protocol definitions into a single global one and
moves the transaction type calculation into the common panel framework.
The Qualcomm SC7180 implementation which previously only supported DCS
commands is enhanced to (hopefully? untested for now...) also support
GENERIC commands. While we're rewriting that whole section also fix some
other issues about how exactly long and short commands need to be passed
to that hardware which we identified in the meantime.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I09ade7857ca04e89d286cf538b1a5ebb1eeb8c04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
|
|
This patch adds new board type BOARD_TYPE_ULT_ULX_T4 and changes
BOARD_TYPE_SERVER value to 8.
BUG=b:199359579
BRANCH=None
TEST=Build and boot brya
Change-Id: I48eb0785a209499ee0d90bd541376d9bbacf2390
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
|
|
After switching to runtime generation of the Intel Power Engine (PEPD)
device, this file is no longer required.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I2444433f08bfda6f79589a397a2ad2b5a3ecb0ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
The pep.asl file is being obsoleted by runtime generation, therefore
switch skylake boards to this method.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I7c7cb424278946a9767ea329d18fb03d4e57dce8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
In order to get rid of pep.asl, skylake also needs to support runtime
generation of the Intel Power Engine, therefore add this support to
devices that have a discoverable PMC as well.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I4bf0c4a338301b335fa78617e0f2ed5a9f4360ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
The pep.asl file is being obsoleted by runtime generation, therefore
switch elkhartlake boards to this method.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I47f03b440729d4b37ae0abc84bd1d18c4e01657d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
The pep.asl file is being obsoleted by runtime generation, therefore
switch jasperlake boards to this method.
soc/intel/jasperlake: Switch to acpigen PEPD
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ib7f17f9b3b1396708ba68fa7a6d199d6e8b0ba11
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
The pep.asl file is being obsoleted by runtime generation, therefore
switch cannonlake boards to this method.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ic5343b0fd37eafac29a23846c8cfc3ca93d1821d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Now that the PMC device is marked as hidden in devicetrees, the device
callbacks can be used instead of BOOT_STATE_INIT_ENTRY callbacks.
Note that this moves PMC initialization from BS_DEV_INIT_CHIPS to
BS_DEV_ENUMERATE, which aligns with other Intel SoCs.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: If292728ad975ba803fed6abea879f6f634470a11
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
The pep.asl file is being obsoleted by runtime generation, therefore
switch tigerlake boards to this method.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I8e97c589273e934e89d69d8829680b9cac1ff9f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
The LPM enable mask is useful to have in more than one place, therefore
more the get_disable_mask() function and its helpers to lpm.c
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ibe83dc106f5f37baf9d5c64f68c47d85ea4e6dd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
The pep.asl file is being obsoleted by runtime generation, therefore
switch alderlake boards to this method.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I617bc3d1c3cf4ac6b6cbbd790dcf62e731024834
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
This patch adds support for the S0ix UUID in the Intel Power Engine _DSM
method. This allows the ACPI tables to expose device/IP power states
requirements for different system low power states
BUG=b:185437326
TEST=Along with following patch on brya0 after resume from s0ix,
cat /sys/kernel/debug/pmc_core/substate_requirements
Element | S0i2.0 | S0i3.0 | Status |
USB2PLL_OFF_STS | Required | Required | Yes |
PCIe/USB3.1_Gen2PLL_OFF_STS | Required | Required | Yes |
PCIe_Gen3PLL_OFF_STS | Required | Required | Yes |
OPIOPLL_OFF_STS | Required | Required | Yes |
OCPLL_OFF_STS | Required | Required | Yes |
MainPLL_OFF_STS | | Required | |
MIPIPLL_OFF_STS | Required | Required | Yes |
Fast_XTAL_Osc_OFF_STS | | Required | |
AC_Ring_Osc_OFF_STS | Required | Required | Yes |
SATAPLL_OFF_STS | Required | Required | Yes |
XTAL_USB2PLL_OFF_STS | | Required | Yes |
CSME_PG_STS | Required | Required | Yes |
SATA_PG_STS | Required | Required | Yes |
xHCI_PG_STS | Required | Required | Yes |
UFSX2_PG_STS | Required | Required | Yes |
OTG_PG_STS | Required | Required | Yes |
SPA_PG_STS | Required | Required | Yes |
SPB_PG_STS | Required | Required | Yes |
SPC_PG_STS | Required | Required | Yes |
THC0_PG_STS | Required | Required | Yes |
THC1_PG_STS | Required | Required | Yes |
GBETSN_PG_STS | Required | Required | Yes |
GBE_PG_STS | Required | Required | Yes |
LPSS_PG_STS | Required | Required | Yes |
ADSP_D3_STS | | Required | Yes |
xHCI0_D3_STS | Required | Required | Yes |
xDCI1_D3_STS | Required | Required | Yes |
IS_D3_STS | Required | Required | Yes |
GBE_TSN_D3_STS | Required | Required | Yes |
CPU_C10_REQ_STS_0 | Required | Required | Yes |
CNVI_REQ_STS_6 | | Required | Yes |
ISH_REQ_STS_7 | | Required | Yes |
MPHY_Core_DL_REQ_STS_16 | Required | Required | Yes |
Break-even_En_REQ_STS_17 | Required | Required | Yes |
Auto-demo_En_REQ_STS_18 | Required | Required | Yes |
Int_Timer_SS_Wake0_Pol_STS | Required | Required | |
Int_Timer_SS_Wake1_Pol_STS | Required | Required | |
Int_Timer_SS_Wake2_Pol_STS | Required | Required | |
Int_Timer_SS_Wake3_Pol_STS | Required | Required | |
Int_Timer_SS_Wake4_Pol_STS | Required | Required | |
Int_Timer_SS_Wake5_Pol_STS | Required | Required | |
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I542290bd5490aa6580a5ae2b266da3d78bc17e6b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56005
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
There is a use-case for generating the AML bytecode at runtime for the
Intel Power Engine device, which comes in a followup patch.
BUG=b:185437326
TEST=verified on google/brya and google/dratini by dumping SSDT and
verifying the PEPD device matches what was previously in the DSDT:
Scope (\_SB.PCI0)
{
Device (PEPD)
{
Name (_HID, "INT33A1")
Name (_CID, EisaId ("PNP0D80")
Method (_DSM, 4, Serialized)
{
ToBuffer (Arg0, Local0)
If ((Local0 == ToUUID ("c4eb40a0-6cd2-11e2-bcfd-0800200c9a66")))
{
ToInteger (Arg2, Local1)
If ((Local1 == Zero))
{
Return (Buffer (One)
{
0x63
})
}
If ((Local1 == One))
{
Return (Package (0x01)
{
Package (0x03)
{
\NULL,
Zero,
Package (0x02)
{
Zero,
Package (0x02)
{
0xFF,
Zero
}
}
}
})
}
If ((Local1 == 0x02)){}
If ((Local1 == 0x03)){}
If ((Local1 == 0x04)){}
If ((Local1 == 0x05))
{
If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX))
{
\_SB.PCI0.LPCB.EC0.S0IX (One)
}
If (CondRefOf (\_SB.MS0X))
{
\_SB.MS0X (One)
}
If (CondRefOf (\_SB.PCI0.EGPM))
{
\_SB.PCI0.EGPM ()
}
}
If ((Local1 == 0x06))
{
If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX))
{
\_SB.PCI0.LPCB.EC0.S0IX (Zero)
}
If (CondRefOf (\_SB.MS0X))
{
\_SB.MS0X (Zero)
}
If (CondRefOf (\_SB.PCI0.RGPM))
{
\_SB.PCI0.RGPM ()
}
}
Return (Buffer (One)
{
0x00
})
}
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie83722e0ed5792e338fc5c39a57eef43b7464e3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Use the get_supported_lpm_states() function to set the respective FSP
UPD.
TEST=with patchtrain on brya0,
/sys/kernel/debug/pmc_core/substate_requirements shows only the
substates that are applicable to the design (S0i2.0, S0i3.0).
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I5bb8b3671e78c5f2706db2d3a21b25cf90a14275
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
This function searches the known MCH device IDs for Alder Lake and
returns the appropriate enum value representing ADL-P, ADL-M, ADL-S, or
unknown.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I26354b340e0c5f15ba246c1cb831d7feaf62d2ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
This reverts commit b90e6fdd25f7fcc9db6be50a0b117a7509c6fdb1. Latest
releases of PSP does not load PSP verstage on S0i3 resume. Hence no need
to skip PSP verstage on S0i3 resume.
BUG=b:196400450
TEST=Build and boot to OS in Guybrush. Trigger a suspend/resume cycle
and then a reboot and ensure that the system boots to OS.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Iaeb92edb69662e6c06f4d0e3d7b760d4597bf650
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Add the pin definitions for the remote GPIOs and the GPIO pin mux values
for the GPIO mode of those pins. For now, accessing the remote GPIOs is
only supported from the native coreboot code running on the x86 cores
and not from verstage on PSP or ACPI.
BUG=b:194524995
TEST=On Majolica with a Cezanne APU configuring GPIO 262 as output and
then toggling that GPIO in an infinite loop in the mainboard's bootblock
code results in GPIO 262 toggling as expected.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0e57042e74da88503b36d6065e9500876287f8bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Right now the ACPI code doesn't support accessing the remote GPIO block
yet, so don't generate invalid remote GPIO access functions and warn
about those being unsupported.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id364a59c9650bf4e3633b494b01ab23c0bbc50b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
|
|
Some AMD SoCs have a 5th GPIO bank, the remote GPIO bank, which isn't
located right after the 4th GPIO bank, but instead at a different
location inside the APCIMMIO region. A difference to the first 4 GPIO
banks is that the corresponding GPIO MUX registers aren't in a separate
bank, but at the end of the remote GPIO region. So this remote GPIO
region only supports 48 GPIOs with a 32 bit configuration register each
and has the 8 bit GPIO MUX registers beginning at offset 0xc0 in the
remote GPIO region.
For now using the remote GPIOs from verstage on PSP isn't supported. To
support this, it would need to map acpimmio_remote_gpio and update the
pointer like it already does for acpimmio_gpio0, acpimmio_iomux and a
few others.
BUG=b:194524995
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic8d7ff677a99381a5558782b80b0c4cae67602db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Default VBOOT_HASH_BLOCK_SIZE is 1 KiB and increasing it to 4 KiB
helps in improving overall boot time since it reduces hashing and
body loading time.
Increasing it over 4 KiB doesn't result in significant improvement,
thus keeping the value at 4 KiB as of now.
Timing data:
Note that before Data is with 1 KiB block size.
|------------------------------------------------------|
| Stage | Block Size | Before | After |
|finished loading body| 4 KiB | 205,187 | 189,947 |
|finished loading body| 8 KiB | 205,187 | 188,708 |
|finished loading body| 16 KiB | 205,187 | 188,085 |
|finished loading body| 32 KiB | 205,187 | 187,793 |
|------------------------------------------------------|
BUG=b:188577893
BRANCH=None
TEST=Boot time for Brya improves by 20 - 25 msec
Change-Id: I9222761c7d58e4a370d3a41c651b6c169599d792
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
This change sets Irms config in FSP if TdcTimeWindow and TdcCurrentLimit
is set to non zero. It results VR TDC Input current to be treated as it
is root mean square.
This change also optimizes the check of TdcTimeWindow and TdcCurrentLimit
for TdcEnable UPD.
BRANCH=None
TEST=Build and boot brya with debug FSP and verify Irms UPD value
from logs
Change-Id: Ice5c775ef9560503109957a1ed994af1d287aafc
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
|
|
This is already done in drivers/intel/fsp2_0/Makefile.inc.
Change-Id: Idfd15d0a9d2cb15e613881f80bb25c18bd7454bb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Change-Id: I7e575cb17e2004bd931f4fa1d05f17c4cdca29ba
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
From ACPI specification, version 6.2 Errata A:
A `duty_width` value of 0 indicates that processor duty cycle is not
supported and the processor continuously runs at its base frequency.
Because Broadwell sets `duty_width` to 0, processor duty cycle is not
supported, and the value of `duty_offset` is ignored. For consistency
with Lynx Point, set `duty_offset` to 0.
Change-Id: I68cb85ec32a6cceda0cea29d76df6c6219b78a40
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
|
Currently coreboot for the AMD SOCs only supports accessing the up to 4
main GPIO banks of up to 64 GPIOs each. Some AMD SoCs including Cezanne
have another GPIO bank in the ACPIMMIO region that can contain up to 48
GPIOs beginning with GPIO 256 which is called the remote GPIO bank. The
first 48 DWORDs of that ACPIMMIO bank are the 32 bit wide GPIO registers
and beginning at offset 0xc0 it has the corresponding 8 bit wide GPIO
MUX registers.
BUG=b:194524995
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ice4e3358de17ac2601621814978cdb70e6f2c926
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Add and use the I2C_RESET_SCL_PIN macro for populating the i2c_scl_pins
array that is used for the sb_reset_i2c_peripherals call to bring the
I2C buses into a defined state.
TEST=Timeless build results in identical image for Mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifedc09d0bf745545fa0510df7d5037f02b9012a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Coverity detects dereference pointers req and res that are NULL when
calling the pmc_send_ipc_cmd function. This change prevents NULL
pointers dereference.
Found-by: Coverity CID 1458068, 1458070, 1458971, 1458073, 1458075,
1458076
TEST=None
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ib88fa5f44dd33ad1ad2e763d79438b5c5b78acb4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Setting the usb_phy version and length in the soc code instead of devicetree.
That way the devicetree code does not have to reapeat it for different
AMD Cezanne based systems.
Tested on guybrush by changing phy settings in devicetree and then checking
the usb phy register.
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: I2db49e095672054b9b15042fb003a93b67e3a4c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
The code under `cpu/x86/tsc` is only compiled in when its `Makefile.inc`
is included from platform (CPU/SoC) code and the `UDELAY_TSC` Kconfig
option is enabled.
Include `cpu/x86/tsc/Makefile.inc` once from `cpu/x86/Makefile.inc` and
drop the now-redundant inclusions from platform code. Also, deduplicate
the `UDELAY_TSC` guards.
Change-Id: I41e96026f37f19de954fd5985b92a08cb97876c1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57456
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Allow to select the primary graphics device between the IGD and the
external PCIe GPU depending on the ONBOARD_VGA_IS_PRIMARY config.
The option sets the priority only. This means that if a high priority
is set for an external PCI device and it is not connected/not enabled,
then the device with a lower priority will be used, in our case it is
IGD.
TEST = Set PRIMARY_PCI and boot Linux on the Kontron mAL10 [1] with
the miniPCIe video adapter on the Silicon Motion SM750 controller. As
a result, the display connected to an external GPU device shows the
Tianocore logo + setup menu and the desktop.
[1] https://review.coreboot.org/c/coreboot/+/39133
Change-Id: Idcd117217cf412ee0722aff52db4b3c8ec2a226c
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
|
|
The eventlog requires RTC to provide correct timestamps, so we have to
turn on the config and add the common drivers.
BUG=b:199003609
TEST=check timestamp in 'mosys eventlog list'
BRANCH=none
Signed-off-by: Chen-Tsung Hsieh <chentsung@chromium.org>
Change-Id: Ia382cd023fcbfdf2c1efeb7b32c0b99feb71effa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
1. Disable external output reset signal in first WDT reset
to preserve WDT original reset reason for WDT issue in kernel stage.
2. After preserved WDT reset reason, do fully reset again by sending
external output reset signal.
BUG=b:194025005
TEST=boot to kernel ok and function test pass
Signed-off-by: Fengquan Chen <fengquan.chen@mediatek.corp-partner.google.com>
Change-Id: I5887a8312f4daab3cbd0a30fea0195670a932e52
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
Suggested-by: Martin Roth <martinroth@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0016a6c7d6581cb261cab6178268c1a86b89c839
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56831
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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