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2023-03-29soc/amd/stoneyridge/acpi: add C state config tableFelix Held
The C state ACPI packages binaryPI generates and passes to coreboot in the PSTATE SSDT only include the C2 state, but the kernel will add the C1 state to its usable C states in this case. The native C state code will generate both the C1 and C2 state packages to be more complete and also to be more in line with the other AMD SoCs. The code added in this commit isn't used yet, but will be used as soon as Stoneyridge will be using the common AMD generate_cpu_entries by selecting SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE once all needed helper functions are implemented for Stoneyridge. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I06f90306ac196704e0102d0da6eab03f51513c29 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-29soc/amd/common/block/cpu/Kconfig: drop FAM17H_19H suffix from TSC optionFelix Held
The SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H option is valid for all SoCs with Zen-based CPU cores including the family 1Ah, so remove the suffix. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I58d29e69a44b7b97fa5cfeb0e461531b926f7480 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-29soc/amd/common/block/cpu/tsc_freq: move static variable inside functionFelix Held
Move the static mhz variable inside the only function that is accessing it. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ief98c0a1c35fe1bbc4ff38dd175f12e0b3ddc515 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-29soc/amd/common/block/cpu/tsc/tsc_freq: use get_pstate_core_freqFelix Held
Use get_pstate_core_freq instead of open-coding the calculations in tsc_freq_mhz. In the case of the CPU frequency divider being 0, get_pstate_core_freq will return 0; in this case that shouldn't happen, TSC_DEFAULT_FREQ_MHZ will be used as frequency, since for the TSC frequency it's better to err on the end of the expected frequency being too high which will cause longer than expected delays instead of too short delays. Now that the code is using get_pstate_core_freq, this code is valid for Glinda too, so also remove the comment on the SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H option being selected in the Glinda Kconfig. This Kconfig option will be renamed in a follow-up patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I01168834d4018c92f44782eda0c65b1aa392030d Reviewed-on: https://review.coreboot.org/c/coreboot/+/74013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-29soc/amd/stoneyridge/tsc_freq: use get_pstate_core_freqFelix Held
Use get_pstate_core_freq instead of open-coding the calculations in tsc_freq_mhz. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If5d526e6b365c62a6669241f4fcdd25eca3f15fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/74012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-29soc/amd/common/cpu/tsc: add get_pstate_core_freq for family 15h and 16hFelix Held
This function will be used in follow-up patches for both the TSC rate calculation and the still to be implemented P state ACPI table generation in coreboot. The was checked against BKDG 52740 Rev 3.05, BKDG #55072 Rev 3.04, and BKDG #50742 Rev 3.08. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9afaa044da994d330c3e546b774eb1f82e4f30e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-29soc/amd/common/cpu/tsc: factor out family-specific get_pstate_core_freqFelix Held
Factor out the get_pstate_core_freq function from the SoC's acpi.c files to both avoid duplication and to also be able to use the same function in the TSC frequency calculation in a follow-up patch. The family 17h and 19h SoCs use the same frequency encoding in the P state MSRs while the family 1Ah SoCs use a different encoding. The family 15h and 16h SoCs use another encoding, but since this isn't implemented in Stoneyridge's acpi.c, this will be added in a follow-up patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8619822c2c61e06ae5db86896d5323c9b105b25b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-29soc/amd/stoneyridge/monotonic_time: add comment that we can't use TSCFelix Held
Due to a non-constant TSC rate before the microcode update is applied, the Performance Time Stamp Counter is used instead. To clarify this, add a comment to the timestamp_get implementation. See commit 24079323d4d8 ("soc/amd/stoneyridge: provide alternate monotonic timer") and the description of the TscInvariant bit in CPUID Fn8000_0007_EDX Advanced Power Management Information in the public version of BKDG #55072 Rev 3.09 for more details. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I824b372c36fa6f3eb912469b235a9474f6a58ff5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-29soc/amd/mendocino: Add FSP parameter for eDP power sequence adjustmentChris.Wang
Add UPD parameter for eDP power sequence adjust. The pwr_on_vary_bl_to_blon is set one unit per 4ms. BUG=b:271704149 TEST=Build; Verify the UPD was pass to system integrated table; measure the power on sequence on whiterun Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I25c9f962e70f599c780259f0943a03f8aa7cbfd1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2023-03-29soc/intel/common: Add Intel Trace Hub driverPratikkumar Prajapati
From Meteor Lake onwards Intel FSP will generate the Trace Hub related HOB if the Trace Hub is configured to save data in DRAM. This memory region is used by Trace Hub to store the traces for debugging purpose. This driver locates the HOB and marks the memory region reserved so that OS does not use it. Intel Trace Hub developer manual can be found via document #671536 on Intel's website. Change-Id: Ie5a348071b6c6a35e8be3efd1b2b658a991aed0e Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-03-29soc/intel/cmn/crashlog: Add check for zero based SRAM BARSubrata Banik
This patch adds a check for zero based SRAM base address. It will help to avoid running into problems if the SRAM is disabled and the base address register is zero. TEST=Able to build and boot google/marasov with PCH SRAM being disabled. Change-Id: Iebc9dc0d0851d5f83115f966bf3c7aad1eb6bc01 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-28soc/amd/stoneyridge/graphics: introduce defines for constantsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2021a106e0d3a603b1a05296411700ffea32fc8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/74042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-28soc/amd/stoneyridge: move map_oprom_vendev to graphics.cFelix Held
Move map_oprom_vendev to graphics.c to match the other AMD SoCs. Also change the comment style to be more in line with the rest of coreboot and drop the unneeded line break in the printk call. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icc1f3d73fba973413c5a22e2f5ae01bc58bc3e76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-28soc/amd/stoneyridge/Kconfig: use correct VGA_BIOS_IDFelix Held
Fix the VGA_BIOS_ID IDs to match the PCI IDs in the VBIOS binaries and the PCI ID Stoneyidge's map_oprom_vendev returns. This fixes the problem that the display wasn't initialized due to not finding the VBIOS file in CBFS. This bug in the Stoneyridge Kconfig was unmasked by commit 42f0396a1028 ("device/pci_rom: rework PCI ID remapping in pci_rom_probe"). TEST=Display in Careena lights up again. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4d1e6a3a65d7d7b07f49df9ce90620b79d9a2d78 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74019 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-28soc/intel/xeon_sp: Use simple device function for setting PMAX_LOCKJonathan Zhang
Change to use simple device function for setting PMAX_LOCK because the Sapphire Rapids PCU device is not scanned during coreboot PCIe bus scan and would see "PCI: dev is NULL!" failure. Change-Id: I3156a6adf874b324b5f4ff5857c40002220e47ab Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72400 Reviewed-by: Simon Chou <simonchou@supermicro.com.tw> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-27soc/amd/stoneyridge/Kconfig: select SOC_AMD_COMMON_BLOCK_SVI2Felix Held
Stoneyridge uses the serial voltage ID 2 standard to tell the VRM on the board which voltage it wants, so select the SOC_AMD_COMMON_BLOCK_SVI2 Kconfig option to have the corresponding code to decode the raw SVI2 value into a voltage. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7d7031d9ad997a86c18d0e9e7af9a88ddf2d873c Reviewed-on: https://review.coreboot.org/c/coreboot/+/73999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-27soc/amd/common/block/cpu/Makefile: group build targets by stageFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idb6087dc44e76ab63bc6b462c3328c23d83ae018 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74009 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-27soc/amd/common/block/cpu/svi2: drop unneeded core_vid checkFelix Held
A core voltage ID larger than 0xff shouldn't happen, since SVI2's core VID is only 8 bit long. In order for making it more difficult to use this function in a wrong way that results in a very wrong voltage being returned, also return 0 for those invalid core VID values. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I95417c45db86cd2373879cdad8a07fb9eb8dfdda Reviewed-on: https://review.coreboot.org/c/coreboot/+/74000 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-27soc/amd/mendocino: Add UPD to support USB3 force to gen1 by portPatrick Huang
Add UPD usb3_port_force_gen1 to support USB3 port force to gen1 BUG=b:273841155 BRANCH=skyrim TEST=Build, verify USB3 port setting to gen1. Change-Id: Iaa476f56cf10588d7de2203deca4122958c00783 Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-03-27soc/amd/stoneyridge/include/msr: add pstate_msr bitfield structFelix Held
Add the pstate_msr union of a bitfield struct and a raw uint64_t to allow easier access of the bitfields of the P state MSRs which will be used in future patches to generate the P state ACPI packages for the CPU objects. BKDG #55072 Rev 3.04 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I944c8598ba95a0333124655c61ef9eba8a7595c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73998 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-27soc/amd: factor out common get_pstate_core_power implementationFelix Held
Now that all get_pstate_core_power implementations in each SoC's acpi.c file is identical, factor it out into a common implementation. This implementation will also work for Stoneyridge which isn't using the common P state code yet. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iba3833024a5e3ca5a47ffb1c1afdbfd884313c96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73997 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-27soc/amd: introduce and use get_pstate_core_uvolts for SVI2 and SVI3Felix Held
Since SVI3 has the CPU voltage ID split into two parts, a serial voltage ID version specific function is needed to get the raw core VID value. This will allow making get_pstate_core_power common for all AMD CPUs in a follow-up patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I71ca88c38b307558905a26cce8be1e8ffc5fbed4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73996 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-27soc/amd: introduce and use get_uvolts_from_vid for SVI2 and SVI3Felix Held
Instead of implementing the conversion from the raw serial voltage ID value to the voltage in microvolts in every SoC, introduce the SOC_AMD_COMMON_BLOCK_SVI[2,3] Kconfig options for the SoC to select the correct version, implement get_uvolts_from_vid for both cases and only include the selected implementation in the build. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I344641217e6e4654fd281d434b88e346e0482f57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73995 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-26soc/intel: Move USB PORTSC definition into IA common codeSubrata Banik
This patch moves USB Port Status and Control (PORTSC) Reg definition into IA common code to allow other SoC code to reuse it without redefining the same for each SoC. TEST=Able to build and boot google/taeko where USB wake is working. Change-Id: I6b540eab282403c7a6038916f5982aa26bd631f8 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-25soc/intel/xeon_sp/chip_common.c: Probe all buses in attach_iio_stacks()Jonathan Zhang
For some Xeon-SP (such as SPR-SP), more buses should be probed. Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: Ica3c61493a0ff6c699b500f30788b2cf5a06c250 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-03-25soc/intel/xeon_sp/uncore_acpi.c: Add SPR-SP supportTim Chu
Add support for Intel SPR-SP to uncore_acpi.c. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Signed-off-by: Shelly Chang <Shelly_Chang@wiwynn.com> Change-Id: I4c436a60743bee21b3b6e4060d7874a6cdc75ecf Reviewed-on: https://review.coreboot.org/c/coreboot/+/71958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-25soc/amd/common/include/cppc: remove cppc_config forward declarationFelix Held
The included acpi/acpigen.h provides the cppc_config struct and nothing in this header file is using the cppc_config struct. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia91fd4105e6872d812f595447783d02a0dd1568b Reviewed-on: https://review.coreboot.org/c/coreboot/+/73993 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-25soc/amd/common/include/cppc: rename include guardFelix Held
When the code was made common in commit 8f7f4bf87a23 ("soc/amd/cezanne, common: factor out CPPC code to common AMD SoC code"), the include guard wasn't renamed accordingly, so do that now. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9eefe2065fae31e97aa4e6710008a6f9712bed40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73992 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-24soc/amd/*/include/msr: add version number to SERIAL_VID_* define namesFelix Held
Picasso and Cezanne use the serial voltage ID 2 standard to communicate the CPU voltage to the voltage regulator module on the mainboard, while Mendocino, Phoenix and Glinda use the serial voltage ID 3 standard for this. Both standards encode the voltage in a different way, so add the serial VID version number to the defines to clarify for which version the define is. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8ddab8df27c86dc2c70a6dfb47908d9405d86240 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73994 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-03-24soc/amd/mendocino: add and use missing cpu_vid_8 pstate_msr fieldFelix Held
Mendocino uses the SVI3 standard for CPU core voltage control which uses 9 data bits instead of the 8 in the SVI2 case and also calculates the actual voltages with a different formula. The Mendocino code uses the correct formula since commit 8d2bfbce23f6 ("soc/amd/sabrina/acpi: Correct VID decoding on Sabrina"), but the MSR definition in the PPR hasn't been updated to show the additional bit. The definition of the register that is mirrored by these MSRs descries this 9th CPU voltage ID bit though. Since this bit is expected to be zero, this shouldn't cause a change in behavior. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I05acd239300836a34e40cd3f31ea819b79766e2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/73969 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-03-24soc/intel/xeon_sp/smihandler.c: enable support for spr-spTim Chu
For SPR-SP, the SMM_FEATURE_CONTROL register is in UBOX_URACU_FUNC instead of UBOX_DEV_PMON. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: Ide46c5f9cdf65b7e05552449b08ad4d7246664cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/71962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-24soc/amd/*/include/msr: drop _LO part from PSTATE definition namesFelix Held
The _LO part in the definition names is a leftover from before moving to the pstate_msr union access to the bitfield elements where it still mattered if a bit was in the lower of higher half of the MSR. With the mask-and-shift access to the two parts of the MSR being gone, the _LO part in the name isn't useful any more and possibly a bit misleading, so drop that part. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib43c71e946388c944ecf40659d4c12ca02a27a5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/73927 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-24soc/amd: pass pstate_msr union to get_pstate_core_[freq,power]Felix Held
Since we already have and use the pstate_msr union in get_pstate_info, also pass it directly to the get_pstate_core_freq and get_pstate_core_power function calls avoids having to sort-of convert the msr_t type parameter in the implementations of those two functions. In amdblocks/cpu.h a forward declaration of the pstate_msr union is used since soc/msr.h doesn't exist in the two pre-Zen SoCs that also include amdblocks/cpu.h. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I112030a15211587ccdc949807d1a1d552fe662b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73926 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-23soc/amd/common/block/acpi/cpu_power_state: use pstate_msr unionFelix Held
Use the pstate_msr union in get_pstate_info to check if the P state enable bit is set. Also drop the now unused PSTATE_DEF_HI_ENABLE_SHIFT and PSTATE_DEF_HI_ENABLE_MASK definitions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I79119e09af79a4bb680a18e93b4a61a049f0080e Reviewed-on: https://review.coreboot.org/c/coreboot/+/73925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-03-23soc/amd/glinda: introduce and use pstate_msr bitfield structFelix Held
Add the pstate_msr union of a bitfield struct and a raw uint64_t to allow easier access of the bitfields of the P state MSRs which will be implemented in a following patch. PPR #57254 Rev 1.52 was used as a reference. This patch adds and uses the cpu_vid_8 bit which is the 9th bit of the voltage ID specified in the SVI3 spec. The way the CPU frequency is encoded in the PSTATE MSR has changed compared to Phoenix, so also update the comment in the SoC's Kconfig file that the selected SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H is likely incompatible which will be addressed in the future. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3d1878ce4d9bc62ac597e6f71ef9630491628698 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-23soc/amd/phoenix: introduce and use pstate_msr bitfield structFelix Held
Add the pstate_msr union of a bitfield struct and a raw uint64_t to allow easier access of the bitfields of the P state MSRs and use this bitfield struct in get_pstate_core_freq and get_pstate_core_power. The signature of those two function will be changed in a follow-up commit. PPR #57019 Rev 1.65 and PPR #57396 Rev 1.54 were used as a reference as well as the reference code. This patch also adds and uses the cpu_vid_8 bit which is the 9th bit of the voltage ID specified in the SVI3 spec. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia024d32ae75cf2ffbc2a2e86a8b3af3dc6cbad61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-03-23soc/intel/xeon_sp: Report platform cpu infoNaresh Solanki
Add platform cpu info for known microcode, print cpuid & processor branding string. This will print as in the following example: CPU: Intel(R) Xeon(R) Platinum 8468H CPU: ID 806f6, Sapphire Rapids E3, ucode: 2b000130 CPU: AES supported, TXT supported, VT supported Change-Id: I9c08fb924aad81608f554523432ab6a549b1b75f Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-03-23soc/intel/xeon_sp: Fix PCH IOAPIC IDPatrick Rudolph
FSP may program a different ID under certain circumstances. Read IOAPIC ID from hardware instead of using some define that might not reflect how hardware is configured. Change-Id: Ia91cb4aef9d15520b8b3402ec10e7b0a4355caeb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-23soc/intel/cmn/cse: Make heci_(send|receive) public functionsJeremy Compostella
Having these two functions public allow "asynchronous" HECI command implementation. Typically, these function can be use to implement an asynchronous End-Of-Post. BUG=b:268546941 BRANCH=firmware-brya-14505.B TEST=Successful compilation for brya0 Change-Id: I7d029bb9af4b53f219018e459d17df9c1bd33fc1 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-03-23soc/amd/mendocino: Remove GPP bridge to Bus BMartin Roth
The internal GPP bridge to bus B is not used on MDN, so remove it. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I4f95afd192c5b799b7a3e12650476b7933cdd118 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-23soc/intel/elkhartlake: Define DIMM_SPD_SIZE in SoC KconfigMichał Żygowski
The default SPD size is set to 256 bytes, instead of 512 for LPDDR4/DDR4 if not overridden by the mainboard Kconfig. This caused the SMBus libraries to read only the lower half of the DIMM SPD on protectli/vault_ehl. The lower half of the SPD passed to FSP causes a bug in DIMM change detection, which relies on the CRC of the manufacturer bytes in the upper half of the SPD (CRC of zero bytes always gives zero so no change was assumed). Setting the DIMM SPD size to 512 fixes it. Setting the SPD size in SoC will also avoid such problems in the future Elkhart Lake ports. Elkhart Lake supports only LPDDR4/DDR4 so providing the correct default of 512 bytes is an obvious thing to do. TEST=Boot Protectli VP2420 (vault_ehl) with different DIMMs and see FSP is retraining the memory instead of doing the fastboot with old DIMM data. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I998ed8781951034419cadc26c04ff1e0a124b267 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73933 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-23soc/intel: Rename IA common code module from `TOM` to `RAMTOP`Subrata Banik
This patch renames all references of `top_of_ram` (TOM) in IA common `basecode` module (for example: functions, variables, Kconfig, Makefile and comments) with `ramtop` aka top_of_ram to make it more meaningful and to avoid conflicts with Intel SA chipset TOM registers. BUG=Able to build and boot google/rex with the same ~49ms savings in place. Change-Id: Icfe6300a8e4c5761064537fb256cfecbe2afb2d8 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73881 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-23intel/common/block/smm: remove return statements from void functionsYuchen He
To be consistent with other occurrences in soc/intel/common, remove the return statements of weak void funtions since they are not generally useful. Found by the linter. Signed-off-by: Yuchen He <yuchenhe126@gmail.com> Change-Id: I3fb8217cfcae65b5dc317458b59aa431f1ccdaef Reviewed-on: https://review.coreboot.org/c/coreboot/+/73866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-22soc/amd/*/acpi: assign proper boolean values in get_pstate_core_freqFelix Held
Assign true/false instead of 1/0 to the valid_freq_divisor bool variable in get_pstate_core_freq. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I92d0eb029c55f80a2027ff6d404c63ed84282750 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-22soc/intel/xeon_sp/uncore.c: Add CXL memory into memory mapJonathan Zhang
If the host supports CXL, get proximity domain info from FSP HOB. The proximity domains may include both processor domains and CXL domains. Add header definition for proximity domain. Add CXL memory into memory map. Change-Id: If3f856958a3e6ed3909240ee455bb639e487087f Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-22soc/intel/xeon_sp/uncore.c: skip configuring VTD devJonathan Zhang
DPR should not be configured for VTD devices of other stacks for SPR-SP. Such processor(s) would be configured with SOC_INTEL_MMAPVTD_ONLY_FOR_DPR. Change-Id: Ib33b1b62f59a10d362c6585b1403490d4a1aedeb Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: David Hendricks <ddaveh@amazon.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72616 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-22soc/intel/xeon_sp/uncore.c: Add NCMEM base/limit to map entriesJonathan Zhang
... instead of ME base/limit if the processor is configured with SOC_INTEL_HAS_NCMEM. Change-Id: I95783cad1a2d5a3599d120ea0c98e2aa8703bdb4 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: David Hendricks <ddaveh@amazon.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72615 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-22soc/intel/xeon_sp/spr: Add soc set_cmos_mrc_cold_boot_flagJohnny Lin
This soc utility function can set cmos flag to enforce FSP MRC training. Change-Id: I88004cbfdcbe8870726493576dfc31de4b6036a9 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-22soc/intel/xeon_sp: Enable FSP_ERROR_INFO_HOB handlingTim Chu
After calling FSP MemoryInit API, if there is an error, some FSPs (such as SPR-SP FSP) is capable of generating FSP_ERROR_INFO_HOB. Check existence of such a HOB and handle it accordingly. Change-Id: Icb5c31daa223ba6b06ba1b2de4f8808e0b27899e Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-22soc/intel/elkhartlake: Increase BSP stack size by 1 KiB to 193 KiBMichał Żygowski
The Kconfig help section says FSP uses 192 KiB of stack (0x30000) and coreboot's romstage requires ~1 KiB, but it is not satisfied currently. Increase the BSP stack size by the missing 1KiB for romstage like other SoCs do. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Iddd4a4613bc174aec4331732371a27450225258c Reviewed-on: https://review.coreboot.org/c/coreboot/+/73820 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-21soc/intel/xeon_sp/spr/cpu: add missing device_match_mask in CPU tableFelix Held
Commit 6a6ac1e0b929 ("arch/x86/cpu: introduce and use device_match_mask") added the device_match_mask element to the cpu_device_id struct and uses it to be able to mask off for example the stepping ID when checking for CPU table entry that matches the silicon the code is running on. Commit 3ed903fda9cb ("soc/intel/xeon_sp/spr: Add Sapphire Rapids ramstage code") added a CPU table that was missing the device_match_mask which results in this being 0, so the first entry of the CPU table would match for any Intel CPU which isn't the intended behavior. Also use CPU_TABLE_END instead of the final {0, 0, 0} array element. Likely all entries could be replaced by one entry that uses the CPUID_ALL_STEPPINGS_MASK instead of the CPUID_EXACT_MATCH_MASK, but that's out of scope for this fix. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib0be2e9fe3c31487c83c9b1cf305a985416760b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-21soc/intel/apl: Fix programming temporary MTRR on GLKArthur Heymans
Programming MTRR happens later in the CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT codepath. fast_spi_cache_bios_region() assumes an existing MTRR solution from x86_setup_mtrrs_with_detect(). This fixes a problem introduced by 829e8e6 "soc/intel: Use common codeflow for MP init". Change-Id: I9b6130cf76317440ebe7a7a53e460e2b658d198e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73836 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-21soc/amd/mendocino: Remove 2 unused PCIe functionsMartin Roth
Mendocino only has 4 PCIe lanes exposed, so there's no need for 6 PCIe functions to control them. These functions just show up as leftover devicetree devices. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I5b801d82f085d77706b8053a8fc9728101f155e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73853 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-03-21soc/intel/common/block/acpi: Support more than 255 coresPatrick Rudolph
Replace the legacy ACPI Processor() object as it only supports 8bit IDs and thus no more than 255 cores. Use the new ACPI Device() object that supports more than 255 cores. Test: - Observed no ACPI errors on IBM/SBP1 and Linux 5.15 running 384 CPU cores in total. - Verified on Intel ADL RVP with 20 cores that Linux 5.15 is still working without errors. Change-Id: I309c06b6824704c84fd16534655334a6f269904a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73578 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-03-21soc/intel/elkhartlake: Make PCIe root port speed limit configurableMario Scheithauer
In cases where there are limitations on the connected device behind the PCIe root port it can be necessary to limit the speed. The FSP parameter 'PcieRpPcieSpeed' allows to set the speed limit. This patch provides a chip config so that this FSP parameter can be set as needed in the devicetree on mainboard level. Change-Id: I9fc24de1682279e4ae4c090147a6ef7995b441bc Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-03-21soc/intel/alderlake/vr_config: Add i3-1220PEPatrick Rudolph
Add the AlderLake-P 4+4+2 (28W) with MCH_ID 0x4629 to the vr_config table. Change-Id: I606ef429f47dfe386177f7257b153acc1611bb61 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-03-20soc/amd/mendocino: introduce and use pstate_msr bitfield structFelix Held
Add the pstate_msr union of a bitfield struct and a raw uint64_t to allow easier access of the bitfields of the P state MSRs and use this bitfield struct in get_pstate_core_freq and get_pstate_core_power. The signature of those two function will be changed in a follow-up commit. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic489b8e1332dde2511647c065ccbdef541bcbcc5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-20soc/amd/cezanne: introduce and use pstate_msr bitfield structFelix Held
Add the pstate_msr union of a bitfield struct and a raw uint64_t to allow easier access of the bitfields of the P state MSRs and use this bitfield struct in get_pstate_core_freq and get_pstate_core_power. The signature of those two function will be changed in a follow-up commit. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If92a4773c669ac2df45396eee52f6de780adbdca Reviewed-on: https://review.coreboot.org/c/coreboot/+/73644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-20soc/amd/picasso: introduce and use pstate_msr bitfield structFelix Held
Add the pstate_msr union of a bitfield struct and a raw uint64_t to allow easier access of the bitfields of the P state MSRs and use this bitfield struct in get_pstate_core_freq and get_pstate_core_power. The signature of those two function will be changed in a follow-up commit. TEST=The coreboot-generated SSDT containing the P state packages stays identical on Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8dc293351f9941cfb8a9c84d9fb9a4fd76361d5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/73643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-20soc/intel/meteorlake: Enable GPIO IOSTANDBY configurationSubrata Banik
Enable SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY so the pads can be configured with non-zero IOSSTATE values. TEST=Able to build and boot google/rex. GPIO debug print is showing GPIO PAD config DW1 bit[14:17] are getting programmed. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9e63fe946d541769fa0ddbb23f902f9c905735c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-20soc/amd/mendocino: Consume fsp misc_data hobJason Glenesk
Provide support function to query fsp misc_data hob and return smu reported power and thermal limit. BUG=b:253301653 TEST=Use get_amd_smu_reported_tdp(&tdp) values match what FSP placed in the hob. Change-Id: I9f0d8cdd616726c5a714e99504b83b0126dd273b Signed-off-by: Jason Glenesk <jason.glenesk@amd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73747 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-19soc/intel/xeon_sp/Makefile.inc: Build EBG for SPR-SPTim Chu
Intel SPR-SP chipset has EBG instead of LBG. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: I9429fe332bb5f01a41aa205c76ad9f0159f93eee Reviewed-on: https://review.coreboot.org/c/coreboot/+/71959 Reviewed-by: Jian-Ming Wang <jianmingW@supermicro.com> Reviewed-by: TimLiu-SMCI <timliu@supermicro.com.tw> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-19soc/intel/xeon_sp/spr: Add Sapphire Rapids ramstage codeJonathan Zhang
It implements SPR ramstage including silicon initialization, MSR programming, MP init and certain registers locking before booting to payload. Change-Id: I128fdc6e58c49fb5abf911d6ffa91e7411f6d1e2 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-19soc/intel/xeon_sp/spr: Add header files and romstage codeJonathan Zhang
Several FSP HOBs processing codes are similar to Intel Cooperlake-SP codes in soc/intel/xeon_sp/cpx. Register datasheet please reference Sapphire Rapids EDS Vol2 Doc#612246 and Emmitsburg PCH EDS Doc#606161. Change-Id: Ia022534e5206dbeec946d3e5f3c66bcb5628748f Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-19soc/intel/mtl: Choose serial msg `log_level` based on DIMM countSubrata Banik
This patch modifies the serial msg log_level at runtime to highlight an ERROR if the DIMM count is zero. It would help to draw the attention while parsing the serial msg and catch any underlying issue. TEST=Able to see ERROR msg while booting google/rex with FSP v3064 Without this patch: [DEBUG] 0 DIMMs found With this patch:     [ERROR]  No DIMMs found Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iacf41efecb4962f91cf322bbc50636dc44033e3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/73756 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-19soc/intel/xeon_sp: add MSR definitions for SPR-SPDavid Hendricks
Some MSRs used in SPR code are common among currently supported Xeon-SP generations and are added to the top-level Xeon-SP msr.h. MSRs which have changed are added to SPR's soc_msr.h. Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: David Hendricks <ddaveh@amazon.com> Change-Id: I92b433a9686734716dc7936895fb79c7751f7f9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/73172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-03-19soc/intel/xeon_sp: Split SKX/CPX MSRs into separate headersJonathan Zhang
Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: David Hendricks <ddaveh@amazon.com> Change-Id: I2ecfebdde453a48b7b0e6f21b3c4394411eed671 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-03-19soc/intel/xeon_sp: Add P2SB definition for SPR-SPJonathan Zhang
Change-Id: I2ece7aac4339266068d4fc8fb1c58d0573eb2895 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Simon Chou <simonchou@supermicro.com.tw> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-03-17soc/intel/alderlake: Hook the VT-d DMA protection optionMichał Żygowski
TEST=Enable DMA protection on MSI PRO Z690-A DDR4 and observe the I/O devices like USB and NVMe fail to enumerate in UEFI Payload (basically proving that DMA protection works). Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Iecaa3d04f1447b7e73507ca57a0d23d42e24d663 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68450 Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-17soc/intel/alderlake/hsphy.c: Handle case with DMA protectionMichał Żygowski
The HSPHY firmware must be downloaded to DMA-allowed host address space. Check for DMA buffer presence and use it as the buffer for HSPHY firmware to be downloaded from CSME. TEST=Successfully load HSPHY firmware to CPU on MSI PRO Z690-A DDR4 with DMA protection enabled. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I88edda26a027b557eeaba80426a5b7be7199507d Reviewed-on: https://review.coreboot.org/c/coreboot/+/68556 Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-17soc/intel/alderlake: Select SOC_INTEL_COMMON_BLOCK_VTDMichał Żygowski
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I226305fa547e9d9ea541a5806d543aa358bce28d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72069 Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-17intelblocks/vtd: Add VT-d block with DMA protection APIMichał Żygowski
Add new common block with VT-d/IOMMU support. The patch adds an option to enable DMA protection with PMR. However the payload and OS must support VT-d in order to properly handle I/O devices. TEST=Enable DMA protection on MSI PRO Z690-A DDR4 and observe the I/O devices like USB and NVMe fail to enumerate in UEFI Payload (basically proving that DMA protection works). Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Id7edf982457c1139624e5cd383788eda41d6a948 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
2023-03-17qualcomm/common: Pass FMAX_LIMIT flag for Lazor board to QcLibSudheer Kumar Amrabadi
This patch passes a hint flag to QcLib on Lazor boards to tell it to limit the DDR frequency for certain memory parts (8GB Hynix) to work around a board-specific stability issue. BRANCH=trogdor BUG=b:267387867 TEST=Validated on qualcomm sc7180 development board Change-Id: I45915cf93d2a57ff0c9710f2ac36dfb665eff1c6 Signed-off-by: Sudheer Kumar Amrabadi <samrabad@codeaurora.org> Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2023-03-15soc/intel/xeon_sp: Rename nb_acpi.c to uncore_acpi.cJohnny Lin
With newer xeon_sp processors, the concept of "north bridge" became obsolete, instead uncore should be used. Therefore we use uncore_acpi.c (instead of nb_acpi.c) going forward. Change-Id: I91ec9023152996bf9f2300a369aff3c4f19d75fd Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-03-15soc/amd/mendocino: MP2 firmware isn't needed in the RO imageMartin Roth
The MP2 firmware doesn't do anything useful when booting into recovery mode, so don't include it in the RO image if vboot is enabled. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I5afbf7e9e730e6951c416f3a3ca75f69a22099cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/73660 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-15soc/amd: Print amdfwtool debug info if V=1Martin Roth
When doing coreboot builds, we can set V=1 to see all of the make info printed as the compile is happening. Use this flag to set the debug flag for amdfwtool so it doesn't have to be enabled separately. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I5b05cbc9f9b540a174db479822af657cf35733de Reviewed-on: https://review.coreboot.org/c/coreboot/+/73658 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-03-15soc/amd/common: Ignore * in PSP dependency generationMartin Roth
The regex getting rid of lines containing a '*' didn't match anything in any configs, so get rid of it. There's nothing in the amdfwtool dataparse.c file that would match it either. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I05aaf46cfb479cebab9234a47574073335984a5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/73669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-15soc/amd/common: Update PSP dependency generationMartin Roth
After adding the ability to add paths into the amdfw.cfg file for the amdfwtool, the dependency generation needs to be updated to not add the firmware location in front of those values. This also allows us to filter out the MP2 binaries as dependencies based on whether or not the Kconfig value is set. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I3a9b9c8246808dc60020a32a7d9d926bc5e57ccd Reviewed-on: https://review.coreboot.org/c/coreboot/+/73657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-15soc/intel/tigerlake: Select `X86_CLFLUSH_CAR` configLean Sheng Tan
This patch selects `X86_CLFLUSH_CAR` config for running `clflush` to invalidate the cache region based on commit 3134a81 for boot performance improvement. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I97c8c07db9b44aa89b433e7962ec77c8501ecaa9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-15soc/intel/elkhartlake: Select `X86_CLFLUSH_CAR` configLean Sheng Tan
This patch selects `X86_CLFLUSH_CAR` config for running `clflush` to invalidate the cache region based on commit 3134a81 for boot performance improvement. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I8f8a0bfeaea508d3b4ad1b3fe2e68742cbab5570 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73687 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-15soc/intel/coffeelake: Select `X86_CLFLUSH_CAR` configLean Sheng Tan
This patch selects `X86_CLFLUSH_CAR` config for running `clflush` to invalidate the cache region based on commit 3134a81 for boot performance improvement. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Icd3d16ab2cb34dc81fc12ec139c52ecaa170528d Reviewed-on: https://review.coreboot.org/c/coreboot/+/73686 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-15soc/intel/alderlake: Select `X86_CLFLUSH_CAR` configLean Sheng Tan
This patch selects `X86_CLFLUSH_CAR` config for running `clflush` to invalidate the cache region based on commit 3134a81 for boot performance improvement. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I1fe6072a3c23a02c9a691406f179bfc8f0f18a93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-15soc/mediatek/mt8186: Shut down PMIC on power key long pressSen Chu
Currently on power key long press, PMIC will be reset. It would cause an unwanted reset pulse in the power-off sequence. To match expected sequence, change PMIC behavior to "force shutdown". BUG=b:271771606 TEST=long-pressing power key doesn't trigger PMIC_AP_RST_L pulse BRANCH=corsola Change-Id: I9ab35d82e57f43bac99fa8bd7bb69fcf52250311 Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com> Signed-off-by: jason-ch chen <jason-ch.chen@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73705 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-15soc/mediatek/mt8188: Shut down PMIC on power key long pressSen Chu
Currently on power key long press, PMIC will be reset. It would cause an unwanted reset pulse in the power-off sequence. To match expected sequence, change PMIC behavior to "force shutdown". BUG=b:271771606 TEST=long-pressing power key doesn't trigger PMIC_AP_RST_L pulse Change-Id: I1626892fd582dfab8fe1c1ede1da00549bc97142 Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com> Signed-off-by: jason-ch chen <jason-ch.chen@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73704 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-13soc/intel/meteorlake: Enable early caching of TOM regionSubrata Banik
Intel Meteor Lake decides to enable early caching of the TOM region to optimize the boot time by selecting `SOC_INTEL_COMMON_BASECODE_TOM` config. TEST=Able to build and boot google/rex to ChromeOS and reduce the boot time by 77 ms. Without this patch: 950:calling FspMemoryInit 936,811 (19,941) 951:returning from FspMemoryInit 1,041,935 (105,123) With this patch: 950:calling FspMemoryInit 905,108 (20,103) 951:returning from FspMemoryInit 964,038 (59,929) Change-Id: Iebb3485b052386b43d5bccd67a04e6115cbcc20d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73274 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-13soc/intel/cmn/sa: Store TOM into the CMOSSubrata Banik
This patch uses the IA common code API to store the top_of_ram (TOM) address intonon-volatile space (CMOS). The code logic will update the TOM address in CMOS NVS if the `top_of_ram` address is calculated differently in any boot and also takes care of caching the updated range. TEST=Able to build and boot google/rex to ChromeOS. First boot: Before calling into FSP-M [DEBUG]  0x00000000fef00006: PHYBASE0: Address = 0x00000000fef00000, WB [DEBUG]  0x00003ffffff80800: PHYMASK0: Length  = 0x0000000000080000, Valid [DEBUG]  0x00000000fef80006: PHYBASE1: Address = 0x00000000fef80000, WB [DEBUG]  0x00003ffffffc0800: PHYMASK1: Length  = 0x0000000000040000, Valid [DEBUG]  0x00000000ff000005: PHYBASE2: Address = 0x00000000ff000000, WP [DEBUG]  0x00003fffff000800: PHYMASK2: Length  = 0x0000000001000000, Valid [DEBUG]  0x00000000f9800005: PHYBASE3: Address = 0x00000000f9800000, WP [DEBUG]  0x00003fffff800800: PHYMASK3: Length  = 0x0000000000800000, Valid ... [DEBUG] tom_table invalid signature [DEBUG]  top_of_ram = 0x76000000 [DEBUG] Updated the TOM address into CMOS 0x76000000 On consecutive boot:Before calling into FSP-M: The TOM region is already cached. [DEBUG]  0x00000000fef00006: PHYBASE0: Address = 0x00000000fef00000, WB [DEBUG]  0x00003ffffff80800: PHYMASK0: Length  = 0x0000000000080000, Valid [DEBUG]  0x00000000fef80006: PHYBASE1: Address = 0x00000000fef80000, WB [DEBUG]  0x00003ffffffc0800: PHYMASK1: Length  = 0x0000000000040000, Valid [DEBUG]  0x00000000ff000005: PHYBASE2: Address = 0x00000000ff000000, WP [DEBUG]  0x00003fffff000800: PHYMASK2: Length  = 0x0000000001000000, Valid [DEBUG]  0x00000000f9800005: PHYBASE3: Address = 0x00000000f9800000, WP [DEBUG]  0x00003fffff800800: PHYMASK3: Length  = 0x0000000000800000, Valid [DEBUG]  0x0000000075000005: PHYBASE4: Address = 0x0000000075000000, WP [DEBUG]  0x00003fffff000800: PHYMASK4: Length  = 0x0000000001000000, Valid Change-Id: I2569495570652c488096f6a29f58dd8f0103af9d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73273 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-13soc/intel/cmn/tom: Cache TOM region earlySubrata Banik
This patch implements a module that can store the top_of_ram (TOM) address into non-volatile space (CMOS) during the first boot and use it across all consecutive boot. As top_of_ram address is not known until FSP-M has exited, it results into lacking of MTRR programming to cache the 16 MB TOM, hence accessing that range during FSP-M and/or late romstage causing long access times. Purpose of this driver code is to cache the TOM (with a fixed size of 16MB) for all consecutive boots even before calling into the FSP. Otherwise, this range remains un-cached until postcar boot stage updates the MTRR programming. FSP-M and late romstage uses this uncached TOM range for various purposes (like relocating services between SPI mapped cached memory to DRAM based uncache memory) hence having the ability to cache this range beforehand would help to optimize the boot time (more than 50ms as applicable). TEST=Able to build and boot google/rex to ChromeOS. Without this patch: 950:calling FspMemoryInit               936,811 (19,941)   951:returning from FspMemoryInit        1,041,935 (105,123) With this patch:  950:calling FspMemoryInit               905,108 (20,103)   951:returning from FspMemoryInit        987,038 (81,929) Change-Id: I29d3e1df91c6057280bdf7fb6a4a356db31a408f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73272 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-13soc/amd/phoenix/mca.c: Remove excess MCA bank namesFred Reitberger
Documentation and hardware differ in the number of MCA bank names, so remove the excess ones to prevent a "CPU has an unexpected number of MCA banks!" warning message. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I75a2348561833f3f19181b4f30a6971ecb317899 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-03-13soc/amd/common/block/cpu/update_microcode: use raw MSR dataFelix Held
Since mst_t is a union of the struct containing the lower and higher 32 bits and the raw 64 bit value, the address of the microcode update can be directly written to the raw value instead of needing to split it into the lower and higher 32 bits and assigning those separately. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I51c84164e81477040a4b7810552d3d65c0e3656b Reviewed-on: https://review.coreboot.org/c/coreboot/+/73636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-13soc/amd/common/block/cpu/noncar/write_resume_eip: use raw MSR dataFelix Held
Since mst_t is a union of the struct containing the lower and higher 32 bits and the raw 64 bit value, the address of the bootblock_resume_entry can be directly written to the raw value instead of needing to split it into the lower and higher 32 bits and assigning those separately. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I7ebab1784ec592e18c29001b1cf3ee7790615bf8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-13soc/intel/meteorlake: Select `X86_CLFLUSH_CAR` configSubrata Banik
This patch selects `X86_CLFLUSH_CAR` config for running `clflush` to invalidate the cache region. TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6b2dce39f82e28cd99ad8621c78bae494c4f16ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/73333 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-10soc/amd/common/psp: Put spl_fuse in separate compilation unitMartin Roth
This separates the SPL fusing function into a separate C file which can be excluded if it is not needed. This allows the psp_set_spl_fuse() function to be made static again as the state of the function will always match the boot_state entry. Move the required #defines to the common header file so they can be used by both psp_gen2.c & spl_fuse.c. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ifbc774a370dd35a5c1e82f271816e8a036745ad5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73655 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-10soc/amd/common/cpu/smm/smm_relocate: don't assume TSEG is below 4GBFelix Held
Even though right now TSEG will always be located below 4GB, better not make assumptions in the SMM relocation code. Instead of clearing the higher 32 bits and just assigning the TSEG base and per-core SMM base to the lower 32 bits of the MSR, assign those two base addresses to the raw 64 bit MSR value to not truncate the base addresses. Since TSEG will realistically never be larger than 4GB and it needs to be aligned to its power-of-two size, the TSEG mask still only needs to affect the lower half of the corresponding MSR value. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1004b5e05a7dba83b76b93b3e7152aef7db58f4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/73639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-03-10soc/amd/common/block/psp/psp_smm: use raw MSR dataFelix Held
Since mst_t is a union of the struct containing the lower and higher 32 bits and the raw 64 bit value, there's no need to convert the lower and higher 32 bits into a 64 bit value and we can just use the 64 bit raw value. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5923df84f0eb3a28ba6eda4a06c7421f4459e560 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-03-10soc/amd/stoneyridge/monotonic_timer: use raw MSR dataFelix Held
Since mst_t is a union of the struct containing the lower and higher 32 bits and the raw 64 bit value, there's no need to convert the lower and higher 32 bits into a 64 bit value and we can just use the 64 bit raw value. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibc5d64c74eaabfc4b7834a34410b48f590f78a12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-03-10xeon_sp: Setup x2apic in SRATNaresh Solanki
Set up SRAT table in X2APIC mode when necessary. Change-Id: Ib8b4cebefe81f7b5514524dba2fa364eee4bb157 Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-10amdfwtool: Add HW IPCFG file whose subprog is 1Zheng Bao
And rename PSP_HW_IPCFG_FILE to PSP_HW_IPCFG_FILE_SUB0 Change-Id: Ia1ab8482074105de367905be2b4b0418066823d2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-10soc/mediatek/mt8188: Enable lastbus debug hardwareot_zhenguo.li
Lastbus is a bus debug tool. When the bus hangs, the bus transmission information before resetting will be recorded. The watchdog cannot clear it and it will be printed out for bus hanging analysis. There are two versions for lastbus: Version 1 for MT8186, and version 2 for MT8188. BUG=b:263753374 TEST=build pass. Change-Id: Ibaf510481d1941376bd8da0168ef17c99a0fb9a2 Signed-off-by: ot_zhenguo.li <ot_zhenguo.li@mediatek.corp-partner.google.com> Signed-off-by: jason-ch chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73624 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-03-10src/soc/amd/phoenix/include/soc/: Update the Data Fabric ID for PhoenixAnand Vaikar
Change-Id: I078b57825377f97f9f5f2b607fa134e3a67e9685 Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: ritul guru <ritul.bits@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-09soc/amd/common/cpu: move get_threads_per_core from noncar to common codeFelix Held
The get_threads_per_core function isn't specific to the non-CAR CPUs and also applies for Stoneyridge and even for family 16h model 30h outside of soc/amd, so move it from the non-CAR-specific cpu.c file to the common AMD SoC cpu.c file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I05946f163112ff93f33139f6c43fed5820fd0a3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/73615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-16 01:50:07 +0000