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authorLean Sheng Tan <sheng.tan@9elements.com>2023-03-13 14:51:10 +0100
committerLean Sheng Tan <sheng.tan@9elements.com>2023-03-15 14:25:12 +0000
commit86152453499c8eee7044078411aa0495eef72a38 (patch)
tree679e5474e8af0dee5aebcafc96cdb0e221e4ce05 /src/soc
parent0e5f51e186ea1a88618db85e0e1bb98c233afcf1 (diff)
soc/intel/alderlake: Select `X86_CLFLUSH_CAR` config
This patch selects `X86_CLFLUSH_CAR` config for running `clflush` to invalidate the cache region based on commit 3134a81 for boot performance improvement. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I1fe6072a3c23a02c9a691406f179bfc8f0f18a93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/alderlake/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index ae5f7a79db..09cd75de18 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -131,6 +131,7 @@ config CPU_SPECIFIC_OPTIONS
select UDELAY_TSC
select UDK_202005_BINDING
select VBOOT_LIB
+ select X86_CLFLUSH_CAR
config SOC_INTEL_ALDERLAKE_TCSS_USB4_SUPPORT
bool