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authorFelix Held <felix-coreboot@felixheld.de>2023-03-24 17:41:05 +0100
committerFelix Held <felix-coreboot@felixheld.de>2023-03-29 16:15:59 +0000
commitad52185c2dab095cbf65f3d55976f47363d5672e (patch)
treeb7491c8d661b33b1142db024adee26c49817d897 /src/soc
parent96fd62f239a7922800d892fed064a941b91ccfce (diff)
soc/amd/stoneyridge/tsc_freq: use get_pstate_core_freq
Use get_pstate_core_freq instead of open-coding the calculations in tsc_freq_mhz. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If5d526e6b365c62a6669241f4fcdd25eca3f15fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/74012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/amd/stoneyridge/tsc_freq.c15
1 files changed, 6 insertions, 9 deletions
diff --git a/src/soc/amd/stoneyridge/tsc_freq.c b/src/soc/amd/stoneyridge/tsc_freq.c
index 0be93aa571..e676fb1ec4 100644
--- a/src/soc/amd/stoneyridge/tsc_freq.c
+++ b/src/soc/amd/stoneyridge/tsc_freq.c
@@ -1,17 +1,17 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <amdblocks/cpu.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/msr.h>
#include <cpu/x86/tsc.h>
#include <console/console.h>
#include <soc/pci_devs.h>
+#include <soc/msr.h>
#include <device/pci_ops.h>
unsigned long tsc_freq_mhz(void)
{
- msr_t msr;
- uint8_t cpufid;
- uint8_t cpudid;
+ union pstate_msr pstate_reg;
uint8_t boost_states;
/*
@@ -23,12 +23,9 @@ unsigned long tsc_freq_mhz(void)
boost_states = (pci_read_config32(SOC_PM_DEV, CORE_PERF_BOOST_CTRL)
>> 2) & 0x7;
- msr = rdmsr(PSTATE_MSR(boost_states));
- if (!(msr.hi & 0x80000000))
+ pstate_reg.raw = rdmsr(PSTATE_MSR(boost_states)).raw;
+ if (!pstate_reg.pstate_en)
die("Unknown error: cannot determine P-state 0\n");
- cpufid = (msr.lo & 0x3f);
- cpudid = (msr.lo & 0x1c0) >> 6;
-
- return (100 * (cpufid + 0x10)) / (0x01 << cpudid);
+ return get_pstate_core_freq(pstate_reg);
}