soc/amd/stoneyridge/acpi: add C state config table

The C state ACPI packages binaryPI generates and passes to coreboot in
the PSTATE SSDT only include the C2 state, but the kernel will add the
C1 state to its usable C states in this case. The native C state code
will generate both the C1 and C2 state packages to be more complete and
also to be more in line with the other AMD SoCs.

The code added in this commit isn't used yet, but will be used as soon
as Stoneyridge will be using the common AMD generate_cpu_entries by
selecting SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE once all needed
helper functions are implemented for Stoneyridge.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I06f90306ac196704e0102d0da6eab03f51513c29
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>

1 files changed, 19 insertions, 0 deletions

diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c
index d60faafa43..1a264f5a4f 100644
--- a/src/soc/amd/stoneyridge/acpi.c
+++ b/src/soc/amd/stoneyridge/acpi.c
@@ -93,6 +93,25 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 				ACPI_FADT_REMOTE_POWER_ON;
 }
 
+const acpi_cstate_t cstate_cfg_table[] = {
+	[0] = {
+		.ctype = 1,
+		.latency = 1,
+		.power = 0,
+	},
+	[1] = {
+		.ctype = 2,
+		.latency = 400,
+		.power = 0,
+	},
+};
+
+const acpi_cstate_t *get_cstate_config_data(size_t *size)
+{
+	*size = ARRAY_SIZE(cstate_cfg_table);
+	return cstate_cfg_table;
+}
+
 void generate_cpu_entries(const struct device *device)
 {
 	int cpu;