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2024-11-07soc/intel/alderlake: select Kconfig MRC_CACHE_USING_MRC_VERSIONRonak Kanabar
This patch introduces support for storing the MRC cache based on the MRC version for RPL platforms. This patch selects the MRC_CACHE_USING_MRC_VERSION option when client SOC_INTEL_RAPTORLAKE is chosen. BUG=b:281846937 TEST=Able to build and boot google/brox and verify MRC version in CBMEM. Change-Id: I8adf519c7f27b30d69c19f1c37cf410ac8ae54db Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-11-07soc/intel/xeon_sp: Add acpigen_write_PRT_pre_routedLu, Pen-ChunX
acpigen_write_PRT_pre_routed writes _PRT covering all direct subordinate child devices based on interrupt line/pin info from their PCI configuration spaces. It is required that IRQ routing and PCI configuration space update to be done ahead of time. TEST=Build and boot on intel/archercity CRB Change-Id: Ic54888f76d2ec9804442bec5aec54267d9a16d7c Signed-off-by: Lu, Pen-ChunX <pen-chunx.lu@intel.com> Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82253 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-11-06soc/intel/alderlake: Fix uninitialized usb_cfg pointerKarthikeyan Ramasubramanian
This patch addresses uninitialized usb_cfg pointer warning which is also an error - src/soc/intel/alderlake/fsp_params.c:936:48: error: 'usb_cfg' may be used uninitialized in this function [-Werror=maybe-uninitialized] BUG=None TEST=./util/abuild/abuild Change-Id: I764fed561dfe2a571f3404fe505997edd7aa5ff7 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84939 Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-06soc/intel/alderlake: select UDK_202305_BINDING for RPLRonak Kanabar
RPL FSP v5311 uses 202305 Edk2. Select UDK_202305_BINDING Kconfig for RPL SoC. BUG=b:281846937 TEST=Able to build and boot google/brox. Change-Id: I8dcc7d85cddadcce148ded5a81658253e8598413 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84722 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jayvik Desai <jayvik@google.com>
2024-11-06soc/intel/jasperlake: add support for RP LTR mechanismLawrence Chang
Reserve Root Port LTR mechanism in FSP, in case some devices need to optimize LTR. BUG=366383364 TEST=Tested on Awasuki with RTL8852BE use lspci -xxx to get PCIE config space dump, and LTR Mechanism Enable bit is offset 68h[10]. 00:1c.0 PCI bridge: Intel Corporation Device 4dbf (rev 01) 00: 86 80 bf 4d 07 05 10 00 01 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 00 01 01 00 20 20 00 20 20: c0 7f c0 7f f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 04 12 00 40: 10 80 42 01 00 80 00 00 00 00 10 00 13 4c 72 08 50: 43 00 11 70 00 b2 3c 00 00 00 40 01 08 00 00 00 60: 00 00 00 00 37 08 00 00 00 04 00 00 0e 00 00 00 70: 03 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 05 90 01 00 38 02 e0 fe 00 00 00 00 00 00 00 00 90: 0d a0 00 00 86 80 bf 4d 00 00 00 00 00 00 00 00 a0: 01 00 03 c8 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 01 10 00 07 42 18 01 40 08 00 9e 09 00 00 00 00 e0: 00 03 e3 00 00 00 00 00 16 00 10 00 00 00 00 00 f0: 50 01 00 00 00 00 00 4c b5 0f 02 01 04 00 00 84 Change-Id: I85e50b01cc9fb5522d457cfce3700b7c85d7012f Signed-off-by: Lawrence Chang <lawrence.chang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84866 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: David Ruth <druth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-06soc/intel/meteorlake: Remove SOC_INTEL_GFX_MBUS_JOIN configSubrata Banik
This patch removes the SOC_INTEL_GFX_MBUS_JOIN configuration option. Support for fast modeset joining has been added to the mainline i915 kernel driver (https://patchwork.freedesktop.org/series/130480/), making this coreboot-specific workaround unnecessary. BUG=b:291885733 TEST=Successful build and boot of google/screebo with single and dual displays, no redundant boot splash. Change-Id: Ifb0416df53a453ce16815f9fd52ec6b53fade5e2 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81034 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Paz Zcharya <pazz@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-05soc/intel/alderlake: Disable UFS controllers only on S5 resumeSubrata Banik
Disable UFS controllers during romstage initialization only when resuming from S5 (full power off). On warm reboot, the UFS controllers are already disabled by the previous boot cycle, so disabling them again is unnecessary. TEST=Able to ensure UFS controller is already disabled in warm reboot path and not causing any problem during S0ix cycle test. Change-Id: Ia27d2156a002cef032d5f57d212cf4eb520b3bdf Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jayvik Desai <jayvik@google.com>
2024-11-05soc/intel/meteorlake: Disable eSOL for Ovis/DekuSubrata Banik
Disable the `FSP_UGOP_EARLY_SIGN_OF_LIFE` option (eSOL) for the Ovis baseboard. eSOL currently only supports display output over eDP and HDMI. Ovis/Deku exclusively use Type-C for display, and eSOL cannot render output over Type-C during early boot because it depends on Type-C firmware loaded in a later stage. TEST=Able to build and boot google/deku. Change-Id: I5ddbd340f667b1631a42d130a793f0b1831aa0ba Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-11-03soc/intel/alderlake: Do lazy reset after disabling UFSKarthikeyan Ramasubramanian
If the mainboard expects upcoming reset, then skip the reset after disabling UFS. This will reduce the number of resets during firmware update. BUG=b:375444631 TEST=Build Brox BIOS image and boot to OS. Perform a firmware update and confirm that the number of reset is reduced by 2 resets. Change-Id: I4399555302ec23a76f89f406f437f311eea0ef99 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84935 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-10-30soc/intel/pantherlake: Populate and pass DRAM info for SMBIOSSubrata Banik
This patch implements the `save_dimm_info()` API to populate and pass DRAM-related information to the next stage. This information is used to generate the SMBIOS memory table, providing details about installed DIMMs. This addresses the issue where SMBIOS lacked detailed DIMM information. Verified that `dmidecode` correctly dumps the DIMM information from the SMBIOS table after this change. BUG=b:376103463 TEST=Built and booted successfully. Verified DIMM info in SMBIOS using `dmidecode`. > dmidecode -t 17 ``` Getting SMBIOS data from sysfs. SMBIOS 3.0 present. Handle 0x000B, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2 GB Form Factor: Row Of Chips Set: None Locator: Channel-0-DIMM-0 Bank Locator: BANK 0 Type: LPDDR5 Type Detail: Unknown Synchronous Speed: 6400 MT/s Manufacturer: Hynix Serial Number: 00000000 Asset Tag: Channel-0-DIMM-0-AssetTag Part Number: H58G56BK7BX068 Rank: 1 Configured Memory Speed: 6400 MT/s Minimum Voltage: 0.5 V Maximum Voltage: 0.5 V Configured Voltage: 0.5 V ... ... Handle 0x0012, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2 GB Form Factor: Row Of Chips Set: None Locator: Channel-3-DIMM-0 Bank Locator: BANK 0 Type: LPDDR5 Type Detail: Unknown Synchronous Speed: 6400 MT/s Manufacturer: Hynix Serial Number: 00000000 Asset Tag: Channel-3-DIMM-0-AssetTag Part Number: H58G56BK7BX068 Rank: 1 Configured Memory Speed: 6400 MT/s Minimum Voltage: 0.5 V Maximum Voltage: 0.5 V Configured Voltage: 0.5 V ``` Change-Id: I3b942610272de401589ee0463de9cd0985974774 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-10-30soc/intel/pantherlake: Add ACPI names for missing devicesSubrata Banik
This patch adds ACPI names for the following devices: - THC0 (PCI: 00:10.0) - THC1 (PCI: 00:10.1) - SRAM (PCI: 00:14.2) - FSPI (PCI: 00:1f.5) TEST=Able to build and boot google/fatcat without any error. w/o this patch: [ERROR] Missing ACPI Name for PCI: 00:10.0 [ERROR] Missing ACPI Name for PCI: 00:10.1 [ERROR] Missing ACPI Name for PCI: 00:14.2 [ERROR] Missing ACPI Name for PCI: 00:1f.5 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I474089607522a4bd13375cc34b8f8645ca3663d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84910 Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-10-30soc/intel/pantherlake: Set SMBUS device ACPI min sleep state as D0Subrata Banik
This change sets the SMBUS device to min sleep state D0 in the ACPI sleep state table. TEST=Able to build and boot google/fatcat. w/o this patch: [WARN ] Unknown min d_state for PCI: 00:1f.4 w/ this patch: No Error or Warning. Change-Id: If84d2ee8abfef34f6411e01e6c37d4e2008a3666 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84909 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-29tree: Fix cast an object of type 'nullptr_t' to 'uintptr_t' errorElyes Haouas
This to fix the error when using C23: cannot cast an object of type 'nullptr_t' to 'uintptr_t' (aka 'unsigned long') return (uintptr_t)NULL; ^ Change-Id: Ibdc8794513a508fc61a5046692f854183c36b781 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-10-28uncore_acpi: Clean up resource codePatrick Rudolph
Use the resource size to determine Vtd BAR size and drop the code to calculate the Vtd BAR size. While on it do not truncate the resource address to 32-bit, since the DMAR entry is 64-bit wide anyway. TEST: Booted on intel/archercity_crb Change-Id: Ibaadc25c44345ba2eb9e6f75989d32b43d00d7a5 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-10-28soc/intel/xeon_sp: Fix iiostack.aslPatrick Rudolph
Align DSDT names with SSDT naming scheme, as provided by iio_domain_set_acpi_name() and hide unused devices by implementing the _STA method as done on newer platforms. Change-Id: I8488907f28a78a6f71046dba54ba9cbd4b0652eb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-10-28soc/intel/xeon_sp: Add SAD PCI driverPatrick Rudolph
Get rid of some helper functions by properly using a pci_driver. Configure SAD if necessary and lock SAD if necessary in the newly added SAD PCI driver. This allows to drop lock_pam0123(), unlock_pam_regions() and socket0_get_ubox_busno(). - Fixes SAD instance on secondary sockets not decoding the C-F segments as DRAM, which would prevent those sockets to access the ACPI/SMBIOS table anchor - Adds PCI multi segment support (SKX and CPX only, other were working properly already) - Moves locking of PAM0123_CSR and PAM456_CSR from SoC to driver code Change-Id: I167b6ce48631fe3f97359ee33704f52ca854dbd1 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84794 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-27soc/intel/skylake/Makefile: Remove dead codeFelix Singer
This code is never reached since the hardware uses different SoCs. Besides, mainboard specific code should not be added to SoC code. Change-Id: Id82d5d0b829442c35c093974c06a029259838a9a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-10-26soc/intel/cmn/fast_spi: Improve debug message for SPI flash windowsSubrata Banik
This commit improves the debug messages when initializing SPI flash windows by adding the window type (Fixed Decode or Extended Decode) to the log output. This makes it easier to understand which window is being initialized and can help with debugging issues related to SPI flash access. w/o this patch: [INFO ] MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000 [INFO ] MMAP window: SPI flash base=0x900000, Host base=0xf9900000, Size=0x700000 w/ this patch: [INFO ] Fixed Decode Window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000 [INFO ] Extended Decode Window: SPI flash base=0x900000, Host base=0xf9900000, Size=0x700000 Change-Id: I904f70f42fa70ea06e6f49bd44631a8491463207 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Pranava Y N <pranavayn@google.com>
2024-10-24soc/intel/common: Add PCIe device IDs for Snow RidgeYuchi Chen
This patch adds SPI and some accelerator device IDs for SNR platform. IDs are from Intel Atom Processor C5100, C5300, P5300 and P5700 Product Families EDS, doc No. 575160 rev 2.0. Change-Id: I7bd135d788816e4c3c42ac937450cf8cdcea00bc Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84782 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-23soc/intel/broadwell; Use boolean for pch_is_wpt_xxElyes Haouas
Use boolean for pch_is_wpt() and pch_is_wpt_ulx(). Change-Id: Ifd1a46ebdbe08df6cc21ada100b94930b02cd7de Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: coreboot org <coreboot.org@gmail.com>
2024-10-23device/pciexp: Add hot-plug capable helper functionPatrick Rudolph
Add and use a new helper function to determine if a device is 1) a PCIe device 2) it's mark hot-plug capable Change-Id: I61cc013844024b43808cd2f054310cb6676ba69e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-10-23soc/intel/xeon_sp: Report PCIe integrated end points under DRHDJincheng Li
In case of a PCH-less platform, no DRHD_INCLUDE_PCI_ALL flags are used, all PCIe integrated end points should be explicitly listed under the DRHD they are affiliated to. Otherwise, the device MSI setting could fail. TESTED = Build and boot on intel/beechnutcity CRB In CentOS Stream (5.14.0-479.el9.x86_64) 9 5.14.0-479.el9.x86_64, without the changes, below failure logs will occur, [ 6.908347] ------------[ cut here ]------------ [ 6.908353] WARNING: CPU: 0 PID: 8 at drivers/pci/msi/msi.h:121 pci_msi_setup_msi_irqs+0x27/0x40 [ 6.908374] Modules linked in: [ 6.908379] CPU: 0 PID: 8 Comm: kworker/0:0 Not tainted 5.14.0-479.el9.x86_64 #1 [ 6.908385] Hardware name: Intel Beechnut City CRB/Beechnut City CRB, BIOS c1e9362c93be-dirty 09/25/2024 [ 6.908389] Workqueue: events work_for_cpu_fn [ 6.908401] RIP: 0010:pci_msi_setup_msi_irqs+0x27/0x40 [ 6.908411] Code: 90 90 90 0f 1f 44 00 00 48 8b 87 00 03 00 00 89 f2 48 85 c0 74 14 f6 40 28 01 74 0e 48 81 c7 c8 00 00 00 31 f6 e9 19 de ac ff <0f> 0b b8 ed ff ff ff c3 cc cc cc cc 66 66 2e 0f 1f 84 00 00 00 00 [ 6.908417] RSP: 0000:ffffac47c0137c80 EFLAGS: 00010246 [ 6.908423] RAX: 0000000000000000 RBX: ffff9a0a874e2000 RCX: 000000000000009c [ 6.908428] RDX: 0000000000000001 RSI: 0000000000000001 RDI: ffff9a0a874e2000 [ 6.908433] RBP: 0000000000000000 R08: 0000000000000004 R09: 0000000000000001 [ 6.908437] R10: ffff9a0a8adcb258 R11: 0000000000000000 R12: 0000000000000001 [ 6.908440] R13: 0000000000000001 R14: ffff9a0a8738be00 R15: ffff9a0a874e20c8 [ 6.908443] FS: 0000000000000000(0000) GS:ffff9a0ded000000(0000) knlGS:0000000000000000 [ 6.908448] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 6.908451] CR2: ffff9a11fffff000 CR3: 00000003cd410001 CR4: 0000000000770ef0 [ 6.908455] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 6.908457] DR3: 0000000000000000 DR6: 00000000ffff07f0 DR7: 0000000000000400 [ 6.908460] PKRU: 55555554 [ 6.908462] Call Trace: [ 6.908465] <TASK> [ 6.908470] ? show_trace_log_lvl+0x1c4/0x2df [ 6.908484] ? show_trace_log_lvl+0x1c4/0x2df [ 6.908492] ? msi_capability_init+0x193/0x280 [ 6.908501] ? pci_msi_setup_msi_irqs+0x27/0x40 [ 6.908509] ? __warn+0x7e/0xd0 [ 6.908519] ? pci_msi_setup_msi_irqs+0x27/0x40 [ 6.908527] ? report_bug+0x100/0x140 [ 6.908537] ? handle_bug+0x3c/0x70 [ 6.908545] ? exc_invalid_op+0x14/0x70 [ 6.908551] ? asm_exc_invalid_op+0x16/0x20 [ 6.908561] ? pci_msi_setup_msi_irqs+0x27/0x40 [ 6.908569] msi_capability_init+0x193/0x280 [ 6.908577] __pci_enable_msi_range+0x1a3/0x230 [ 6.908586] pci_alloc_irq_vectors_affinity+0xc3/0x110 [ 6.908594] pcie_port_enable_irq_vec+0x3f/0x250 [ 6.908604] ? __pci_set_master+0x31/0xd0 [ 6.908614] pcie_portdrv_probe+0xdf/0x300 [ 6.908620] local_pci_probe+0x4c/0xa0 [ 6.908627] work_for_cpu_fn+0x13/0x20 [ 6.908635] process_one_work+0x194/0x380 [ 6.908643] worker_thread+0x2fe/0x410 [ 6.908649] ? __pfx_worker_thread+0x10/0x10 [ 6.908655] kthread+0xdd/0x100 [ 6.908665] ? __pfx_kthread+0x10/0x10 [ 6.908673] ret_from_fork+0x29/0x50 [ 6.908686] </TASK> [ 6.908688] ---[ end trace 0000000000000000 ]--- Change-Id: Ib015b002f2c077f50d48c046513504bdbd5b35aa Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84315 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-23soc/intel/xeon_sp/ibl: Remove unused logicsJincheng Li
Change-Id: I79b08630753b3aceb94becc8b9d682a3d3ca8310 Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84308 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Alicja Michalska <ahplka19@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-10-23soc/intel/xeon_sp/ibl: Update registers for reach bootableShuo Liu
Change-Id: Id2a2946b7fdfd7fd245835afe6abc9a3f7e1a508 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Co-authored-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-10-23soc/intel/xeon_sp: Add Kconfig SUPPORT_SIMICS_SIMULATIONShuo Liu
Xeon-SP simics doesn't provide simulation of writable PAM-F (Programmable Attribute Map) segment and hence coreboot needs to enable SHADOW_ROM_TABLE_TO_EBDA to write system table pointers to EBDA (Extended BIOS Data Area). Change-Id: I216204987ad646a5d1655323d2725cfd3415a2d7 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-10-23soc/intel/pantherlake: Update PlatformDebugOption to Trace ReadyJamie Ryu
This enables SOC_INTEL_DEBUG_CONSENT to set PlatformDebugOption to Trace Ready to have the safe configurations for Panther Lake ES SoC. This safe configuration will be removed once the feature is fully verified and safe to be set to the default value. BUG=b:373915085 TEST=Build fatcat and check the platform boots without an issue. Change-Id: I1eaabcb2e2aaff16ee4e64d1c7709b229de18459 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84823 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com>
2024-10-22soc/intel/alderlake_n: Fix display flicker issue when using internal FIVRSimon Yang
If project set configure_ext_fivr = 0 will cause PchFivrVccstIccMaxControl do not set correctly. BUG=b:361831628 TEST=Verified on Teliks360 that affected DUTs. Change-Id: I816de9c0c507aad3b73ab29e9f72048704f4662d Signed-off-by: Simon Yang <simon1.yang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84812 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2024-10-21soc/intel: Use NEM+ effective way size for for ADL, MTL and PTLJeremy Compostella
Alder Lake, Meteor Lake and Panther Lake use the effective way size when setting up the Enhanced No-Eviction Mode (cf. `INTEL_CAR_ENEM_USE_EFFECTIVE_WAY_SIZE'). BUG=b:360332771 TEST=Verified on PTL Intel reference platform Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521b Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83947 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Jayvik Desai <jayvik@google.com>
2024-10-21soc/intel/common/block/cpu: Add Kconfig for effective way size for NEM+Jeremy Compostella
On Alder Lake, Meteor Lake and Panther Lake platforms the way size to consider for NEM+ computation is the effective way size. On Alder Lake, the External Design Specification #627270 "3.5.2 No-Eviction Mode (NEM) Sizes" provides a way to compute the effective way size by reading the number of CBO. Unfortunately, reading the number of CBO is not possible on Meteor Lake and Panther Lake. Therefore, we instead compute the effective way size as the biggest of power of two of the way size which works across all three platforms. The Kconfig `INTEL_CAR_ENEM_USE_EFFECTIVE_WAY_SIZE' is introduced to control this behavior. The issue addressed by this commit can be observed with the following experiment: using a 18 MB LLC SKU, set `DCACHE_RAM_SIZE` to 0x400000 (4 MB). The number of ways that used to be computed is round(0x400000 / 0x180000) = round(2.66) = 3. 3 ways were mapped to cover the 0x400000 NEM+ region. When the bootblock code accesses memory between 3 MB and 4 MB, the core would raise a page fault exception. The right computation is: 0x400000 / eff_way_size(0x180000) = 4. 4 ways needs to be mapped to cover the entire 0x400000 NEM+ region. BUG=b:360332771 TEST=Verified on PTL Intel reference platform Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521c Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-10-18soc/xeon_sp: Initially add N-1 IBL codesShuo Liu
N-1 IBL (Integrated Boot Logic) codes are initially forked from EBG (Emmitsburg PCH) codes (src/soc/intel/xeon_sp/ebg). N-1 IBL codes are a set of stub codes to fulfill build sanity check for GNR SoC and CRB codes before the formal codes are published. Change-Id: I6bd5a2ed973ff91750c5ed1f9a57d30e41d8b97e Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-10-16soc/intel/xeon_sp: Allow Memory POR independent of RMTNaresh Solanki
TEST=Build & boot in IBM SBP1 system. Verified the settings are effective in FSP logs. Change-Id: I4341ead89a2683f64c834a6981ba316fcfef4f9a Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84741 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-10-14soc/intel/*: Add debug prints for misaligned FSP and driver settingsSean Rhodes
Print a warning when the FSP UPD for CNVi Audio Offload is enabled without the corresponding USB ACPI driver being enabled. Throw an error when the USB ACPI driver is enabled without the corresponding UPD being enabled. Change-Id: I449c43998dd379dc68a33db47a2fe51cfe5cda2f Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-10-11soc/intel/xeon_sp: Revise IIO domain ACPI name encodingShuo Liu
GNR/SRF supports up to 18 logical IIO stacks. Revise IIO domain ACPI name encoding in below form to support GNR/SRF, prefix (16 bit) | socket (3-bit) | stack (5-bit) Change-Id: I6f4c3c22980f2797dd47c8e0d684e0a3175030b7 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-10-11soc/intel/alderlake: Fix PEG0 IRQ routingSean Rhodes
PEG0 should be set to PCI_INT_D, not PCI_INT_A. This fixes: pcieport 0000:00:06.0: can't derive routing for PCI INT D pcieport 0000:00:06.0: PCI INT D: not connected PEG1 should also be PCI_INT_B. Tested on `starbook_adl` with Ubuntu 24.04 by running SSD benchmark with GNOME disks and suspend. Change-Id: I0f37bb9ac8572d7335084a20fceca6977a491498 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84619 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-11soc/intel/cnvi: Add CNIP MethodSean Rhodes
This method is used to provision the CNVi, and ensure that it is in the correct state. Intel document #559910 details this. Change-Id: Id8a36a09c7beaf3ba8b29d3276bd9dc59420dab5 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83713 Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-11soc/intel/cnvi: Add CFLR MethodSean Rhodes
This method is used to limit frequencies on CNVi. Intel document #559910 details this. Change-Id: Idc4c35e71076fd31786212995472bb8d58c961de Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83712 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
2024-10-11soc/intel/cnvi: Add power related methodsSean Rhodes
Only the _PRR method is used here, however, _PS0, _PS3 and _DSW must exist to avoid a BSOD on Windows. Change-Id: Ib4a1a8a76ce74b991a3e8686e9594c2c2b145a39 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
2024-10-11soc/intel/cnvw: Add GPEH MethodSean Rhodes
Add a general purpose handle to allow CNVi to be notified of state changes. Intel document #559910 details this. Change-Id: I36c98c525c99fb2b7b5ebd8b0e392e6626e97290 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83710 Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-11soc/intel/cnvi: Add PRR method for CNVi ResetSean Rhodes
Add a _PRR method that the OS can use to reset the wireless. This is only used for integrated solutions and depends on the CNMT Mutex that's created with `drivers/usb/acpi`. Whilst new ACPI is added, the behavior of existing boards won't be changed unless they configure the accompanying Bluetooth device. Intel document #559910 details this. Change-Id: I25e8462780badcad88b13052a6eb282c83af5def Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
2024-10-11soc/intel/cnvi: Add _S0W to ensure CNVi isn't put into D3 ColdSean Rhodes
All CNVi modules, integrated or dedicated only support D3 Hot so add _S0W to limit the sleep state. Intel document #559910 details this. Change-Id: I1541cebc022adc927a9cd883500320e9ef82359f Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
2024-10-11soc/intel/cnvi: Add CWAR FieldsSean Rhodes
These fields are used to monitor events on CNVi. Intel document #559910 details this. Change-Id: I3c1efc039e929ad1eeb8a0dd7c176e370e502e0c Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83709 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
2024-10-11soc/intel/cnvi: Add CNVW OpRegionSean Rhodes
The CNVi driver is relatively basic in coreboot and most noticeably, recent Linux kernels flag that lack of a _PRR method, which is used to reset WiFi and Bluetooth. This patch series adds methods recommended by Intel in document #559910. This patch defines an OpRegion for CNVi, for both integrated and dedicated solutions. Change-Id: Idd2ff93fb65c40f656804d96966e1881202ccb56 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-10-11soc/intel/cannonlake: Hook up CNVi Bluetooth UPDs to devicetreeSean Rhodes
Hook up CNVi Bluetooth UPDs to the devicetree. Set CnviBtCore to `true` so the current behaviour is not changed. Change-Id: Ic5640c23af3ce30498be814a6d7ce56988653b25 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84596 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-09soc/intel/{tigerlake,alderlake}: Correct FSP config rather than assertingSean Rhodes
Meteor Lake handles a misconfigured devicetree better than Alder Lake and Tiger Lake; it throws a warning and corrects the FSP config rather than asserting. Copy that behavior to Alder Lake and Tiger Lake. Change-Id: Ifd768fc31a0a6ef2fa0ae7e890cf0b47a9968d30 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84647 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
2024-10-09drivers/usb/acpi: Move the CNMT Mutex to USBSean Rhodes
The Intel Bluetooth driver can be combined with either CNVi, or full PCI wireless cards such as the AX210. Move it to the USB code so it can be used by either or. Change-Id: Ib456b1870501182b2d8788e5d53bbf4d7981f91b Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84627 Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-07soc/intel/cannonlake: Add missing USB port aliasesMaxim Polyakov
FSP for Comet Lake S allows one to configure 16 USB2 (PortUsb20Enable array) ports and 10 USB3 (PortUsb30Enable array) ports [1, 2]. [1] src/soc/intel/cannonlake/chip.h [2] 3rdparty/fsp/CometLakeFspBinPkg/CometLakeS/Include/FspsUpd.h Change-Id: Ie69543f335be1a69cf0c068335c2e17eebf4c6a9 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-10-07soc/intel/cannonlake/fsp_params: Rename FSP_S_CONFIG variableMatt DeVillier
All newer Intel SoCs use `s_cfg` as the variable name for a FSP_S_CONFIG struct pointer, so use that for CNL as well to avoid copy/paste errors when applying changes across SoCs which touch the FSP_S_CONFIG struct. Change-Id: I5eadb77f312ad6ad1072bc02adf98d97b1940236 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84653 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-07soc/intel/adl to jsl: Explicitly include static.h for config_of_socNicholas Chin
As per commit 865173153760 ("sconfig: Move config_of_soc from device.h to static.h"), sources that require access to the devicetree should directly include static.h so that it can be removed from device.h, eliminating unnecessary dependencies on static.h for files that only need the types and function declarations in device.h. Change-Id: I03e42689487c6d63436d9c2945558073aae87cd1 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84586 Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-07soc/intel/alderlake: Hook up PCIe Power Management to option APISean Rhodes
Hook up PCIEXP_CLK_PM, PCIEXP_ASPM and PCIEXP_L1_SUBSTATE to the option API. This provides users an easy way to disable power saving options that can limit performance. Change-Id: I2b06a7c734a4fd4073e86c668742ee35e1d79956 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81906 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-05soc/intel/pantherlake: Add FSP-S programmingJeremy Compostella
FSP-S UPDs are programmed according to the configuration (Kconfig and device tree) in ramstage. BUG=348678529 TEST=Hardware is programmed as desired and Intel Panther Lake reference board boots to UI. Change-Id: Iea26d962748116fa84afdb4afcba1098a64b6989 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84552 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-10-03soc/intel/pantherlake: Remove soc_info.[hc] interfaceJeremy Compostella
This commit removes the unnecessary layer provided by soc_info.[hc]. It was providing an abstraction which only was resulting in extra function calls without any added value as the returned constants are well identified and could be used directly. More importantly, and this is the actual selling point in my opinion, this extra indirection was preventing the compiler from detecting array overflows. BUG=348678529 TEST=Build is successful Change-Id: Iea26d962748116fa84afdb4afcba1098a64b6986 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-10-02soc/intel/cannonlake,skylake: Fix locking SMRAMMichał Żygowski
Intel TXT SINIT required the D_LCK bit set. Although coreboot tries to set it, the bit ws still clear. The D_LCK bit has to be set using I/O CF8/CFC cycle. TEST=Boot Linux with tboot on Protectli VP4670 with Intel TXT enabled Change-Id: I03aff482b53ab7b0bcaccf18e47ad4c22b53583c Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: coreboot org <coreboot.org@gmail.com>
2024-10-02soc/intel/meteorlake: Correctly set Usb4CmModeSean Rhodes
The ACPI is adjusted based on SOFTWARE_CONNECTION_MANAGER, so set the UPD to match this to avoid the connection type being mismatched. If it's mismatched, the TBT port will timeout. TEST=Boot starbook/rpl and check TBT 4 dock is correctly identified. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3ab68c01f682723dab39870f0676e59ae3d89add Reviewed-on: https://review.coreboot.org/c/coreboot/+/77567 Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-10-02soc/intel/xeon_sp: Use MemoryMapDataHob to add high RAM resourcesShuo Liu
On GNR, there are CXL Type-3 memory windows covered under TOHM. The current 4GB to TOHM DRAM reporting doesn't work on GNR. Use MemoryMapDataHob to add high RAM resources as a generic mechanism for GNR and previous generation SoCs. TEST=Build and boot on intel/archercity CRB TEST=Build and boot on intel/beechnutcity CRB (with topic:"Xeon6-Basic-Boot") Change-Id: Ie5fbc5735704d95c7ad50740ff0e35737afdbd80 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84304 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-02soc/intel/pantherlake: Delete duplicated lineJeremy Compostella
BUG=348678529 TEST=Build successful Change-Id: Iea26d962748116fa84afdb4afcba1098a64b6987 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84607 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-02soc/intel: Deprecate SoC-specific global reset status configsSubrata Banik
This change removes the SoC-specific `FSP_STATUS_GLOBAL_RESET_REQUIRED_X` Kconfigs, as they are no longer necessary for handling FSP global reset requests. Previously, these Kconfigs were used to select a specific 32-bit reset status code. However, with the introduction of FSP 2.4 and 64-bit interfaces, the global reset status code can now vary between architectures. To address this, the FSP driver now sets the `FSP_STATUS_GLOBAL_RESET` config to a common default value (depending upon most commonly used global reset status code) based on the interface: - 0x40000003 for 32-bit FSP interfaces - 0x4000000000000003 for 64-bit FSP interfaces This default can be overridden if an FSP implementation uses a different status code (for example: Apollo Lake selects different FSP reset status code as 0x40000005). By removing the SoC-specific configurations, this change simplifies global reset handling and ensures compatibility across different FSP versions and platforms. Below table shows the relationship between Platform, FSP and FSP Global Reset Status: +-----------------+--------------+-------------------------+ | Platform | FSP | Global Reset Status | +-----------------+--------------+-------------------------+ | Alder Lake | 32-bit | 0x40000003 | +-----------------+--------------+-------------------------+ | Apollo Lake | 32-bit | 0x40000005 | +-----------------+--------------+-------------------------+ | Cannon Lake | 32-bit | 0x40000003 | +-----------------+--------------+-------------------------+ | Elkhart Lake | 32-bit | 0x40000003 | +-----------------+--------------+-------------------------+ | Jasper Lake | 32-bit | 0x40000003 | +-----------------+--------------+-------------------------+ | Meteor Lake | 32-bit | 0x40000003 | +-----------------+--------------+-------------------------+ | Sky Lake | 32-bit | 0x40000003 | +-----------------+--------------+-------------------------+ | Tiger Lake | 32-bit | 0x40000003 | +-----------------+--------------+-------------------------+ | Panther Lake | 64-bit | 0x4000000000000003 | +-----------------+--------------+-------------------------+ BUG=b:347669091 TEST=Verified FSP requested global reset functionality on google/rex0 (32-bit) and google/rex64 (64-bit) platforms. w/ 32-bit FSP: ``` (Wdt) AllowKnownReset [FspResetSystem2] FSP Reset Initiated FSP returning control to Bootloader with reset required return status 40000003 FSPS, status=0x40000003 FSP: handling reset type, status=0x40000003 GLOBAL RESET! global_reset() called! HECI: Global Reset(Type:1) Command ``` w/ 64-bit FSP: ``` (Wdt) AllowKnownReset [FspResetSystem2] FSP Reset Initiated FSP returning control to Bootloader with reset required return status 3 FSPS, status=0x4000000000000003 FSP: handling reset type, status=0x4000000000000003 GLOBAL RESET! global_reset() called! HECI: Global Reset(Type:1) Command ``` Change-Id: I32bdbf7ea6afa7d5e5f91ea96d887719d26a593f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84572 Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com>
2024-10-01soc/intel: Correct return type of fsp_get_pch_reset_status()Subrata Banik
The `fsp_get_pch_reset_status()` function returns a FSP reset status code. This change corrects its return type from `uint32_t` to `efi_return_status_t` to ensure consistency with the FSP API and prevent potential issues caused by type mismatch. This correction is necessary for compatibility with both 32-bit and 64-bit FSP interfaces. The change also updates all callers of this function in the Meteor Lake and Panther Lake SoCs to use the correct return type. Includes `fsp/api.h` to provide the `efi_return_status_t` definition. BUG=b:347669091 TEST=Verified global reset functionality on google/rex0 (32-bit) and google/rex64 (64-bit) platforms. Change-Id: I0cdee541506bf424f50fd00833d5ee200a3a8a48 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84571 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-01soc/intel/common/cnvi: Add CNMT MutexSean Rhodes
Add "CNMT" Mutex, that will be used by the Bluetooth and CNVi driver. Change-Id: I607865458f925d6f4aa713e07cfa34e83b2e5c8f Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84598 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-01soc/intel/cannonlake: Fix USB port numbersMaxim Polyakov
It should be in HEX. Change-Id: I15a354bae414ad94a2f76030b3099179022b935c Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84546 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-01tree: Use boolean for dptf_enableElyes Haouas
Change-Id: Ic6e578199e7e4ca3a014eecb1eb7a4d9d24893b8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84161 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-30soc/intel/common: systemagent: Fix typo in HAVE_BDSM_BGSM_REGISTER help textPaul Menzel
regist*re*s → regist*er*s Change-Id: Ie5f5cb481f0fac335e592fd3f1f56d5462e37c1e Fixes: 2b0b2ef9a258 ("soc/intel/common/systemagent: select CAPID_A, BDSM and BGSM by Kconfig") Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
2024-09-28soc/intel/pantherlake: Add FSP-M programmingJeremy Compostella
FSP-M UPDs are programmed according to the configuration (Kconfig and device tree). BUG=348678529 TEST=Memory is initialized successfully and hardware is programmed as desired on Intel pantherlake reference board. Change-Id: Iea26d962748116fa84afdb4afcba1098a64b6988 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84443 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-27soc/intel/pantherlake: Comply with the no typedef coding style ruleJeremy Compostella
As https://doc.coreboot.org/contributing/coding_style.html#typedefs states: "In general, a pointer, or a struct that has elements that can reasonably be directly accessed should never be a typedef". This commit makes the Intel Panther Lake SoC code comply with this by using explicitly `struct soc_intel_pantherlake_config' in the soc/intel/pantherlake code as I have been suggested to for the `fsp_params.c' files. The rule being the rule and consistency across a project matters more than personal preferences. The documentation lists five exceptions and none on them cover the use of `config_t' instead `struct soc_intel_pantherlake' but I believe it does not make the code better for the following three reasons: 1. It is repetitive, make the line longer and the code is in soc/intel/pantherlake so obviously the config_t data structure is the pantherlake soc configuration. 2. It makes re-usability from one generation to another unnecessarily harder. 3. This config_t abstraction is required for and used by some common block code anyway. Hence, we end-up with some code using `config_t' and other using the final structure which break the consistency of the code when the project in looked as a whole. BUG=348678529 TEST=Google fatcat mainboard compiles Change-Id: Ibe382615db1a7c7a0841d8fe4ae43c226e2c2021 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2024-09-27driver/intel/ish: Add config to indicate the presence of ISH MAIN firmwareJayvik Desai
This commit introduces a new config DRIVER_INTEL_ISH_HAS_MAIN_FW to indicate that the Intel Sensor Hub (ISH) is using the ISH MAIN firmware. The ISH MAIN firmware is located in rootfs, hence we no longer need to store the ISH BUP version in the CSE partition. When this config is enabled, fetching the ISH BUP version from the CSE firmware partition is skipped. BUG=b:360144613 TEST=Local build successful and tested on trulo by toggling the config. Enabling this config skips printing the ISH version in cbmem. Change-Id: I6cacf7b44ce6895ecb96db295d184c7b7d5a872c Signed-off-by: Jayvik Desai <jayvik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84493 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-09-26soc/intel/ptl: Remove tcss_d3_hot_disable en config structure fieldJeremy Compostella
This commit drops tcss_d3_hot_disable chip config as FSP is not exposing the same purpose UPD anymore starting with Panther Lake SoC. BUG=b:348678529 TEST=Build for fatcat Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d58 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Pranava Y N <pranavayn@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2024-09-25ssoc/intel/tigerlake: Use boolean for enable_c6dramElyes Haouas
"enable_c6dram" needs only 2 "states" to be clearly defined. C provides "true/false", so use it instead of using unsigned int. Change-Id: Icff1b42ceb2e89cc0b2e7abab6743430c635db7b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84155 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-24soc/intel/xeon_sp: Support GNR PCIe root portsShuo Liu
Add device IDs for GNR PCIe root ports so that these devices can be supported by the Xeon-SP PCIe root port driver. Change-Id: I450c0088aa2e3be60489becf0600f534ea90d7a4 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84311 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-24soc/intel/xeon_sp/gnr: Enable VMX by FSPJohnny Lin
Configure FSP UPD VMX from Kconfig ENABLE_VMX. Change-Id: I0c03f535b6f93761419657127e791c02e8ee4988 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84327 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-24soc/intel/xeon_sp/gnr: Remove duplicated HPET tableLu, Pen-ChunX
Both lpc.c and chip.c will create HPET table. remove hpet_device_ops for avoiding create two HPET table. Change-Id: I32628e98b5c1fac4b72ea3abf755b62847161bec Signed-off-by: Lu, Pen-ChunX <pen-chunx.lu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-09-24soc/intel/xeon_sp/gnr: Implement SMM methodsJincheng Li
Change-Id: I578b2c213ff1b33b4ca37e0422f690bedc9f5ba1 Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84325 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-24soc/intel/common/block/lpc: Support IBL eSPIShuo Liu
IBL eSPI should be correctly configured by LPC driver so that console input is usable. Change-Id: I77cc6dd67b36035974e7f268d32b8473e8d83483 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-09-24soc/intel/meminit: Check array sizeArthur Heymans
Work around a GCC LTO bug. Even if no buffer overflow is bound to happen as the soldered down path is taken GCC LTO complains about this. Change-Id: Ib3d4ed8032bb06b6d08fbc2dc4b697df88745243 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-23soc/intel/pantherlake: Disable Total Memory EncryptionJamie Ryu
TME, Total Memory Encryption will be enabled once the feature is fully verified with Panther Lake. Change-Id: I600c8a499df3b8796df35813422d0e89f67cc630 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84418 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-09-21soc/intel/ptl: Remove usb2_port_reset_msg_en config structure fieldJeremy Compostella
Similarly to what is done in Meteor Lake, the PortResetMessageEnable UPD can be set based on usb2_port[].type_c setting and therefore usb2_port_reset_msg_en is not necessary. BUG=b/348678529 TEST=Build for fatcat Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d57 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84429 Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-21soc/intel/ptl: Provide the TCSS port policy setting optionsJeremy Compostella
Each TCSS port can be associated a setting via the tcss_cap_policy device tree field. The setting can be picked within five values listed by this commit. BUG=b/348678529 TEST=fatcat board build tcss_cap_policy[0]=TCSS_TYPE_C_PORT_FULL_FUN Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d56 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-20soc/intel/common/block/acpi: Fix GPE1 blocks to ACPI FADT tableCliff Huang
Use CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 to add GPE1 block rather than checking if GPE1_STS(0) is '0'. BUG:362310295 TEST=with the flag, boot google/fatcat or intel/ptlrvp to OS and check that FADT table includes GPE1. FADT should have: GPE1 Block Address : 00001810 GPE1 Block Length : 18 GPE1 Base Offset : 80 Without the flag, boot to OS and check that FADT table does not include GPE1. FADT should have: GPE1 Block Address : 0 GPE1 Block Length : 0 GPE1 Base Offset : 0 Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Idd8115044faff3161ea6bd1cae6c0fe8aa0ff8d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-19soc/intel/mtl: Hook up GMA ACPI brightness controlsJeremy Soller
Add function needed to generate ACPI backlight control SSDT, along with Kconfig values for accessing the registers. Change-Id: Ied08e5e9fe4913bd60474ed7dcf88b945172558d Signed-off-by: Jeremy Soller <jeremy@sysetm76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-09-19soc/intel/common/block/acpi: exclude DMI fixed memory range if no DMICliff Huang
In newer SOC, such as PTL, there is no DMI. Exclude DMI memory range in northbridge.asl if DMI_BASE_SIZE is '0' BUG=b:348678529 TEST=Build CB with DMI_BASE_SIZE set to '0' in the SOC directory. Boot to OS and check ACPI PDRC device from the ACPI DSDT table. There should not have an entry for DMI in its _CRS method. Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I971af2eb214b5940fa09d9dc0f9717bb5f0dfb4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/84349 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-19soc/intel/ehl/fsp_params: Do not re-enable 'PchPwrOptEnable' for real-time ↵Mario Scheithauer
tuning If real-time tuning was enabled, 'PchPwrOptEnable' was set two times with different values. This patch fixes the issue. BUG=none TEST=Enabled FSP UPD debug output and checked 'PchPwrOptEnable' offset Change-Id: I2f31015c1da51a4ae1b8d5226f5d7b60a6023f3d Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84399 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-18soc/intel: Move CSE update ELOG to cse_lite.cSubrata Banik
The ELOG for CSE updates was being added in fsp_params.c, but the actual update happens in cse_lite.c. This commit moves the ELOG to cse_lite.c to more accurately reflect where the event is happening. This also removes the need for a sol_type variable in meteorlake/romstage/fsp_params.c. It also helps to avoid redundant ELOG event entry while performing CSE update (due to CSE RO to RW switch dependency). BUG=b:361253028 (Multiple CSE sync elog prints for Nissa/Trulo) TEST=Able to see only one instance of ELOG while performimg CSE sync. w/o this patch: elogtool list 0 | Log area cleared | 4088 1 | Kernel Event | Clean Shutdown 2 | Early Sign of Life | MRC Early SOL Screen Shown 3 | Early Sign of Life | CSE Sync Early SOL Screen Shown 4 | System boot | 29 5 | Memory Cache Update | Normal | Success 6 | Early Sign of Life | CSE Sync Early SOL Screen Shown w/ this patch: elogtool list 0 | Log area cleared | 4088 1 | Early Sign of Life | MRC Early SOL Screen Shown 2 | Memory Cache Update | Normal | Success 3 | System boot | 30 4 | Memory Cache Update | Normal | Success 5 | Early Sign of Life | CSE Sync Early SOL Screen Shown Change-Id: I37fe3f097e581f79bf67db1ceb923f10ce651d62 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Jakub Czapiga <czapiga@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com>
2024-09-18soc/intel/ptl: Add SoC ACPI directory for Panther LakeRavi Sarawadi
List of changes: 1. Select common ACPI Kconfig to include common ACPI code block from IA-common code 2. Select ACPI Kconfig support for wake-up from sleep states. 3. Add SoC ASL code for SoC IPs like IPU, HDA etc. 4. PTL replaces DMI3 with SAF to ensure common/block/acpi/acpi/northbridge.asl binding with PTL change, #if DMI_BASE_SIZE guard check is added in northbridge.asl 5. include GPIO ASL that supports new pinctrl schema. BUG=b:348678529 TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f15 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-17soc/intel/alderlake: Enable CRASHLOG for Chrome OSSubrata Banik
Enable the CRASHLOG config option for Chrome OS boards. This allows the Chrome OS crash reporter to collect and analyze crash dumps, aiding in debugging and improving system stability. TEST=Able to build and boot google/brox Change-Id: Ia23ef1cbebdba9a3b724204eb25ee788afa3e8fd Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-09-17Revert "soc/intel/meteorlake: Skip the TCSS D3 cold entry sequence"Subrata Banik
This reverts commit 88a496a9c81ba6447a4c1453a45d09ee79f30309. This workaround is not valid with the latest Intel PRQ silicon, so I'm dropping it now. Additionally, able to boot to ChromeOS without any hang, and I also ran an S0ix cycle without any failures. BUG=b:244082753 TEST=Able to boot google/rex0 to CrOS. Change-Id: Idf0da5841705888d2787f61dd6e6fada2fbe3e3e Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84368 Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-14mainboard/intel/avenuecity_crb: Update full IIO configurationShuo Liu
Change-Id: I88baa159475ac57ec6a2a638ab84f76a6af4fe82 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84318 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-13mb/google/brox: Fix booting to kernel without batterySowmya Aralguppe
When battery is disconnected and only adaptor is connected higher PL2 power draw causes cpu brown out and system does not boot to kernel. To avoid this set Boot frequency UPD to 1. Reduce PL4 value to overcome power spikes from SoC during boot. Remove Psys implementation as it impacts active state platform performance. BUG=b:335046538,b:329722827 BRANCH=None TEST=Able to successfully boot on 3 different Brox proto2 SKU1 and SKU2 boards with 65W, 45W and 30W adaptors for 3 iterations of cold boot. Change-Id: I58e136c607ea9290ecac0cee453d6632760a6433 Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-09-13soc/intel/xeon_sp/gnr: Support full IIO UPD configurationsShuo Liu
Change-Id: Iebfadffd2da83992af983b8c0dfe2706f81eb728 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84317 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-13soc/intel/xeon_sp/gnr: Move CPU ID definition to common headerJincheng Li
Change-Id: I816c6f68840c122fbc37085e31a1b0368a819f4a Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84313 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-13soc/intel/xeon_sp/gnr: Enlarge MAX_CPUS to 512Jincheng Li
GNR-AP supports up-to 128 cores/256 threads per socket. Enlarge MAX_CPUS to 512 = 128*2*2 with 2 socket configuration considered. Change-Id: I8dc46dcdd3ca1c3ddfa47fbb28912a2c6e4c46fa Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84312 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-13soc/intel/xeon_sp/gnr: Use default DCACHE_BSP_STACK_SIZEGang Chen
For Xeon-SP, DCACHE_BSP_STACK_SIZE is by default 0x10000. For GNR, this default size is enough. Use the default size so that more CAR spaces could be saved for other purpose. Change-Id: I68a79df150c4954ef8d703987d7c0bb446ba4cda Signed-off-by: Gang Chen <gang.c.chen@intel.com> Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84302 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-13soc/intel/ptl: Do initial Panther Lake SoC commit till ramstageSaurabh Mishra
List of changes: 1. Add required SoC programming till ramstage. 2. Include only required headers into include/soc. 3. Skeleton code used to call FSP-S API. BUG=b:348678529 TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Change-Id: I61930726ad0c765bfa1d72c5df893262be884834 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84332 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-13soc/intel/cmn/block/cpu: Simplify calculation of non-eviction waysSubrata Banik
The calculation of non-eviction ways (used for cache-as-ram configuration) has been simplified by removing conditional move instructions and directly adding the remainder to the quotient. This achieves the same ceiling operation but with potentially improved efficiency (less instructions). No functional changes are expected. TEST=Able to build and boot google/rex. Change-Id: I7cf5ff19ec440d049edc3bf52c660dea96b1f08a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-09-11soc/intel/raptorlake: Fall back to Intel microcode repoFelix Singer
With the release 20240910 of the Intel microcode repository, it also includes the updated microcode file with version 0x129, which makes the one from the coreboot blobs repo superfluous. Thus, use the one from the Intel repository again. Change-Id: I7fb58874719a8373072419e34b3f8923f7db927d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84295 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-11soc/intel/cml, pci_ids: Remove IDs of non-existent graphics devicesMaxim Polyakov
These identifiers are not included in the GPU list from Intel [1]. At the same time, 0x9B44 is not PCI DID of graphics device at all: 8086:9B44 - 10th Gen Core Processor Host Bridge/DRAM Registers [2]. [1] https://web.archive.org/web/20240731152818/https:// dgpu-docs.intel.com/devices/hardware-table.html [2] https://web.archive.org/web/20231004011832/https://devicehunt.com/ view/type/pci/vendor/8086/device/9B44 Change-Id: I8ff7b062f930cb63ffd9caf240874742bd53fc23 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-09-11tree: Use boolean for dmi_power_optimize_disableElyes Haouas
Change-Id: Ifbe76bd69d847603345a4a1fa4f41e529634fa92 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84158 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-10intel/alderlake: Order Kconfig selectors for FSP pathsNico Huber
Should make the sorting order of the paths more obvious. Change-Id: Ie73e717f37f80a11a903e99cc094ea4d76e1ca1f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83827 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-10intel/alderlake: Drop redundant Client/AlderLake* FSP pathsNico Huber
The Alder Lake "Client" FSP paths have been replaced by symlinks to Raptor Lake in the FSP repo. Hence we get the same files anyway and can spare us to maintain the individual paths. Change-Id: Ia9b256ce1940894e2cf31acaa4a83ea39f6723b6 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-09-09intel/alderlake: Sort FSP paths, most specific selectors firstNico Huber
The `!FSP_USE_REPO` is most specific, if we're not using the FSP repo, we can ignore all the FSP-repo paths. Hence put these first. Having `FSP_TYPE_IOT` selected is also more specific, we can ignore all the "Client" paths then. This makes sure that we don't catch a "Client" by accident (otherwise we'd have to add a `!FSP_TYPE_IOT` for those). Change-Id: Ibe9931d8f964a337c46fde31a3bc22c69d40eded Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2024-09-09soc/intel/xeon_sp: Reserve MMIO high rangeShuo Liu
Xeon-SP supports MMIO high range, a.k.a. MMIO range above 4G. FSP will assign domain MMIO high windows from this range. However, there will be unassigned parts among these high windows for non-domain device usage (e.g. misc devices belonging to an IIO stack but not belonged to any PCIe domains under that stack). This will cause segmentation in MTRR UC coverage. For example, in SPR-XCC where only CPM0/HQM0 are supported and instantiated to PCIe domains, MMIO ranges are still reserved for CPM1/HQM1. See more at src/soc/intel/xeon_sp/spr/ioat.c. Reserve MMIO high range as a whole under domain0/00:0.0. During MTRR calculation, this reservation will connect the discontinued domain MMIO high windows together to form one continuous range, and save MTRR register usage from inadequacy. This change is initially raised for SPR but could be effective for GNR as well. TESTED = Build and boot in intel/archercity CRB, MTRR register usage decreases from 7 to 3 in 2S system. TESTED = Only setting MTRR for below 4GB ranges test fails with LinuxBoot on SPR (through x86_setup_mtrrs_with_detect_no_above_4gb) tsc: Detected 2000.000 MHz processor last_pfn = 0x2080000 max_arch_pfn = 0x10000000000 x86/PAT: Configuration [0-7]: WB WC UC- UC WB WP UC- WT WARNING: BIOS bug: CPU MTRRs don't cover all of memory, losing 129024MB of RAM. ------------[ cut here ]------------ WARNING: CPU: 0 PID: 0 at arch/x86/kernel/cpu/mtrr/cleanup.c:978 mtrr_trim_uncached_memory+0x2b9/0x2f9 ... Call Trace: ? 0xffffffff8f600000 ? setup_arch+0x4bb/0xaed ? printk+0x53/0x6a ? start_kernel+0x55/0x507 ? load_ucode_intel_bsp+0x1c/0x4d ? secondary_startup_64_no_verify+0xc2/0xcb random: get_random_bytes called from init_oops_id+0x1d/0x2c with crng_init=0 ---[ end trace 0e56686fd458f0c5 ]--- update e820 for mtrr modified physical RAM map: modified: [mem 0x0000000000000000-0x0000000000000fff] reserved ... modified: [mem 0x00000000ff000000-0x000000207fffffff] reserved last_pfn = 0x6354e max_arch_pfn = 0x10000000000 Memory KASLR using RDRAND RDTSC... x2apic: enabled by BIOS, switching to x2apic ops Using GB pages for direct mapping ... Initmem setup node 0 [mem 0x0000000000001000-0x000000006354dfff] DMA zone: 28769 pages in unavailable ranges DMA32 zone: 19122 pages in unavailable ranges BUG: unable to handle page fault for address: ff24b56eba60cff8 BAD Oops: 0000 [#1] SMP NOPTI CPU: 0 PID: 0 Comm: swapper Tainted: G W 5.10.50 #2 ... Call Trace: ? set_pte_vaddr_p4d+0x24/0x35 ? __native_set_fixmap+0x21/0x28 ? map_vsyscall+0x35/0x56 ? setup_arch+0xa00/0xaed ? printk+0x53/0x6a ? start_kernel+0x55/0x507 ? load_ucode_intel_bsp+0x1c/0x4d ? secondary_startup_64_no_verify+0xc2/0xcb CR2: ff24b56eba60cff8 ---[ end trace 0e56686fd458f0c6 ]--- RIP: 0010:fill_pud+0xa/0x62 ... Kernel panic - not syncing: Attempted to kill the idle task! ---[ end Kernel panic - not syncing: Attempted to kill the idle task! ]--- Change-Id: Ib2a0e1f1f13e797c1fab6aca589d060c4d3fa15b Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83538 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-09-07soc/intel/ptl: Add GPIOs for Panther Lake SOCCliff Huang
Add definitions for the GPIO pins on Panther Lake SoC, as well as GPIO IRQ routing information and defines for ACPI ASL. For now, add the following GPIO communities and GPIO groups: Comm. 0: GPP_V, GPP_C Comm. 1: GPP_F, GPP_E Comm. 3: CPUJTAG, GPP_H, GPP_A, VGPIO3 Comm. 4: GPP_S Comm. 5: GPP_B, GPP_D, VGPIO ref doc: - PT EDS vol2 - Panther Lake H GPIO Implementation Summary (#817954) BUG=b:348678529 TEST=Verify on Intel Silicon platform for PTL using google/fatcat mainboard. Note that these GPIO changes cannot be verified along as they are merely data structure and defines for the SOC. With the GPIO ASL, we should see the following GPIO instances under /sys/bus/acpi/devices when booting to OS: INTC10BC:00/ INTC10BC:01/ INTC10BC:02/ INTC10BC:03/ INTC10BC:04/ Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Iae1bc072841214efaec7a10719dbc742f2da795b Reviewed-on: https://review.coreboot.org/c/coreboot/+/83789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-07soc/intel/{common,alderlake}: Add missing ADL-N SKUsMichał Żygowski
Based on DOC #767454 (public) version 1.2. Allows to boot the HARDKERNEL ODROID H4+ with N97 SoC. Without this patch the MCH ID was not recognized and the SA driver did not pick up the stolen ranges, causing the PCI MMIO allocation to be placed in the stolen areas. TEST=Boot HARDKERNEL ODROID H4+ with N97 SoC to Ubuntu 23.04. Change-Id: I0fbdb12c6411e4109e68a13960b4570701629bc9 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84212 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-16 03:36:49 +0000